IBM z15 (microprocessor)
|Max. CPU clock rate||5.2 GHz|
|L1 cache||128 KB I-L1|
128 KB D-L1
|L2 cache||4 MB I-L2|
4 MB D-L2
|L3 cache||256 MB|
|Architecture and classification|
|Min. feature size||14 nm|
The cache (e.g. level 3) is doubled from the previous generation z14, while the "L4 Cache increased from 672MB to 960MB, or +43%" with the new add-on chip System Controller (SC) SCM. Both it and all levels of cache in the main processor from level 1 use eDRAM, instead of the traditionally used SRAM. "A five-CPC drawer system has 4800 MB (5 x 960 MB) of shared L4 cache."
- IBM System z
- Mainframe computer
- "IBM z15 (z15)". https://www.ibm.com/downloads/cas/NN7GBPJ1.
- "IBM Unveils z15 With Industry-First Data Privacy Capabilities" (Press release). IBM. September 12, 2019.
- IBM z15 (8561) Technical Guide. September 2019. SG24-8851-00. https://www.redbooks.ibm.com/redpieces/pdfs/sg248851.pdf. Retrieved September 14, 2019.
Original source: https://en.wikipedia.org/wiki/ IBM z15 (microprocessor). Read more