View source for 128-bit

{{N-bit|128|(16 octets)}}
While there are currently no mainstream general-purpose processors built to operate on '''128-bit''' ''integers'' or addresses, a number of processors do have specialized ways to operate on 128-bit chunks of data. The IBM System/370 could be considered the first simple 128-bit computer, as it used 128-bit floating-point registers. Most modern CPUs feature [[Single instruction, multiple data|single-instruction multiple-data]] (SIMD) instruction sets ([[Streaming SIMD Extensions]], [[Engineering:AltiVec|AltiVec]] etc.) where 128-bit vector registers are used to store several smaller numbers, such as four 32-bit floating-point numbers. A single instruction can then operate on all these values in parallel. However, these processors do not operate on individual numbers that are 128 binary digits in length; only their [[Processor register|registers]] have the size of 128&nbsp;bits.

The DEC [[VAX]] supported operations on 128-bit integer ('O' or octaword) and 128-bit floating-point ('H-float' or HFLOAT) datatypes. Support for such operations was an upgrade option rather than being a standard feature. Since the VAX's registers were 32&nbsp;bits wide, a 128-bit operation used four consecutive registers or four longwords in memory.

The [[ICL 2900 Series]] provided a 128-bit accumulator, and its instruction set included 128-bit floating-point and packed decimal arithmetic.

In the same way that compilers emulate e.g. 64-bit integer arithmetic on architectures with register sizes less than 64 bits, some compilers also support 128-bit integer arithmetic. For example, the [[Software:GNU Compiler Collection|GCC C compiler]] 4.6 and later has a 128-bit integer type <code>__int128</code> for some architectures.<ref>{{cite web|title=GCC 4.6 Release Series - Changes, New Features, and Fixes|url=https://gcc.gnu.org/gcc-4.6/changes.html|access-date=25 July 2016}}</ref> For the C programming language, this is a compiler-specific extension, as [[C11 (C standard revision)|C11]] itself does not guarantee support for 128-bit integers.

A 128-bit register can store 2<sup>128</sup> (over 3.40 × 10<sup>38</sup>) different values. The range of [[Integer|integer]] values that can be stored in 128 bits depends on the [[Integer (computer science)#Value and representation|integer representation]] used. With the two most common representations, the range is 0 through 340,282,366,920,938,463,463,374,607,431,768,211,455 (2<sup>128</sup> − 1) for representation as an ([[Signedness|unsigned]]) [[Binary number|binary number]], and −170,141,183,460,469,231,731,687,303,715,884,105,728 (−2<sup>127</sup>) through 170,141,183,460,469,231,731,687,303,715,884,105,727 (2<sup>127</sup> − 1) for representation as [[Two's complement|two's complement]].

==Uses==
* The [[Free software|free software]] used to implement [[Engineering:RISC-V|RISC-V]] architecture is defined for 32, 64 and 128 bits of integer data width.
* Universally Unique Identifiers (UUID) consist of a 128-bit value.
* [[IPv6]] routes computer network traffic amongst a 128-bit range of addresses.
* [[ZFS]] is a 128-bit file system.
* GPU chips commonly move data across a 128-bit bus.<ref>{{ cite journal|url=http://www.tomshardware.com/reviews/graphics-beginners,1288-8.html | title= The Graphics Processor | publisher=tomshardware.com| author=Don Woligroski | date=July 2006 | accessdate=24 February 2013}}</ref>
* 128 bits is a common [[Social:Key size|key size]] for symmetric ciphers and a common block size for [[Block cipher|block cipher]]s in [[Cryptography|cryptography]].
* 128-bit processors could be used for addressing directly up to 2<sup>128</sup> (over 3.40 × 10<sup>38</sup>) bytes, which would greatly exceed the total data stored on Earth as of 2010, which has been estimated to be around 1.2 [[Zettabyte|zettabyte]]s (1.42 × 10<sup>21</sup> bytes).<ref>{{ cite journal|url=http://www.datacenterknowledge.com/archives/2010/05/04/digital-universe-nears-a-zettabyte/|title=Digital Universe nears a Zettabyte | publisher=datacenterknowledge.com| author=Rich Miller | journal=The Guardian | date=May 2010 | accessdate=16 September 2010}}</ref>
* Quadruple precision (128-bit) floating-point numbers can store 64-bit [[Fixed-point arithmetic|fixed point]] numbers or [[Integer (computer science)|integers]] accurately without losing [[Accuracy and precision|precision]].
* The AS/400 virtual instruction set defines all pointers as 128-bit. This gets translated to the hardware's real instruction set as required, allowing the underlying hardware to change without needing to recompile the software. Past hardware was 48-bit CISC, while current hardware is 64-bit [[PowerPC]]. Because pointers are defined to be 128-bit, future hardware may be 128-bit without software incompatibility.
* Increasing the word size can speed up [[Arbitrary-precision arithmetic|multiple precision]] mathematical libraries.  Applications include [[Cryptography|cryptography]], and potentially speed up algorithms used in complex mathematical processing ([[Numerical analysis|numerical analysis]], [[Signal processing|signal processing]], complex [[Photo manipulation|photo editing]] and [[Audio signal processing|audio]] and [[Engineering:Video processing|video processing]]).

* [[Software:Apache Avro|Apache Avro]] uses a 128-bit random number as synchronization marker for efficient splitting of data files.<ref>{{cite web |title=Compression Formats and Delimiter Sequences |url=https://stackoverflow.com/questions/38161285/compression-formats-and-delimiter-sequences |website=Stack Overflow |accessdate=20 June 2018}}</ref>

==History==
A 128-bit multicomparator was described by researchers in 1976.<ref>{{ cite journal|last1=Mead|first1=C.A.|last2=Pashley|first2=R.D.|last3=Britton|first3=L.D.|last4=Daimon|first4=Y.T.|last5=Sando|first5=S.F.|title=128-bit multicomparator|url=http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1050799|journal=IEEE Journal of Solid-State Circuits|volume=11|pages=692|year=1976| doi= 10.1109/JSSC.1976.1050799  }}</ref>

A CPU with 128-bit multimedia extensions was designed by researchers in 1999.<ref>{{Cite journal | last1 = Suzuoki | first1 = M. | last2 = Kutaragi | first2 = K. | last3 = Hiroi | first3 = T. | last4 = Magoshi | first4 = H. | last5 = Okamoto | first5 = S. | last6 = Oka | first6 = M. | last7 = Ohba | first7 = A. | last8 = Yamamoto | first8 = Y. | last9 = Furuhashi | first9 = M. | last10 = Tanaka | first10 = M. | last11 = Yutaka | first11 = T. | last12 = Okada | first12 = T. | last13 = Nagamatsu | first13 = M. | last14 = Urakawa | first14 = Y. | last15 = Funyu | first15 = M. | last16 = Kunimatsu | first16 = A. | last17 = Goto | first17 = H. | last18 = Hashimoto | first18 = K. | last19 = Ide | first19 = N. | last20 = Murakami | first20 = H. | last21 = Ohtaguro | first21 = Y. | last22 = Aono | first22 = A. | doi = 10.1109/4.799870 | title = A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder | journal = IEEE Journal of Solid-State Circuits | volume = 34 | issue = 11 | pages = 1608 | year = 1999 | pmid =  | pmc = }}</ref>

==References==
{{Reflist|30em}}

{{CPU technologies}}


[[Category:Data unit]]

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