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There are currently no mainstream general-purpose processors built to operate on 512-bit integers or addresses, though a number of processors do operate on 512-bit data. {{As of|2013}}, the [[Engineering:Xeon Phi|Intel Xeon Phi]] has a vector processing unit with 512-bit vector registers, each one holding sixteen 32-bit elements or eight 64-bit elements, and a single instruction can operate on all these values in parallel. However, the Xeon Phi's vector processing unit does not operate on individual numbers that are 512 bits in length.<ref>{{cite web|url=https://secure-software.intel.com/sites/default/files/article/334766/intel-xeon-phi-systemsoftwaredevelopersguide.pdf|title=Intel® Xeon PhiTM Coprocessor System Software Developers Guide|publisher=[[Company:Intel|Intel]]|date=November 8, 2012|accessdate=February 8, 2013}}</ref>

==Uses==
[[File:Sapphire Radeon R9 290X-front oblique PNr°0437.jpg|thumb|The AMD Radeon R9 290X (Sapphire OEM version pictured here) uses a 512 bit memory bus]]
* Some GPUs such as the [[Company:Nvidia|Nvidia]] GTX280,<ref>{{cite web|url=http://www.geforce.com/hardware/desktop-gpus/geforce-gtx-280/specifications |title=GTX 280 &#124; Specifications |publisher=GeForce |date= |accessdate=2013-08-13}}</ref> GTX285,<ref>{{cite web|url=http://www.geforce.com/hardware/desktop-gpus/geforce-gtx-285/specifications |title=GTX 285 &#124; Specifications |publisher=GeForce |date= |accessdate=2013-08-13}}</ref> Quadro FX 5800<ref>{{cite web|url=http://www.nvidia.com/object/product_quadro_fx_5800_us.html |title=NVIDIA® Quadro® FX 5800 provides professionals with visual supercomputing from their desktops delivering results that push visualization beyond traditional 3D |publisher=Nvidia.com |date= |accessdate=2013-08-13}}</ref> and several [[Engineering:Nvidia Tesla|Tesla]] products move data across a 512-bit memory bus. Then AMD Radeon R9 290, R9 290X and 295X2 followed.
* Many hash functions, such as SHA-512, have a 512-bit output.
* [[AVX-512]] are 512-bit extensions to the 256-bit [[Advanced Vector Extensions]] SIMD instructions for x86 [[Instruction set architecture|instruction set architecture]] proposed by Intel in July 2013, and released on 2016 with [[Engineering:Xeon Phi#Knights Landing|Knights Landing]], and in 2018 on the HEDT and consumer server platform, with Skylake-X and [[Skylake (microarchitecture)#"Skylake-SP" (14 nm) Scalable Performance|Skylake-SP]] respectively.

==References==
{{reflist}}

{{CPU technologies}}

[[Category:Data unit]]

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