View source for CPUID

In the [[X86|x86]] architecture, the '''CPUID''' instruction (identified by a <code>CPUID</code> [[Opcode|opcode]]) is a processor supplementary instruction (its name derived from "[[Central processing unit|CPU]] Identification") allowing software to discover details of the processor. It was introduced by [[Company:Intel|Intel]] in 1993 with the launch of the [[Engineering:Pentium|Pentium]] and [[Engineering:I486|late 486]] processors.<ref>{{cite web|url=http://www.intel.com/design/processor/manuals/253668.pdf |title=Intel 64 and IA-32 Architectures Software Developer's Manual |publisher=Intel.com |access-date=2013-04-11}}</ref>

A program can use the <code>CPUID</code> to determine processor type and whether features such as [[MMX (instruction set)|MMX]]/[[Streaming SIMD Extensions|SSE]] are implemented.

== History ==
Prior to the general availability of the <code>CPUID</code> instruction, programmers would write esoteric [[Machine code|machine code]] which exploited minor differences in CPU behavior in order to determine the processor make and model.<ref>{{cite web|url=http://www.rcollins.org/ddj/Sep96/Sep96.html |title=Detecting Intel Processors - Knowing the generation of a system CPU |publisher=Rcollins.org |access-date=2013-04-11}}</ref><ref>{{cite web |url=http://lxr.linux.no/source/arch/i386/kernel/head.S?v=1.2.13#L92 |archive-url=https://archive.today/20120713012856/http://lxr.linux.no/source/arch/i386/kernel/head.S?v=1.2.13%23L92 |url-status=dead|title=LXR linux-old/arch/i386/kernel/head.S |publisher=Lxr.linux.no |access-date=2013-04-11 |archive-date = 2012-07-13}}</ref><ref name="debs_cpuident"/><ref>B-CoolWare, [https://www.sac.sk/download/utildiag/cpu215.zip TMi0SDGL] x86 CPU/FPU detection library with source code, v2.15, June 2000 - see /SOURCE/REALCODE.ASM for a large collection of pre-CPUID x86 CPU detection routines. [https://web.archive.org/web/20230314185852/https://www.sac.sk/download/utildiag/cpu215.zip Archived] on 14 Mar 2023.</ref> With the introduction of the 80386 processor, EDX on reset indicated the revision but this was only readable after reset and there was no standard way for applications to read the value.

Outside the x86 family, developers are mostly still required to use esoteric processes (involving instruction timing or CPU fault triggers) to determine the variations in CPU design that are present.

For example, in the [[Motorola 68000 series]] — which never had a <code>CPUID</code> instruction of any kind — certain specific instructions required elevated privileges. These could be used to tell various CPU family members apart. In the [[Engineering:Motorola 68010|Motorola 68010]] the instruction ''MOVE from SR'' became privileged. Because the [[Engineering:Motorola 68000|68000]] offered an unprivileged ''MOVE from SR'' the two different CPUs could be told apart by a CPU error condition being triggered.

While the <code>CPUID</code> instruction is specific to the x86 architecture, other architectures (like ARM) often provide on-chip registers which can be read in prescribed ways to obtain the same sorts of information provided by the x86 <code>CPUID</code> instruction.

== Calling CPUID ==
The <code>CPUID</code> opcode is <code>0F A2</code>.

In [[Assembly language|assembly language]], the <code>CPUID</code> instruction takes no parameters as <code>CPUID</code> implicitly uses the EAX register to determine the main category of information returned. In Intel's more recent terminology, this is called the CPUID leaf. <code>CPUID</code> should be called with <code>EAX = 0</code> first, as this will store in the EAX register the highest EAX calling parameter (leaf) that the CPU implements.

To obtain extended function information <code>CPUID</code> should be called with the most significant bit of EAX set. To determine the highest extended function calling parameter, call <code>CPUID</code> with <code>EAX = 80000000h</code>.

CPUID leaves greater than 3 but less than 80000000 are accessible only when the [[Model-specific register|model-specific register]]s have IA32_MISC_ENABLE.BOOT_NT4 [bit 22] = 0 (which is so by default). As the name suggests, [[Software:Windows NT 4.0|Windows NT 4.0]] until SP6 did not boot properly unless this bit was set,<ref>{{cite web|url=https://software.intel.com/en-us/forums/topic/306523?language=en#comment-1590394 |title=CPUID, EAX=4 - Strange results (Solved) |publisher=Software.intel.com |access-date=2014-07-10}}</ref> but later versions of Windows do not need it, so basic leaves greater than 4 can be assumed visible on current Windows systems. {{As of|April 2024}}, basic valid leaves go up to 23h, but the information returned by some leaves are not disclosed in the publicly available documentation, i.e. they are "reserved".

Some of the more recently added leaves also have sub-leaves, which are selected via the ECX register before calling <code>CPUID</code>.

== EAX=0: Highest Function Parameter and Manufacturer ID ==

This returns the CPU's manufacturer ID string{{snd}}a twelve-character [[ASCII]] string stored in EBX, EDX, ECX (in that order). The highest basic calling parameter (the largest value that EAX can be set to before calling <code>CPUID</code>) is returned in EAX.

Here is a list of processors and the highest function implemented.

{| class="wikitable"
|+ Highest Function Parameter
! Processors || Basic || Extended
|-
|| Earlier [[Engineering:Intel 80486|Intel 486]] || colspan=2 | ''CPUID Not Implemented''
|-
|| Later Intel 486 and [[Engineering:Pentium|Pentium]] || 0x01 || ''Not Implemented''
|-
|| [[Engineering:Pentium Pro|Pentium Pro]], [[Engineering:Pentium II|Pentium II]] and [[Engineering:Celeron|Celeron]] || 0x02 || ''Not Implemented''
|-
|| [[Engineering:Pentium III|Pentium III]] || 0x03 || ''Not Implemented''
|-
|| [[Engineering:Pentium 4|Pentium 4]] || 0x02 || 0x8000 0004
|-
|| [[Engineering:Xeon|Xeon]] || 0x02 || 0x8000 0004
|-
|| [[Engineering:Pentium M|Pentium M]] || 0x02 || 0x8000 0004
|-
|| Pentium 4 with Hyper-Threading || 0x05 || 0x8000 0008
|-
|| [[Engineering:Pentium D|Pentium D]] (8xx) || 0x05 || 0x8000 0008
|-
|| Pentium D (9xx) || 0x06 || 0x8000 0008
|-
|| [[Engineering:Intel Core#Core 2 Duo|Core Duo]] || 0x0A || 0x8000 0008
|-
|| [[Engineering:Intel Core#Core 2 Duo|Core 2 Duo]] || 0x0A || 0x8000 0008
|-
|| Xeon [[Engineering:List of Intel Nehalem-based Xeon microprocessors#Xeon 3000-series (uniprocessor)|3000]], 5100, 5200, 5300, 5400 ([[Engineering:List of Intel Nehalem-based Xeon microprocessors#Xeon 5000-series (dual-processor)|5000 series]]) || 0x0A || 0x8000 0008
|-
|| Core 2 Duo [[Engineering:Wolfdale (microprocessor)#Wolfdale|8000 series]] || 0x0D || 0x8000 0008
|-
|| Xeon 5200, 5400 series || 0x0A || 0x8000 0008
|-
|| [[Engineering:Intel Atom|Atom]] || 0x0A || 0x8000 0008
|-
|| [[Engineering:Nehalem (microarchitecture)|Nehalem]]-based processors || 0x0B || 0x8000 0008
|-
|Ivy Bridge-based processors
|0x0D
|0x8000 0008
|-
|[[Skylake (microarchitecture)|Skylake]]-based processors (proc base & max freq; Bus ref. freq)
|0x16
|0x8000 0008
|-
|[[System on a chip|System-On-Chip]] Vendor Attribute Enumeration Main Leaf
|0x17
|0x8000 0008
|-
|[[Engineering:Meteor Lake|Meteor Lake]]-based processors
|0x23
|0x8000 0008
|}

The following are known processor manufacturer ID strings:
* <code>"AuthenticAMD"</code>{{snd}}[[Company:Advanced Micro Devices|AMD]]
* <code>"CentaurHauls"</code>{{snd}}[[Company:Integrated Device Technology|IDT]] WinChip/[[Company:Centaur Technology|Centaur]] (Including some VIA and Zhaoxin CPUs)
* <code>"CyrixInstead"</code>{{snd}}[[Company:Cyrix|Cyrix]]/early [[Company:STMicroelectronics|STMicroelectronics]] and [[Company:IBM|IBM]]
* <code>"GenuineIntel"</code>{{snd}}[[Company:Intel|Intel]]
* <code>"GenuineIotel"</code>{{snd}}Intel (rare)<ref>{{Cite tweet |user=InstLatX64 |number=1101230794364862464 |title=First encounter with "GenuineIotel" (o after I, instead of n)}}</ref><ref>{{Cite web |website=instlatx64 |title=GenuineIotel CPUID dump for Intel Xeon E3-1231 |url=http://users.atw.hu/instlatx64/GenuineIotel/GenuineIotel00306C3_Haswell_CPUID5.txt |archive-url=https://web.archive.org/web/20191207082343/http://users.atw.hu/instlatx64/GenuineIotel/GenuineIotel00306C3_Haswell_CPUID5.txt |archive-date=7 December 2019 |url-status=live}}</ref>
* <code>"TransmetaCPU"</code>{{snd}}[[Company:Transmeta|Transmeta]]
* <code>"GenuineTMx86"</code>{{snd}}[[Company:Transmeta|Transmeta]]
* <code>"Geode by NSC"</code>{{snd}}[[Company:National Semiconductor|National Semiconductor]]
* <code>"NexGenDriven"</code>{{snd}}[[Company:NexGen|NexGen]]
* <code>"RiseRiseRise"</code>{{snd}}[[Company:Rise Technology|Rise]]
* <code>"SiS SiS SiS "</code>{{snd}}[[Company:Silicon Integrated Systems|SiS]]
* <code>"UMC UMC UMC "</code>{{snd}}[[Company:United Microelectronics Corporation|UMC]]
* <code>"Vortex86 SoC"</code>{{snd}}DM&P [[Vortex86]]
* <code>"{{spaces|2}}Shanghai{{spaces|2}}"</code>{{snd}}<!--using spaces template in order to make clearer that the intent here is to display two consecutive spaces that should not be collapsed to one, because that's what's actually present in the Zhaoxin and RDC ID strings--> [[Company:Zhaoxin|Zhaoxin]]
* <code>"HygonGenuine"</code>{{snd}}[[Engineering:AMD–Chinese joint venture|Hygon]]
* <code>"Genuine{{spaces|2}}RDC"</code>{{snd}}RDC Semiconductor Co. Ltd.<ref>instlatx64, [http://users.atw.hu/instlatx64/Genuine__RDC/Genuine%20%20RDC0000586_RDC_CPUID.txt CPUID dump for RDC IAD 100]. Retrieved 22 December 2022. [https://web.archive.org/web/20191205235603/http://users.atw.hu/instlatx64/Genuine__RDC/Genuine%20%20RDC0000586_RDC_CPUID.txt Archived] on 5 Dec 2019.</ref>
* <code>"E2K MACHINE "</code>{{snd}}[[Engineering:Elbrus (computer)|MCST Elbrus]]<ref name="inxi197_elbrus">smxi, [https://codeberg.org/smxi/inxi/issues/197 Inxi issue 197: Elbrus CPU support data and implementation]. Retrieved 23 October 2023. [https://web.archive.org/web/20231023190035/https://codeberg.org/smxi/inxi/issues/197 Archived] on 23 October 2023.</ref>
* <code>"VIA VIA VIA "</code>{{snd}}[[Company:VIA Technologies|VIA]] * <code>"AMD ISBETTER"</code>{{snd}}early engineering samples of [[Engineering:AMD K5|AMD K5]] processor<ref>Grzegorz Mazur, [https://web.archive.org/web/19970524043213/http://grafi.ii.pw.edu.pl/gbm/x86/cpuid.html Identification of x86 CPUs with CPUID support], 5 May 1997. Archived from the [http://grafi.ii.pw.edu.pl:80/gbm/x86/cpuid.html original] on 24 May 1997.</ref><ref>Ingo Böttcher, [https://groups.google.com/g/fido.ger.pascal/c/Hy8JY6JqO_o/m/0Xv22DWi6TAJ CPUDET.PAS v1.61], 23 Oct 1996 - CPU identification program that tests for "AMD ISBETTER" string. [https://web.archive.org/web/20240426153142/https://groups.google.com/g/fido.ger.pascal/c/Hy8JY6JqO_o/m/0Xv22DWi6TAJ Archived] on 26 Apr 2024.</ref> <!-- A variation of this string - "AMDisbetter!" - was added to the CPUID article on 15 Nov 2006, but no citation was provided, and unlike "AMD ISBETTER", there doesn't seem to exist any sources for "AMDisbetter!" that pre-date the Nov 15 addition or otherwise can be clearly traced back to a non-Wikpedia source. Citing any of the occurrences on e.g. GitHub risks citogenesis. -->

The following are ID strings used by open source soft CPU cores:
* <code>"GenuineAO486"</code>{{snd}}ao486 CPU (old)<ref>{{cite web |last=sorgelig |date=Aug 3, 2017 |title=ao486 CPUID instruction (in commit 43a2004) |url=https://github.com/MiSTer-devel/ao486_MiSTer/blob/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/commands/CMD_CPUID.txt |url-status=live |archive-url=https://web.archive.org/web/20231204102715/https://github.com/MiSTer-devel/ao486_MiSTer/blob/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/commands/CMD_CPUID.txt |archive-date=2023-12-04 |access-date=2023-12-04 |website=[[GitHub]]}}</ref><ref name=":1">{{Cite web |last=sorgelig |date=Aug 30, 2020 |title=Update cpuid. · MiSTer-devel/ao486_MiSTer@82f5014 |url=https://github.com/MiSTer-devel/ao486_MiSTer/commit/82f5014bb44356e256a9c5454e8810d43a9990f1 |url-status=live |archive-url=https://web.archive.org/web/20231204102456/https://github.com/MiSTer-devel/ao486_MiSTer/commit/82f5014bb44356e256a9c5454e8810d43a9990f1 |archive-date=2023-12-04 |access-date=2023-12-04 |website=GitHub |language=en}}</ref>
* <code>"MiSTer AO486"</code>{{snd}}ao486 CPU (new)<ref>{{cite web |last=sorgelig |date=Aug 30, 2020 |title=ao486 CPUID instruction |url=https://github.com/MiSTer-devel/ao486_MiSTer/blob/master/rtl/ao486/commands/CMD_CPUID.txt |url-status=live |archive-url=https://web.archive.org/web/20231023063725/https://github.com/MiSTer-devel/ao486_MiSTer/blob/master/rtl/ao486/commands/CMD_CPUID.txt |archive-date=October 23, 2023 |access-date=4 Dec 2023 |website=[[GitHub]] }}</ref><ref name=":1" />
* <code>"GenuineIntel"</code>{{snd}}v586 core<ref>{{cite web |title=v586: 586 compatible soft core for FPGA |website=[[GitHub]]|date=6 December 2021|url=https://github.com/valptek/v586}}</ref> (this is identical to the Intel ID string)

The following are known ID strings from virtual machines:<!-- Virtual machine IDs that are returned through CPUID leaf 40000000h should be listed under that leaf, not leaf 0. Also, the "MicrosoftXTA" and "VirtualApple" CPU vendor strings show up in the "Steam Hardware & Software Survey", but Steam doesn't actually state that these strings are in fact taken from CPUID.(EAX=0) vendor strings, and there doesn't seem to exist any other source that corroborates that these strings are ever actually returned by Microsoft x86-to-ARM or Apple Rosetta 2 for CPUID.(EAX=0), so comment these out for now. "VirtualApple" does show up in the brand name string returned by CPUID.(EAX=80000002) on Rosetta 2, but not for CPUID.(EAX=0).
* <code>"MicrosoftXTA"</code>{{snd}}Microsoft x86-to-ARM<ref>{{Cite web |title=Steam Hardware & Software Survey |url=https://store.steampowered.com/hwsurvey/processormfg?sort=chg |access-date=2022-07-26 |website=store.steampowered.com}}</ref>
* <code>"VirtualApple"</code>{{snd}}Newer versions of Apple Rosetta 2 -->
* <code>"ConnectixCPU"</code>{{snd}}Connectix [[Software:Virtual PC|Virtual PC]] (version 6 and lower)<ref>Peter Ferrie, [https://pferrie.tripod.com/papers/attacks2.pdf Attacks on More Virtual Machine Emulators], page 5. [https://web.archive.org/web/20100215194824/https://pferrie.tripod.com/papers/attacks2.pdf Archived] on 15 Feb 2010.</ref><ref name="singh_virtualpc">Amit Singh, [https://web.archive.org/web/20041210031247/http://www.kernelthread.com/mac/vpc/misc.html#Solaris Miscellaneous], see Solaris section. Archived from the [http://www.kernelthread.com/mac/vpc/misc.html#Solaris original] on 10 Dec 2004.</ref>
* <code>"Virtual CPU "</code>{{snd}}Microsoft Virtual PC 7;<ref name="singh_virtualpc"/> Microsoft x86-to-ARM (32-bit x86)<ref name="mihocka_2024">Darek Mihocka, [http://emulators.com/docs/abc_exit_xta.htm#Probing_CPUID ARM64 Boot Camp: Understanding x86/x64 Emulation on Windows on ARM], 28 Jan 2024, see "Probing CPUID" section. [https://web.archive.org/web/20240224200718/http://emulators.com/docs/abc_exit_xta.htm#Probing_CPUID Archived] on 24 Feb 2024.</ref>
* <code>"AuthenticAMD"</code>{{snd}}Microsoft x86-to-ARM (64-bit x86)<ref name="mihocka_2024"/>
* <code>"GenuineIntel"</code>{{snd}}[[Software:Rosetta|Apple Rosetta 2]]<ref>{{cite web| url = https://cpufun.substack.com/p/fun-with-timers-and-cpuid| title = Fun with Timers and cpuid - by Jim Cownie - CPU fun| date = 3 March 2021 |archive-url=https://web.archive.org/web/20210303122337/https://cpufun.substack.com/p/fun-with-timers-and-cpuid |archive-date = 3 March 2021 |url-status=live}}</ref>
* <code>"Insignia 586"</code>{{snd}}Insignia RealPC<ref>Insignia Solutions, [https://web.archive.org/web/20151128001710/http://macintoshgarden.org/sites/macintoshgarden.org/files/manuals/realpcuserguide.p RealPC Installation and User’s Guide], 1997, p. 71. Archived from the [http://macintoshgarden.org/sites/macintoshgarden.org/files/manuals/realpcuserguide.pdf original] on 28 Nov 2015.</ref><ref>Philippe Geneste, [https://groups.google.com/g/fr.comp.sys.mac/c/HedttDQgP9U/m/pz1jT7CaHgoJ (INFO) Emulation PC sur Mac] (in French), 21 Jan 1998. [https://web.archive.org/web/20250624104454/https://groups.google.com/g/fr.comp.sys.mac/c/HedttDQgP9U/m/pz1jT7CaHgoJ Archived] on 24 Jun 2025.</ref> and SoftWindows 98<ref>Insignia Solutions, [https://web.archive.org/web/20151125180704/http://macintoshgarden.org/sites/macintoshgarden.org/files/manuals/SoftWindows_User_Guide.pdf SoftWindows 98 Installation and User's Guide], 1998, p. 127. Archived from the [http://macintoshgarden.org/sites/macintoshgarden.org/files/manuals/SoftWindows_User_Guide.pdf original] on 25 Nov 2015.</ref>
* <code>"Compaq FX!32"</code>{{snd}}Compaq FX!32 (x86 emulator for [[DEC Alpha]] processors)<ref>VOGONS discussion thread [http://www.vogons.org/viewtopic.php?f=46&t=68756&start=780#p1000298 "SIV support for 386/486/586 class + Alpha CPUs and 3dfx + S3 + SiS + Matrox + XGI + old ATI + NVidia GPUs - Testing Help", post by lolo799 on 2021-09-12 17:10] — see SIV32L attachments for a screenshot and a CPUID dump listing the {{nowrap|<code>"Compaq FX!32"</code>}} string. [https://web.archive.org/web/20240519154442/http://www.vogons.org/viewtopic.php?f=46&t=68756&start=780#p1000298 Archived] on 19 May 2024.</ref>
* <code>"PowerVM Lx86"</code>{{snd}}[[Software:PowerVM Lx86|PowerVM Lx86]] (x86 emulator for IBM [[Engineering:POWER5|POWER5]]/[[Engineering:POWER6|POWER6]] processors)<ref>virt-what source tree, [http://git.annexia.org/?p=virt-what.git;a=blob;f=tests/lx86/proc/cpuinfo;h=9da5dca2c754ff95c6f3d3ef96da0e6fa24aeb34;hb=82c0e9c469953a36f18db1e329629cecd950134a tests/lx86/proc/cpuinfo] - PowerVM Lx86 cpuinfo dump. [https://web.archive.org/web/20241110183018/http://git.annexia.org/?p=virt-what.git;a=blob;f=tests/lx86/proc/cpuinfo;h=9da5dca2c754ff95c6f3d3ef96da0e6fa24aeb34;hb=82c0e9c469953a36f18db1e329629cecd950134a Archived] on 10 Nov 2024.</ref>
* <code>"Neko Project"</code>{{snd}}Neko Project II ([[Engineering:PC-98|PC-98]] emulator) (used when the CPU to emulate is set to "Neko Processor II")<ref>Neko Project 21/W, [https://simk98.github.io/np21w/help/cfgdlg.html help/configure] (in Japanese). [https://web.archive.org/web/20240922124350/https://simk98.github.io/np21w/help/cfgdlg.html Archived] on 22 Sep 2024.</ref><ref>CPU-World, [https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=82924 CPUID for emulated Neko Project CPU] with "Neko Project" string. [https://web.archive.org/web/20251116031810/https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=82924 Archived] on 16 Nov 2025.</ref>
{{vpad}}
For instance, on a <code>GenuineIntel</code> processor, values returned in EBX is <code>0x756e6547</code>, EDX is <code>0x49656e69</code> and ECX is <code>0x6c65746e</code>. The following example code displays the vendor ID string as well as the highest calling parameter that the CPU implements.

<syntaxhighlight lang="nasm" line="1">
	.intel_syntax noprefix
	.text
.m0: .string "CPUID: %x\n"
.m1: .string "Largest basic function number implemented: %i\n"
.m2: .string "Vendor ID: %s\n"

    .globl main

main:
	push    r12
	mov	    eax, 1
	sub	    rsp, 16
    cpuid
    lea	    rdi, .m0[rip]
	mov	    esi, eax
	call	printf
	xor     eax, eax
    cpuid
	lea	    rdi, .m1[rip]
	mov	    esi, eax
	mov	    r12d, edx
	mov	    ebp, ecx
	call    printf
	mov     3[rsp], ebx
	lea	    rsi, 3[rsp]
    lea	    rdi, .m2[rip]
    mov     7[rsp], r12d
    mov     11[rsp], ebp
	call	printf
	add	    rsp, 16
	pop	    r12
	ret

    .section .note.GNU-stack,"",@progbits

</syntaxhighlight>

On some processors, it is possible to modify the Manufacturer ID string reported by CPUID.(EAX=0) by writing a new ID string to particular MSRs ([[Model-specific register]]s) using the <code>WRMSR</code> instruction. This has been used on non-Intel processors to enable features and optimizations that have been disabled in software for CPUs that don't return the <code>GenuineIntel</code> ID string.<ref>iXBT Labs, [http://ixbtlabs.com/articles3/cpu/via-nano-cpuid-fake-p1.html VIA Nano CPUID Tricks], Aug 26, 2010. [https://web.archive.org/web/20100829072405/http://ixbtlabs.com/articles3/cpu/via-nano-cpuid-fake-p1.html Archived] on Aug 29, 2010.</ref> Processors that are known to possess such MSRs include:
 
{| class="wikitable"
|+ Processors with Manufacturer ID MSRs
! Processor || MSRs
|-
| IDT WinChip || <code>108h-109h</code><ref>IDT, [https://www.ardent-tool.com/CPU/docs/IDT_Centaur/WinChip2/wc_2_datasheet_a2.pdf WinChip 2A data sheet], v1.0, Jan 1999, page A-3.</ref>
|-
| [[Engineering:VIA C3|VIA C3]], [[Engineering:VIA C7|C7]] || <code>1108h-1109h</code><ref>VIA, [http://datasheets.chipdb.org/VIA/Nehemiah/VIA%20C3%20Nehemiah%20Datasheet%20R113.pdf C3 Nehemiah Datasheet], rev 1.13, Sep 29, 2004, page A-3.</ref>
|-
| VIA Nano || <code>1206h-1207h</code><ref>Agner Fog, [http://www.agner.org/optimize/cpuidfake.zip CpuIDFake, v1.00], Jan 22, 2010, see "Instructions.txt". [https://web.archive.org/web/20100709200509/http://www.agner.org/optimize/cpuidfake.zip Archived] on Jul 9, 2010.</ref>
|-
| [[Engineering:Transmeta Crusoe|Transmeta Crusoe]], [[Engineering:Transmeta Efficeon|Efficeon]] || <code>80860001h-80860003h</code><ref name="transmeta_msr">Transmeta, [http://datasheets.chipdb.org/Transmeta/Crusoe/TM5900/tm5900_bisoguide_040123.pdf Crusoe BIOS Programmer's Guide], Jan 23, 2004, pages 63-65.</ref><ref>Transmeta, Efficeon BIOS Programmers Guide, Aug 19, 2003, section 8.3, page 148.</ref>
|-
| AMD [[Engineering:Geode (processor)|Geode]] GX, LX || <code>3000h-3001h</code><ref>AMD, [https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/33234H_LX_databook.pdf Geode LX Data Book], pub.id. 33234H, Feb. 2009, page 107. [https://web.archive.org/web/20231203113022/https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/33234H_LX_databook.pdf Archived] on Dec 3, 2023.</ref>
|-
| DM&P [[Vortex86]]EX2 || <code>52444300h-52444301h</code><ref>DM&P, [https://www.vortex86.com/downloads/Vortex86EX2 Vortex86EX2_A9133_Master_Data_Sheet_V11_BF], May 8, 2019, page 72.</ref>
|}
{{vpad}}

== EAX=1: Processor Info and Feature Bits ==

This returns the CPU's stepping, model, [[Microarchitecture|microarchitecture]] codename, and family information in register EAX (also called the ''signature'' of a CPU), feature flags in registers EDX and ECX, and additional feature info in register EBX.<ref>{{cite book |author=<!--Staff writer(s); no by-line.--> |chapter-url=https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4 |chapter-format=PDF |title=Intel 64 and IA-32 Architectures Software Developer's Manual |chapter=Chapter 3 Instruction Set Reference, A-L |publisher=Intel Corporation  |date=2018-12-20 |access-date=2018-12-20}}</ref>

{| class="wikitable" style="margin-left: auto; margin-right: auto; border: none;"
|+ CPUID EAX=1: Processor Version Information in EAX
|-
! colspan="32" | EAX
|-
! style="width: 75px" | 31
! style="width: 75px" | 30
! style="width: 75px" | 29
! style="width: 75px" | 28
! style="width: 75px" | 27
! style="width: 75px" | 26
! style="width: 75px" | 25
! style="width: 75px" | 24
! style="width: 75px" | 23
! style="width: 75px" | 22
! style="width: 75px" | 21
! style="width: 75px" | 20
! style="width: 75px" | 19
! style="width: 75px" | 18
! style="width: 75px" | 17
! style="width: 75px" | 16
! style="width: 75px" | 15
! style="width: 75px" | 14
! style="width: 75px" | 13
! style="width: 75px" | 12
! style="width: 75px" | 11
! style="width: 75px" | 10
! style="width: 75px" | 9
! style="width: 75px" | 8
! style="width: 75px" | 7
! style="width: 75px" | 6
! style="width: 75px" | 5
! style="width: 75px" | 4
! style="width: 75px" | 3
! style="width: 75px" | 2
! style="width: 75px" | 1
! style="width: 75px" | 0
|- style="text-align: center"
| colspan="4" style="background: lightgrey" | Reserved
| colspan="8" | Extended Family ID
| colspan="4" | Extended Model ID
| colspan="2" style="background: lightgrey" | Reserved
| colspan="2" | Processor Type
| colspan="4" | Family ID
| colspan="4" | Model
| colspan="4" | Stepping ID
|}

* Stepping ID is a product revision number assigned due to fixed errata or other changes.
* The actual processor model is derived from the Model, Extended Model ID and Family ID fields. If the Family ID field is either 6 or 15, the model is equal to the sum of the Extended Model ID field shifted left by 4 bits and the Model field. Otherwise, the model is equal to the value of the Model field.
* The actual processor family is derived from the Family ID and Extended Family ID fields. If the Family ID field is equal to 15, the family is equal to the sum of the Extended Family ID and the Family ID fields. Otherwise, the family is equal to the value of the Family ID field.
* The meaning of the Processor Type field is given in the table below.

{| class="wikitable"
|+ Processor Type
|-
! Type
! Encoding in [[Binary number|Binary]]
|-
| Original equipment manufacturer ([[Finance:Original equipment manufacturer|OEM]]) Processor
| style="text-align: center" | 00
|-
| [[Engineering:Pentium OverDrive|Intel Overdrive Processor]]
| style="text-align: center" | 01
|-
| Dual processor (applicable to Intel [[Engineering:Pentium (original)|P5 Pentium]] processors only)<ref>Intel, [https://www.ardent-tool.com/CPU/docs/Intel/Pentium/241428-005.pdf Pentium Processor Family Developer's Manual], 1997, order no. 241428-005, sections 3.4.1.2 (page 91), 17.5.1 (page 489) and appendix A (page 522) provide more detail on how the "processor type" field and the "dual processor" designation work.</ref>
| style="text-align: center" | 10
|-
| Reserved value
| style="text-align: center" | 11
|}
{{vpad}}

As of October 2023, the following x86 processor family IDs are known:<ref>InstLatx64, [http://users.atw.hu/instlatx64/ x86, x64 Instruction Latency, Memory Latency and CPUID dumps], 30 Sep 2023.</ref>
{{sticky header}}
{| class="wikitable sortable sticky-header-multi"
|+ CPUID EAX=1: Processor Family IDs
! colspan=2 | Family ID +<br/>Extended Family ID !! rowspan=2 class="unsortable" | Intel !! rowspan=2 class="unsortable" | AMD !! rowspan=2 class="unsortable" | Other
|-
! class="unsortable" | hex !! class="unsortable" | dec
|-
! <code>0h</code> !! 0
| {{n/a}} || {{n/a}} || {{n/a}}
|-
! <code>1h</code> !! 1
| {{n/a}} || {{n/a}} || {{n/a}}
|-
! <code>2h</code> !! 2
| {{n/a}} || {{n/a}} || {{n/a}}
|-
! <code>3h</code> !! 3
| {{n/a|{{efn|The [[Engineering:I386|i386]] processor does not support the <code>CPUID</code> instruction - it does however return Family ID <code>3h</code> in the reset-value of EDX.}}}} || {{n/a}} || {{n/a}}
|-
! <code>4h</code> !! 4
| [[Engineering:I486|486]]
| [[Engineering:Am486|486]],<ref>AMD, [https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/20736.pdf Enhanced Am486DX Microprocessor Family], pub.no. 20736 rev B, March 1997, section 9.2.2, page 55. [https://web.archive.org/web/20231018093730/https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/20736.pdf Archived] on 18 Oct 2023.</ref><br/>[[Engineering:Am5x86|5x86]],<br/>[[Engineering:AMD Élan|Élan]] SC4xx/5xx<ref>AMD, [https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/user-guides/21030.pdf ÉlanSC400 and ÉlanSC410 Microcontrollers User's Manual], pub.no. 21030, 1997, section 3.6.2, page 73. [https://web.archive.org/web/20231018093705/https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/user-guides/21030.pdf Archived] on 18 Oct 2023.</ref>
| Cyrix 5x86,<ref>Cyrix, [http://www.bitsavers.org/components/cyrix/94246-00_5x86_CPU_BIOS_Writers_Guide_199510.pdf 5x86 BIOS Writers Guide], rev 1.12, order no. 92426-00, 1995, page 7</ref><br/>Cyrix [[Engineering:MediaGX|MediaGX]],<ref name="cyrix_detguide">Cyrix, [http://www.bitsavers.org/components/cyrix/appnotes/Cyrix_CPU_Detection_Guide_1997.pdf CPU Detection Guide], rev 1.01, 2 Oct 1997, page 6.</ref><br/>[[Engineering:UMC Green CPU|UMC Green CPU]],<ref name="debs_cpuident">Debbie Wiles, [https://web.archive.org/web/20040604002243/http://debs.future.easyspace.com/Programming/OS/cpuid.txt CPU Identification], archived on 2006-06-04</ref><br/>[[Company:MCST|MCST]] Elbrus (most models),<ref name="inxi197_elbrus" /><br/>[[Engineering:MiSTer|MiSTer]] ao486<ref>MiSTer ao486 source code, [https://github.com/MiSTer-devel/ao486_MiSTer/blob/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/defines.v rtl/ao486/defines.v], line 70. [https://web.archive.org/web/20231023193346/https://raw.githubusercontent.com/MiSTer-devel/ao486_MiSTer/43a20047d5e2e99f1264dadbdab777733ccbb61a/rtl/ao486/defines.v Archived] on 23 Oct 2023.</ref>
|-
! <code>5h</code> !! 5
| [[Engineering:Pentium (original)|Pentium]],<br/>Pentium MMX,<br/>[[Engineering:Intel Quark|Quark X1000]]
| [[Engineering:AMD K5|K5]],<br/>[[Engineering:AMD K6|K6]]
| [[Engineering:Cyrix 6x86|Cyrix 6x86]],<br/>Cyrix [[Engineering:MediaGX|MediaGX]]m,<ref name="cyrix_detguide" /><br/>[[Engineering:Geode (processor)|Geode]] (except NX),<br/>[[Company:NexGen|NexGen]] Nx586,<ref name="debs_cpuident" /><br/>IDT WinChip,<br/>IDT WinChip 2,<br/>IDT WinChip 3,<br/>[[Engineering:Transmeta Crusoe|Transmeta Crusoe]],<br/>Rise [[Engineering:MP6|mP6]],<br/>[[Company:Silicon Integrated Systems|SiS]] 550,<br/>DM&P [[Vortex86]] (early),<ref>CPU-World, [https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=66102 CPUID for Vortex86DX2 933&nbsp;MHz]. [https://web.archive.org/web/20251115085858/https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=66102 Archived] on 15 Nov 2025.</ref><br/>RDC IAD 100,<br/>[[Company:MCST|MCST]] Elbrus-8C2<ref name="inxi197_elbrus" /><!--Advantech EVA-X4150 and X4300 not listed due to lack of sources-->
|-
! <code>6h</code> !! 6
| [[Engineering:Pentium Pro|Pentium Pro]],<br/>[[Engineering:Pentium II|Pentium II]],<br/>[[Engineering:Pentium III|Pentium III]],<br/>[[Engineering:Pentium M|Pentium M]],<br/>{{nowrap|[[Engineering:Intel Core|Intel Core]] (all variants),}}<br/>{{nowrap|[[Engineering:Intel Atom|Intel Atom]] (all variants),}}<br/>[[Engineering:Xeon|Xeon]] (except NetBurst [[Engineering:List of Intel Xeon processors (NetBurst-based)|variants]]),<br/>[[Engineering:Xeon Phi|Xeon Phi]] (except KNC)
| K7: [[Engineering:Athlon|Athlon]],<br/>Athlon XP
| [[Engineering:Cyrix 6x86|Cyrix 6x86]]MX/MII,<br/>[[Engineering:VIA C3|VIA C3]],<br/>[[Engineering:VIA C7|VIA C7]],<br/>VIA Nano,<br/>DM&P [[Vortex86]] (DX3,EX2<ref>CPU-World, [https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=72324 CPUID for Vortex86EX2]. [https://web.archive.org/web/20250907195433/https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=72324 Archived] on 7 Sep 2025.</ref>),<br/>[[Company:Zhaoxin|Zhaoxin]] ZX-A/B/C/C+,<br/>([[Company:Centaur Technology#CNS core|Centaur CNS]]<ref>InstLatx64, [http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls0040672_CNS_04_CPUID.txt Centaur CNS CPUID dump]. [https://web.archive.org/web/20230530122012/http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls0040672_CNS_04_CPUID.txt Archived] on 30 May 2023.</ref>),<br/>[[Company:MCST|MCST]] Elbrus-12C/16C/2C3<ref name="inxi197_elbrus" />
|-
! <code>7h</code> !! 7
| [[Engineering:Itanium|Itanium]]<br/>(in IA-32 mode)
| {{n/a}}
| [[Company:Zhaoxin|Zhaoxin]] KaiXian,<br/>[[Company:Zhaoxin|Zhaoxin]] KaisHeng
|-
! <code>8h</code> !! 8
| {{n/a|{{efn|Family ID <code>8h</code> has been reported to have been deliberately avoided for the Pentium 4 processor family due to incompatibility with Windows NT 4.0.<ref>Jeff Atwood, [https://blog.codinghorror.com/nasty-software-hacks-and-intels-cpuid/ Nasty Software Hacks and Intel's CPUID]. ''Coding Horror'', 16 Aug 2005.</ref>}}}} || {{n/a}} || {{n/a}}
|-
! <code>9h</code> !! 9
| {{n/a}} || {{n/a}} || {{n/a}}
|-
! <code>0Ah</code> !! 10
| {{n/a}} || {{n/a}} || {{n/a}}
|-
! <code>0Bh</code> !! 11
| [[Engineering:Xeon Phi|Xeon Phi]] (Knights Corner)<ref name="intel_knc_ref">Intel, [https://www.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual], sep 2012, order no. 327364-001, appendix B.8, pages 673-674. [https://web.archive.org/web/20210804022347/https://software.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf Archived] on 4 Aug 2021.</ref> || {{n/a}} || {{n/a}}
|-
! <code>0Ch</code> !! 12
| {{n/a}} || {{n/a}} || {{n/a}}
|-
! <code>0Dh</code> !! 13
| {{n/a}} || {{n/a}} || {{n/a}}
|-
! <code>0Eh</code> !! 14
| {{n/a}} || {{n/a}} || {{n/a}}
|-
! <code>0Fh</code> !! 15
| [[Engineering:NetBurst|NetBurst]] (Pentium 4)
| K8/Hammer<br/>([[Engineering:Athlon 64|Athlon 64]])
| [[Engineering:Transmeta Efficeon|Transmeta Efficeon]]
|-
! <code>10h</code> !! 16
| {{n/a}} || [[Engineering:AMD 10h|K10]]: [[Engineering:AMD Phenom|Phenom]] || {{n/a}}
|-
! <code>11h</code> !! 17
| Itanium 2<ref>CPU-World, [https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=40724 CPUID for Intel Itanium 2 1.50 GHz]. [https://web.archive.org/web/20251114214202/https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=40724 Archived] on 14 Nov 2025.</ref><br/>(in IA-32 mode) || [[Engineering:AMD 10h#Family 11h and 12h derivatives|Turion X2]] || {{n/a}}
|-
! <code>12h</code> !! 18
| [[Engineering:Intel Core|Intel Core]] (Nova Lake and up)<ref>{{Cite web |title=[PATCH] x86/cpu: Add CPU model numbers for Novalake - Tony Luck |url=https://lore.kernel.org/lkml/20250801160028.4799-1-tony.luck@intel.com/ | access-date=2025-08-16 |website=lore.kernel.org}}</ref> || [[Engineering:AMD 10h#Family 11h and 12h derivatives|Llano]] || {{n/a}}
|-
! <code>13h</code> !! 19
| [[Engineering:Xeon|Xeon]] (Panther Cove and up)<ref>{{Cite web |title=[PATCH] x86/cpu: Add two Intel CPU model numbers - Tony Luck |url=https://lore.kernel.org/lkml/20240923173750.16874-1-tony.luck@intel.com/ |access-date=2024-09-24 |website=lore.kernel.org}}</ref> || {{n/a}} || {{n/a}}
|-
! <code>14h</code> !! 20
| {{n/a}} || [[Engineering:Bobcat (microarchitecture)|Bobcat]] || {{n/a}}
|-
! <code>15h</code> !! 21
| {{n/a}} || [[Engineering:Bulldozer (microarchitecture)|Bulldozer]],<br/>[[Engineering:Piledriver (microarchitecture)|Piledriver]],<br/>[[Engineering:Steamroller (microarchitecture)|Steamroller]],<br/>[[Engineering:Excavator (microarchitecture)|Excavator]] || {{n/a}}
|-
! <code>16h</code> !! 22
| {{n/a}} || [[Engineering:Jaguar (microarchitecture)|Jaguar]],<br/>[[Engineering:Puma (microarchitecture)|Puma]] || {{n/a}}
|-
! <code>17h</code> !! 23
| {{n/a}} || Zen 1,<br/>[[Engineering:Zen 2|Zen 2]] || {{n/a}}
|-
! <code>18h</code> !! 24
| {{n/a}} || colspan=2 style="text-align:center" | [[Engineering:AMD–Chinese joint venture|Hygon Dhyana]]
|-
! <code>19h</code> !! 25
| {{n/a}} || [[Engineering:Zen 3|Zen 3]],<br/>[[Engineering:Zen 4|Zen 4]] || {{n/a}}
|-
! <code>1Ah</code> !! 26
| {{n/a}} || [[Engineering:Zen 5|Zen 5]],<br/>(Zen 6) || {{n/a}}
|}
{{notelist}}

{{vpad}}
{| class="wikitable"
|+ CPUID EAX=1: Additional Information in EBX
!Bits
!EBX
!Valid
|-
! 7:0
| Brand Index
|
|-
! 15:8
| <code>CLFLUSH</code> line size (Value * 8 = cache line size in bytes) 
| if <code>CLFLUSH</code> feature flag is set.

CPUID.01.EDX.CLFSH [bit 19]= 1
|-
! 23:16
| Maximum number of addressable IDs for logical processors in this physical package;

The nearest power-of-2 integer that is not smaller than this value is the number of unique initial APIC IDs reserved for addressing different logical processors in a physical package.{{efn|On CPUs with more than 128 logical processors in a single package (e.g. Intel [[Engineering:Xeon Phi|Xeon Phi]] 7290<ref>InstLatX64, [http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0050671_KnightsLanding_CPUID2.txt 72-Core Intel Xeon Phi 7290 CPUID dump]</ref> and AMD [[Engineering:List of AMD Ryzen processors#Storm Peak desktop|Threadripper Pro 7995WX]]<ref>InstLatx64, [http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0A10F81_K19_StormPeak_01_CPUID.txt 96-Core AMD Ryzen Threadripper Pro 7995WX CPUID dump]</ref>) the value in bit 23:16 is set to a non-power-of-2 value.}}

Former use: Number of logical processors per physical processor; two for the Pentium 4 processor with Hyper-Threading Technology.<ref>{{Citation |title=Intel Processor Identification and the CPUID Instruction |date=May 2002 |url=https://bochs.sourceforge.net/techspec/24161821.pdf |archive-url=https://web.archive.org/web/20210417041749/https://bochs.sourceforge.io/techspec/24161821.pdf |archive-date=2021-04-17 |publisher=Intel}}</ref>
| if [[Hyper-threading]] feature flag is set.

CPUID.01.EDX.HTT [bit 28]= 1
|-
! 31:24
| Local APIC ID: The initial APIC-ID is used to identify the executing logical processor.{{efn|text=The Local APIC ID can also be identified via the cpuid 0Bh leaf ( CPUID.0Bh.EDX[x2APIC-ID] ). On CPUs with more than 256 logical processors in one package (e.g. Xeon Phi 7290), leaf 0Bh ''must'' be used because the APIC ID does not fit into 8 bits. }}
| Pentium 4 and subsequent processors.
|}
{{notelist}}
{{vpad}}

The processor info and feature flags are manufacturer specific but usually, the Intel values are used by other manufacturers for the sake of compatibility.

{| class="wikitable"
|+ CPUID EAX=1: Feature Information in EDX and ECX
! rowspan=2 | Bit
! colspan=2 | EDX 
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan=34 |
! colspan=2 | ECX{{efn|On some older processors, executing <code>CPUID</code> with a leaf index (EAX) greater than 0 may leave EBX and ECX unmodified, keeping their old values. For this reason, it is recommended to zero out EBX and ECX before executing <code>CPUID</code> with a leaf index of 1.<p>Processors noted to exhibit this behavior include Cyrix MII<ref>Linux 6.3 kernel sources, [https://elixir.bootlin.com/linux/v6.3/source/arch/x86/include/asm/cpuid.h /arch/x86/include/asm/cpuid.h], line 69</ref> and IDT WinChip 2.<ref>gcc-patches mailing list, [https://gcc.gnu.org/pipermail/gcc-patches/2019-May/522177.html CPUID Patch for IDT Winchip], May 21, 2019</ref></p>}}
! rowspan=2 | Bit
|-
! Short || Feature || Short || Feature
|-
! 0
| fpu || Onboard [[X87|x87]] FPU
| sse3|| SSE3 (Prescott New Instructions - PNI)
! 0
|-
! 1
| vme || Virtual 8086 mode extensions (such as VIF, VIP, PVI)
| pclmulqdq || <code>[[CLMUL instruction set|PCLMULQDQ]]</code> (carry-less multiply) instruction
! 1
|-
! 2
| de || Debugging extensions ([[Control register#CR4|CR4]] bit 3)
| dtes64 || 64-bit debug store (edx bit 21)
! 2
|-
! 3
| pse || [[Page Size Extension]] (4&nbsp;MB pages)
| monitor || <code>MONITOR</code> and <code>MWAIT</code> instructions (PNI)
! 3
|-
! 4
| tsc || [[Time Stamp Counter]] and <code>RDTSC</code> instruction
| ds-cpl || CPL qualified debug store
! 4
|-
! 5
| msr || [[Model-specific register]]s and <code>RDMSR</code>/<code>WRMSR</code> instructions 
| vmx || [[X86 virtualization|Virtual Machine eXtensions]]
! 5
|-
! 6
| pae || [[Physical Address Extension]] 
| smx || Safer Mode Extensions (LaGrande) (<code>GETSEC</code> instruction)
! 6
|-
! 7
| mce || Machine Check Exception 
| est || Enhanced [[Engineering:SpeedStep|SpeedStep]]
! 7
|-
! 8
| cx8{{efn|text=On processors from IDT, Transmeta and Rise (vendor IDs <code>CentaurHauls</code>, <code>GenuineTMx86</code> and <code>RiseRiseRise</code>), the <code>CMPXCHG8B</code> instruction is always supported, however the feature bit for the instruction might not be set. This is a workaround for a bug in Windows NT.<ref>Geoff Chappell, [https://www.geoffchappell.com/studies/windows/km/cpu/cx8.htm CMPXCHG8B Support in the 32-Bit Windows Kernel], Jan 23, 2008. [https://web.archive.org/web/20230130233150/https://www.geoffchappell.com/studies/windows/km/cpu/cx8.htm Archived] on Jan 30, 2023.</ref>}}|| <code>CMPXCHG8B</code> ([[Compare-and-swap|compare-and-swap]]) instruction 
| tm2 || [[Engineering:Thermal Monitor 2|Thermal Monitor 2]]
! 8
|-
! 9
| apic{{efn|On early [[Engineering:AMD K5|AMD K5]] (<code>AuthenticAMD</code> Family 5 Model 0) processors only, EDX bit 9 used to indicate support for PGE instead. This was moved to bit 13 from K5 Model 1 onwards.<ref>AMD, [http://www.bitsavers.org/components/amd/x86/K86/20734D_AMD_Processor_Recognition_Application_Notes_Jan97.pdf AMD Processor Recognition Application Note], publication #20734, rev D, Jan 1997, page 13</ref>}} || Onboard [[Advanced Programmable Interrupt Controller]] 
| ssse3 || [[SSSE3|Supplemental SSE3]] instructions
! 9
|-
! 10
| style="background:lightgrey;" | (mtrr){{efn|text=Intel AP-485, revisions 006<ref>Intel, [https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-006.pdf AP-485 Application Note - Intel Processor Identification and the CPUID Instruction], order no. 241618-006, march 1997, table 5 on page 10, see bit 10.</ref> to 008, lists {{nowrap|1=CPUID.(EAX=1):EDX[bit 10]}} as having the name "MTRR" (albeit described as "Reserved"/"Do not count on their value") - this name was removed in later revisions of AP-485, and the bit has been listed as reserved with no name since then.}}
| style="text-align:center; background:lightgrey;" | ''(reserved)'' 
| cnxt-id || L1 Context ID
! 10
|-
! 11
| sep{{efn|On [[Engineering:Pentium Pro|Pentium Pro]] (<code>GenuineIntel</code> Family 6 Model 1) processors only, EDX bit 11 is invalid - the bit is set, but the <code>SYSENTER</code> and <code>SYSEXIT</code> instructions are not supported on the Pentium Pro.<ref>Michal Necasek, [http://www.os2museum.com/wp/sysenter-where-are-you/ SYSENTER, Where Are You?], ''OS/2 Museum'', July 20, 2017</ref>}} || <code>SYSENTER</code> and <code>SYSEXIT</code> fast system call instructions 
| sdbg || Silicon Debug interface
! 11
|-
! 12
| mtrr || Memory Type Range Registers{{efn|text=For the MTRRs, additional feature information is not available through CPUID, but instead through the read-only <code>MTRRCAP</code> MSR (MSR <code>0FEh</code>). This MSR has the following layout: {{(!}} class="wikitable sortable"
! Bits !! Usage
{{!}}-
{{!}} 7:0 {{!!}} Number of variable-range MTRRs
{{!}}-
{{!}} 8 {{!!}} Fixed-range MTRRs supported
{{!}}-
{{!}} 9 {{!!}} {{n/a|(Reserved)}}
{{!}}-
{{!}} 10 {{!!}} Write-Combining memory type supported
{{!}}-
{{!}} 11 {{!!}} SMRR (System-Management Range Register) supported
{{!}}-
{{!}} 12 {{!!}} PRMRR (Processor Reserved Memory Range Register, part of [[Software Guard Extensions|SGX]]) supported
{{!}}-
{{!}} 13 {{!!}} SMRR2 supported<ref>Intel, [https://downloadmirror.intel.com/782148/tdx-module-v1.0.03.03.zip TDX module source code, v1.0.03.03], 22 Jun 2023, see src/common/helpers/smrrs.h. [https://web.archive.org/web/20250120025424/https://downloadmirror.intel.com/782148/tdx-module-v1.0.03.03.zip Archived] on 20 Jan 2025.</ref>
{{!}}-
{{!}} 14 {{!!}} SMRR-lock supported
{{!}}-
{{!}} 15 {{!!}} SEAMRR (SEcure Arbitration Mode Range Register, part of [[Trust Domain Extensions|TDX]]) supported<ref>Intel, [https://cdrdv2-public.intel.com/733582/intel-tdx-cpu-architectural-specification.pdf Trust Domain CPU Architectural Extensions], order no. 343754-002, may 2021. [https://web.archive.org/web/20241217122739/https://cdrdv2-public.intel.com/733582/intel-tdx-cpu-architectural-specification.pdf Archived] on 17 Dec 2024.</ref>
{{!}}-
{{!}} 63:16 {{!!}} {{n/a|(Reserved)}}
{{!)}}}}
| fma || [[FMA instruction set|Fused multiply-add]] (FMA3)
! 12
|-
! 13
| pge || [[Page table|Page]] Global Enable bit in [[Control register#CR4|CR4]] 
| cx16 || <code>CMPXCHG16B</code> instruction{{efn|1=Some very early Intel 64 processors have the <code>CMPXCHG16B</code> feature bit set even though they do not support the instruction - this applies to <code>GenuineIntel</code> Family <code>0Fh</code> Model 3 Stepping 4 chips (90nm Pentium 4) only.<ref>Intel, [https://www.intel.com/Assets/PDF/specupdate/302352.pdf Pentium 4 Processor on 90 nm Process Specification Update], order no. 302352-031, sep 2006, see erratum R85 on page 59. [https://web.archive.org/web/20081231012952/https://www.intel.com/Assets/PDF/specupdate/302352.pdf Archived] on 31 Dec 2008.</ref>}}
! 13
|-
! 14
| mca || Machine check architecture
| xtpr || Can disable sending task priority messages
! 14
|-
! 15
| cmov || Conditional move: <code>CMOV</code>, <code>[[FCMOV]]</code> and <code>FCOMI</code> instructions{{efn|<code>FCMOV</code> and <code>FCOMI</code> instructions only available if onboard x87 FPU also present (indicated by EDX bit 0).}}
| pdcm || Perfmon & debug capability
! 15
|-
! 16
| pat || Page Attribute Table
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''{{efn|ECX bit 16 is listed as "Reserved" in public Intel and AMD documentation and is not set in any known processor. However, some versions of the [[Software:Windows Vista|Windows Vista]] kernel are reported to be checking this bit<ref>Geoff Chappell, [https://www.geoffchappell.com/studies/windows/km/cpu/cpuid/00000001h/ecx.htm ECX From CPUID Leaf 1], Jan 26, 2020. [https://web.archive.org/web/20200509082346/https://www.geoffchappell.com/studies/windows/km/cpu/cpuid/00000001h/ecx.htm Archived] on May 9, 2020.</ref> - if it is set, Vista will recognize it as a "processor channels" feature.}}
! 16
|-
! 17
| pse-36 || [[PSE-36|36-bit page size extension]] 
| pcid || Process context identifiers ([[Control register#CR4|CR4]] bit 17)
! 17
|-
! 18
| psn || Processor Serial Number supported and enabled{{efn|text=On Intel and Transmeta<ref name="transmeta_msr"/> CPUs that support PSN (Processor Serial Number), the PSN can be disabled by setting bit 21 of MSR <code>119h</code> (<code>BBL_CR_CTL</code>) to 1. Doing so will remove leaf 3 and cause {{nowrap|1=CPUID.(EAX=1):EDX[bit 18]}} to return 0.}}
| dca || Direct cache access for DMA writes<ref>{{Cite journal | last1 = Huggahalli | first1 = Ram| last2 = Iyer | first2 = Ravi| last3 = Tetrick | first3 = Scott| doi = 10.1145/1080695.1069976 | title = Direct Cache Access for High Bandwidth Network I/O | journal = ACM SIGARCH Computer Architecture News | volume = 33 | issue = 2 | pages = 50–59| year = 2005 | id = [[CiteSeerX]]:{{URL|1=citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.957|2=10.1.1.91.957}}| citeseerx = 10.1.1.85.3862 }}</ref><ref>{{Citation |title=What Every Programmer Should Know About Memory |year=2007 |first=Ulrich |last=Drepper |id = [[CiteSeerX]]:{{URL|1=citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.91.957|2=10.1.1.91.957}} }}</ref>
! 18
|-
! 19
| clfsh || <code>CLFLUSH</code> cache line flush instruction ([[SSE2]]) 
| sse4.1 || SSE4.1 instructions
! 19
|-
! 20
| style="background:lightgrey;" | (nx) 
| style="background:lightgrey;" | [[NX bit|No-execute (NX) bit]] ([[Engineering:Itanium|Itanium]] only, reserved on other CPUs)<ref name="ia64_sdm">Intel, [https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-4-manual.pdf Itanium Architecture Software Developer's Manual, rev 2.3, volume 4: IA-32 Instruction Set], may 2010, document number: 323208, table 2-5, page 4:81, see bits 20 and 30. [https://web.archive.org/web/20120215121932/https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-4-manual.pdf Archived] on Feb 15, 2012.</ref>{{efn|On non-Itanium x86 processors, support for the [[NX bit|No-execute bit]] is indicated in {{nowrap|1=CPUID.(EAX=8000_0001):EDX[bit 20]}} instead.}}
| sse4.2 || SSE4.2 instructions
! 20
|-
! 21
| ds || Debug store: save trace of executed jumps 
| x2apic || x2APIC (enhanced APIC)
! 21
|-
! 22
| acpi || Onboard thermal control MSRs for [[Advanced Configuration and Power Interface|ACPI]] 
| movbe || <code>MOVBE</code> instruction (big-endian)
! 22
|-
! 23
| mmx || [[MMX (instruction set)|MMX]] instructions (64-bit SIMD) 
| popcnt || <code>POPCNT</code> instruction
! 23
|-
! 24
| fxsr || <code>FXSAVE</code>, <code>FXRSTOR</code> instructions, [[Control register#CR4|CR4]] bit 9 
| tsc-deadline || APIC implements one-shot operation using a TSC deadline value
! 24
|-
! 25
| sse || [[Streaming SIMD Extensions]] (SSE) instructions<br/>(aka "Katmai New Instructions"; 128-bit SIMD) 
| aes-ni || [[AES instruction set]]
! 25
|-
! 26
| sse2 || [[SSE2]] instructions 
| xsave || Extensible processor state save/restore:<br/><code>XSAVE</code>, <code>XRSTOR</code>, <code>XSETBV</code>, <code>XGETBV</code> instructions
! 26
|-
! 27
| ss || CPU cache implements self-snoop 
| osxsave || <code>XSAVE</code> enabled by OS
! 27
|-
! 28
| htt || Max APIC IDs reserved field is Valid{{efn|text=EDX bit 28, if set, indicates that bits 23:16 of CPUID.(EAX=1):EBX are valid. If this bit is not set, then the CPU package contains only 1 logical processor.<p>In older documentation, this bit is often listed as a "[[Hyper-threading]] technology"<ref>Intel, [https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-030.pdf AP-485, Processor Identification and the CPUID Instruction flag], rev 30, jan 2006, page 26</ref> flag - however, while this flag is a prerequisite for Hyper-Threading support, it does not by itself indicate support for Hyper-Threading and it has been set on many CPUs that do not feature any form of multi-threading technology.<ref>Michal Necasek, [http://www.os2museum.com/wp/htt-means-hyper-threading-right/ HTT Means Hyper-Threading, Right?], ''OS/2 Museum'', dec 11, 2017</ref></p>}}
| avx || [[Advanced Vector Extensions]] (256-bit SIMD)
! 28
|-
! 29
| tm || Thermal monitor automatically limits temperature 
| f16c || Floating-point conversion instructions to/from FP16 format
! 29
|-
! 30
| ia64 || IA64 processor emulating x86<ref name="ia64_sdm"/>
| rdrnd || <code>[[RDRAND]]</code> (on-chip random number generator) feature
! 30
|-
! 31
| pbe || Pending Break Enable (PBE# pin) wakeup capability
| hypervisor || [[Hypervisor]] present (always zero on physical CPUs)<ref name="VMware KB 1009458">{{cite web |url=https://kb.vmware.com/s/article/1009458 |title=Mechanisms to determine if software is running in a VMware virtual machine |work=VMware Knowledge Base |publisher=VMWare |date=2015-05-01 |quote=Intel and AMD CPUs have reserved bit 31 of ECX of CPUID leaf 0x1 as the hypervisor present bit. This bit allows hypervisors to indicate their presence to the guest operating system. Hypervisors set this bit and physical CPUs (all existing and future CPUs) set this bit to zero. Guest operating systems can test bit 31 to detect if they are running inside a virtual machine. }}</ref><ref>{{cite web |url=https://lore.kernel.org/lkml/1222881242.9381.17.camel@alok-dev1/ |title=Hypervisor CPUID Interface Proposal |last1=Kataria |first1=Alok |last2=Hecht |first2=Dan |publisher=LKML Archive on lore.kernel.org |date=2008-10-01 |url-status=live |archive-url=https://web.archive.org/web/20190315105121/https://lore.kernel.org/lkml/1222881242.9381.17.camel@alok-dev1/ |archive-date=2019-03-15 |quote=Bit 31 of ECX of CPUID leaf 0x1. This bit has been reserved by Intel & AMD for use by hypervisors and indicates the presence of a hypervisor. Virtual CPU's (hypervisors) set this bit to 1 and physical CPU's (all existing and future CPU's) set this bit to zero. This bit can be probed by the guest software to detect whether they are running inside a virtual machine. }}</ref><ref>{{cite web |title=AMD64 Technology AMD64 Architecture Programmer's Manual Volume 2: System Programming |url=https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf |publisher=Advanced Micro Devices, Inc. |access-date=9 September 2023 |page=498 |language=English |id=24593 |edition=3.41 |archive-url=https://web.archive.org/web/20230930084941/https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf |archive-date=30 Sep 2023 |quote=15.2.2 Guest Mode This new processor mode is entered through the VMRUN instruction. When in guest mode, the behavior of some x86 instructions changes to facilitate virtualization. The CPUID function numbers 4000_0000h-4000_00FFh have been reserved for software use. Hypervisors can use these function numbers to provide an interface to pass information from the hypervisor to the guest. This is similar to extracting information about a physical CPU by using CPUID. Hypervisors use the CPUID Fn 400000[FF:00] bit to denote a virtual platform. Feature bit CPUID Fn0000_0001_ECX[31] has been reserved for use by hypervisors to indicate the presence of a hypervisor. Hypervisors set this bit to 1 and physical CPU's set this bit to zero. This bit can be probed by the guest software to detect whether they are running inside a virtual machine. }}</ref>
! 31
|}
{{notelist}}
Reserved fields should be masked before using them for processor identification purposes.
{{vpad}}

== EAX=2: Cache and TLB Descriptor Information ==
This returns a list of descriptors indicating cache and TLB capabilities in EAX, EBX, ECX and EDX registers.

On processors that support this leaf, calling <code>CPUID</code> with EAX=2 will cause the bottom byte of EAX to be set to <code>01h</code>{{efn|text=In older Intel documentation, the bottom byte of the value returned in EAX is described as specifying the number of times the <code>CPUID</code> must be called with EAX=2 to get hold of all the cache/TLB descriptors. However, all known processors that implement this leaf return <code>01h</code> in this byte, and newer Intel documentation (SDM rev 053<ref>Intel [https://kib.kiev.ua/x86docs/Intel/SDMs/253666-053.pdf SDM vol 2A], order no. 253666-053, Jan 2015, p. 244</ref> and later) specifies this byte as having the value <code>01h</code>.}} and the remaining 15&nbsp;bytes of EAX/EBX/ECX/EDX to be filled with 15 descriptors, one byte each. These descriptors provide information about the processor's caches, TLBs and prefetch. This is typically one cache or TLB per descriptor, but some descriptor-values provide other information as well — in particular, <code>00h</code> is used for an empty descriptor, <code>FFh</code> indicates that the leaf does not contain valid cache information and that leaf 4h should be used instead, and <code>FEh</code> indicates that the leaf does not contain valid TLB information and that leaf 18h should be used instead. There are also some cases, such as descriptors <code>63h</code> and <code>C3h</code>, where a single descriptor provides information about multiple TLBs. The descriptors may appear in any order.

For each of the four registers (EAX,EBX,ECX,EDX), if bit 31 is set, then the register should not be considered to contain valid descriptors (e.g. on Itanium in IA-32 mode, CPUID(EAX=2) returns <code>80000000h</code> in EDX — this should be interpreted to mean that EDX contains no valid information, not that it contains a descriptor for a 512K L2 cache.)
{{vpad}}
The table below provides, for known descriptor values, a condensed description of the cache or TLB indicated by that descriptor value (or other information, where that applies). The suffixes used in the table are:
* K,M,G : kibibyte, mebibyte, gibibyte (capacity for caches, page-size for TLBs)
* E : entries (for TLBs; e.g. 64E = 64 entries)
* p : page-size (e.g. 4Kp for TLBs where each entry describes one 4&nbsp;KiB [[Page (computer memory)|page]], 4K/2Mp for TLBs where each entry can describe either one 4&nbsp;KiB page or one 2&nbsp;MiB hugepage)
* L : cache-line size (e.g. 32L = 32-byte cache line size)
* S : cache sector size (e.g. 2S means that the cache uses sectors of 2 cache-lines each)
* A : associativity (e.g. 6A = 6-way [[Cache placement policies|set-associative]], FA = fully-associative)

<div style="overflow-x:auto">
{| class="wikitable"
|+ Legend for cache/TLB descriptor byte encodings
|-
| {{shade|color=blue|35|Level-1<br/>instruction<br/>or data cache}}
| {{shade|color=blue|70|Level-2<br/>cache}}
| {{shade|color=blue|100|Level-3<br/>cache}}
| {{shade|color=gold|25|Instruction<br/>or data TLB}}
| {{shade|color=gold|80|Level-2<br/>shared<br/>TLB}}
| {{yes|Other<br/>information}}
| style="background: #ccc; color: black; vertical-align: middle; text-align: center" | (reserved)
|}

{| class="wikitable" style="background:#ccc; color: black; vertical-align: middle; text-align: center"
|+ CPUID EAX=2: Cache/TLB descriptor byte encodings
! !! x0 !! x1 !! x2 !! x3 !! x4 !! x5 !! x6 !! x7 !! !! x8 !! x9 !! xA !! xB !! xC !! xD !! xE !! xF !!
|-
! 0x
| {{yes|null<br/>descriptor}} || {{shade|color=gold|25|ITLB: 32E,<br/>4Kp, 4A}} || {{shade|color=gold|25|ITLB: 2E,<br/>4Mp, FA}} || {{shade|color=gold|25|DTLB: 64E,<br/>4Kp, 4A}} || {{shade|color=gold|25|DTLB: 8E,<br/>4Mp, 4A}} || {{shade|color=gold|25|DTLB: 32E,<br/>4Mp, 4A}} || {{shade|color=blue|35|L1I: 8K,<br/>4A, 32L}} ||
! 0x
| {{shade|color=blue|35|L1I: 16K,<br/>4A, 32L}} || {{shade|color=blue|35|L1I: 32K,<br/>4A, 64L}} || {{shade|color=blue|35|L1D: 8K,<br/>2A, 32L}} || {{shade|color=gold|25|ITLB: 4E,<br/>4Mp, FA}} || {{shade|color=blue|35|L1D: 16K,<br/>4A, 32L}} || {{shade|color=blue|35|L1D: 16K,<br/>4A, 64L{{efn|name=leaf2_ecc|text=For descriptors <code>0Dh</code> and <code>0Eh</code>, Intel AP-485 rev 37<ref name="ap485_rev037"/> lists the caches they describe as having [[Error correction code|ECC]] - this was removed in rev 38 and later Intel documentation.}}}} || {{shade|color=blue|35|L1D: 24K,<br/>6A, 64L{{efn|name=leaf2_ecc}}}} ||  
! 0x
|-
! 1x
| {{shade|color=blue|35|(L1D: 16K,<br/>4A, 32L){{efn|name=leaf2_itanium|Descriptors <code>10h</code>, <code>15h</code>, <code>1Ah</code>, <code>88h</code>, <code>89h</code>, <code>8Ah</code>, <code>90h</code>, <code>96h</code>, <code>9Bh</code> are documented for the IA-32 operation mode of [[Engineering:Itanium|Itanium]] only.<ref>Intel, [https://web.archive.org/web/20040218001603/http://www.intel.com/design/itanium/downloads/24532003.pdf Itanium Processor Reference Manual for Software Development], rev 2.0, order no. 245320-003, December 2001, page 110. Archived from [http://www.intel.com/design/itanium/downloads/24532003.pdf the original] on 18 Feb 2004.</ref>}}}} ||   ||   ||   ||   || {{shade|color=blue|35|(L1I: 16K,<br/>4A, 32L){{efn|name=leaf2_itanium}}}} ||   ||  
! 1x
|   ||   || {{shade|color=blue|70|(L2C: 96K,<br/>6A, 64L){{efn|name=leaf2_itanium}}}} ||   ||   || {{shade|color=blue|70|L2C: 128K,<br/>2A, 64L}} ||   ||  
! 1x
|-
! 2x
|   || {{shade|color=blue|70|L2C: 256K,<br/>8A, 64L{{efn|The cache described by descriptor <code>21h</code> is in some places (e.g. AP-485 rev 36<ref name="ap485_rev36"/> but not rev 37) referred to as an "MLC" (Mid-Level Cache).}}}} || {{shade|color=blue|100|L3C: 512K,<br/>4A, 64L, 2S}} || {{shade|color=blue|100|L3C: 1M,<br/>8A, 64L, 2S}} || {{shade|color=blue|70|L2C: 1M,<br/>16A, 64L}} || {{shade|color=blue|100|L3C: 2M,<br/>8A, 64L, 2S}} || (128-byte<br/>prefetch){{efn|name=cpuid2_winnt}} || (128-byte<br/>prefetch){{efn|name=cpuid2_winnt}}
! 2x
| (128-byte<br/>prefetch){{efn|name=cpuid2_winnt}} || {{shade|color=blue|100|L3C: 4M,<br/>8A, 64L, 2S}} ||   ||   || {{shade|color=blue|35|L1D: 32K,<br/>8A, 64L}} ||   ||   ||  
! 2x
|-
! 3x
| {{shade|color=blue|35|L1I: 32K,<br/>8A, 64L}} ||   ||   ||   ||   ||   ||   ||  
! 3x
|   || {{shade|color=blue|70|L2C: 128K,<br/>{{nowrap|4A, 64L, 2S{{efn|name=ap485_36|Descriptors <code>39h-3Eh</code> and <code>73h</code> are listed in rev 36 of Intel AP-485,<ref name="ap485_rev36">Intel, [https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-036.pdf Processor Identification and the CPUID Instruction Application Note 485], order no. 241618-036, Aug 2009, page 26. [https://web.archive.org/web/20231006233052/https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-036.pdf Archived] on 6 Oct 2023.</ref>
 but have been removed from later Intel documentation even though several of them have been used in Intel CPUs (mostly in [[Engineering:List of Intel Celeron processors#Netburst based Celerons|Netburst-based Celeron]] CPUs, e.g. <code>39h</code> in [[Engineering:Celeron#Willamette-128|"Willamette-128"]],<ref>InstLatX64, [http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0000F13_P4_Willamette_CPUID.txt Willamette-128 CPUID dump]. [https://web.archive.org/web/20191207190538/http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0000F13_P4_Willamette_CPUID.txt Archived] on 7 Dec 2019.</ref> <code>3Bh</code> in "Northwood-128",<ref>InstLatX64, [http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0000F27_P4_NorthwoodCeleron_CPUID.txt Northwood-128 CPUID dump]. [https://web.archive.org/web/20191207111724/http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0000F27_P4_NorthwoodCeleron_CPUID.txt Archived] on 7 Dec 2019.</ref> and <code>3Ch</code> in "Prescott-256"<ref>InstLatX64, [http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0000F41_P4_Prescott_CPUID.txt Prescott-256 CPUID dump]. [https://web.archive.org/web/20191206083832/http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0000F41_P4_Prescott_CPUID.txt Archived] on 6 Dec 2019.</ref>).}}}}}} || {{shade|color=blue|70|L2C: 192K,<br/>{{nowrap|6A, 64L, 2S{{efn|name=ap485_36}}}}}} || {{shade|color=blue|70|L2C: 128K,<br/>{{nowrap|2A, 64L, 2S{{efn|name=ap485_36}}}}}} || {{shade|color=blue|70|L2C: 256K,<br/>{{nowrap|4A, 64L, 2S{{efn|name=ap485_36}}}}}} || {{shade|color=blue|70|L2C: 384K,<br/>{{nowrap|6A, 64L, 2S{{efn|name=ap485_36}}}}}} || {{shade|color=blue|70|L2C: 512K,<br/>{{nowrap|4A, 64L, 2S{{efn|name=ap485_36}}}}}} || {{shade|color=blue|70|L2C: 256K,<br />{{nowrap|2A, 64L}}}}<!-- Intel Tolapai https://github.com/torvalds/linux/commit/04fa11ea170afd147b5d1e1ec88ec359a766bf31 -->{{efn|text=Descriptor <code>3Fh</code> is, as of November 2024, not listed in any known Intel documentation - it is nevertheless used in Intel [[Engineering:Tolapai|Tolapai]] processors,<ref>InstLatX64, [http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0010650_Tolapai_CPUID2.txt Intel Tolapai CPUID dump]. [https://web.archive.org/web/20210119004154/http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0010650_Tolapai_CPUID2.txt Archived] on 19 Jan 2019.</ref> and is listed in an Intel-provided Linux kernel patch.<ref>Jason Gaston, [https://marc.info/?l=linux-kernel&m=119819457630979&w=2 (PATCH 2.6.24-rc5) x86 intel_cacheinfo.c: cpu cache info entry for Intel Tolapai], ''LKML'', 20 Dec 2007. [https://web.archive.org/web/20241109130228/https://marc.info/?l=linux-kernel&m=119819457630979&w=2 Archived] on 9 Nov 2024.</ref>}}
! 3x
|-
! 4x
| {{yes|no L3 cache<br/>present}} || {{shade|color=blue|70|L2C: 128K,<br/>4A, 32L}} || {{shade|color=blue|70|L2C: 256K,<br/>4A, 32L{{efn|name=cyrix3_leaf2|text=Documentation for the VIA Cyrix III "Joshua" processor (<code>CyrixInstead</code> Family 6 Model 5) indicates that this processor uses descriptor values <code>74h</code> and <code>77h</code> for its TLBs, and values <code>42h</code> and <code>82h</code> for its caches - but does not specify which caches/TLBs in the processor each of these descriptor values correspond to.<ref>VIA-Cyrix, [https://web.archive.org/web/20000929185216/http://www.viatech.com:80/pdf/cyrix/cyrix3/cyr3_bios.pdf Application Note 120: Cyrix III CPU BIOS Writer's Guide], rev 1.1, 24 Nov 1999, page 13. Archived from the [http://www.viatech.com:80/pdf/cyrix/cyrix3/cyr3_bios.pdf original] on 29 Sep 2000.</ref>}}}} || {{shade|color=blue|70|L2C: 512K,<br/>4A, 32L}} || {{shade|color=blue|70|L2C: 1M,<br/>4A, 32L}} || {{shade|color=blue|70|L2C: 2M,<br/>4A, 32L}} || {{shade|color=blue|100|L3C: 4M,<br/>4A, 64L}} || {{shade|color=blue|100|L3C: 8M,<br/>8A, 64L}}
! 4x
| {{shade|color=blue|70|L2C: 3M,<br/>12A, 64L}}
| style="background: linear-gradient(to top right, #73CEFF 0%, #73CEFF 50%, #AADCFE 50%, #AADCFE); color: black; vertical-align: middle; text-align: center" | L2C/L3C:{{efn|Descriptor <code>49h</code> indicates a level-3 cache on <code>GenuineIntel</code> Family 0Fh Model 6 (Pentium 4 based Xeon) CPUs, and a level-2 cache on other CPUs.}}<br/>{{nowrap|4M,16A,64L}}
| {{shade|color=blue|100|L3C: 6M,<br/>12A, 64L}} || {{shade|color=blue|100|L3C: 8M,<br/>16A, 64L}} || {{shade|color=blue|100|L3C: 12M,<br/>12A, 64L}} || {{shade|color=blue|100|L3C: 16M,<br/>16A, 64L}} || {{shade|color=blue|70|L2C: 6M,<br/>24A, 64L}} || {{shade|color=gold|25|ITLB: 32E,<br/>{{nowrap|4Kp{{efn|Intel's CPUID documentation does not specify the associativity of the ITLB indicated by descriptor <code>4Fh</code>. The processors that use this descriptor (Intel Atom [[Engineering:Bonnell (microarchitecture)|"Bonnell"]]<ref>InstlatX64, [http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00106C2_Diamondville_CPUID.txt Intel Atom 230 CPUID dump]. [https://web.archive.org/web/20191207081927/http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00106C2_Diamondville_CPUID.txt Archived] on 7 Dec 2019.</ref>) are described elsewhere as having a fully-associative 32-entry ITLB.<ref>WikiChip, [https://en.wikichip.org/wiki/intel/microarchitectures/bonnell Bonnell]. [https://web.archive.org/web/20170716171201/https://en.wikichip.org/wiki/intel/microarchitectures/bonnell Archived] on 16 Jul 2017.</ref><!-- also listed in SDM, vol 3m chaper 12, memory cache control, table 12-1-->}}}}}}
! 4x
|-
! 5x
| {{shade|color=gold|25|{{nowrap|ITLB: 64E,FA,}}<!-- entries 50/51/52 and 5B/5C/5D are listed as fully-associative in AP-485 rev 36, but not in the SDM; SDM vol 3, table 12-1 seems to indicate that the P4 ITLB (which uses 50h) is *not* FA and does not support largepages - however http://ixbtlabs.com/articles2/rmma/rmma-p4.html measured the P4 ITLB to be 64-entry fully-associative--><br/>4K/2M/4Mp}} || {{shade|color=gold|25|{{nowrap|ITLB: 128E,FA,}}<br/>4K/2M/4Mp}} || {{shade|color=gold|25|{{nowrap|ITLB: 256E,FA,}}<br/>4K/2M/4Mp}} ||   ||   || {{shade|color=gold|25|ITLB: 7E,<br/>{{nowrap|2M/4Mp, FA}}}} || {{shade|color=gold|25|DTLB: 16E,<br/>4Mp, 4A}} || {{shade|color=gold|25|{{nowrap|DTLB: 16E,}}<br/>4Kp, 4A}}
! 5x
|   || {{shade|color=gold|25|DTLB: 16E,<br/>4Kp, FA}} || {{shade|color=gold|25|DTLB: 32E,<br/>2M/4Mp, 4A}} || {{shade|color=gold|25|DTLB: 64E<br/>4K/4Mp, FA}} || {{shade|color=gold|25|DTLB: 128E,<br/>4K/4Mp, FA}} || {{shade|color=gold|25|DTLB: 256E,<br/>4K/4Mp, FA}} ||   ||  
! 5x
|-
! 6x
| {{shade|color=blue|35|L1D: 16K,<br/>8A, 64L}} || {{shade|color=gold|25|ITLB: 48E,<br/>4Kp, FA}} ||   || {{shade|color=gold|25|style=line-height:1.2|{{small|Two DTLBs:<br/>{{nowrap|32E, 2M/4Mp, 4A}}<br/>+ 4E, 1Gp, FA}}}}
| {{shade|color=gold|25|{{nowrap|DTLB: 512E,}}<br/>4Kp, 4A}} ||   || {{shade|color=blue|35|L1D: 8K,<br/>4A, 64L}} || {{shade|color=blue|35|L1D: 16K,<br/>4A, 64L}}
! 6x
| {{shade|color=blue|35|{{nowrap|L1D: 32K,}}<br/>4A, 64L}} ||   || {{shade|color=gold|25|DTLB: 64E,<br/>4Kp, 8A}}<!-- 6A is described as an utlb in Intel documentation, but appears to be a pretty normal L1 DTLB. Entries 6A/6B/6C/6D mislabelled as Cache in Intel documentation --> || {{shade|color=gold|25|DTLB: 256E,<br/>4Kp, 8A}} || {{shade|color=gold|25|DTLB: 128E,<br/>2M/4Mp, 8A}} || {{shade|color=gold|25|DTLB: 16E,<br/>1Gp, FA}} ||   ||  
! 6x
|-
! 7x
| {{shade|color=blue|35|[[Trace cache]],<br/>{{nowrap|12K-μop, 8A{{efn|name=cyrix_leaf2|On Cyrix and Geode CPUs (Vendor IDs <code>CyrixInstead</code> and {{nowrap|<code>Geode by NSC</code>}}), descriptors <code>70h</code> and <code>80h</code> have a different meaning:<ref>Cyrix, [http://datasheets.chipdb.org/Cyrix/detect.pdf Cyrix CPU Detection Guide], rev 1.01, 2 Oct 1997, page 13.</ref>
* Descriptor <code>70h</code> indicates a 32-entry shared instruction+data 4-way-set-associative TLB with a 4K page size.
* Descriptor <code>80h</code> indicates a 16&nbsp;KiB shared instruction+data L1 cache with 4-way set-associativity and a cache-line size of 16&nbsp;bytes.}}}}}} || {{shade|color=blue|35|Trace cache,<br/>16K-μop, 8A}} || {{shade|color=blue|35|Trace cache,<br/>32K-μop, 8A}} || {{shade|color=blue|35|Trace cache,<br/>64K-μop, 8A{{efn|name=ap485_36}}}} || {{efn|name=cyrix3_leaf2}}  ||   || {{shade|color=gold|25|ITLB: 8E,<br/>2M/4Mp, FA{{efn|Descriptor <code>76h</code> is listed as an 1&nbsp;MiB L2 cache in rev 37 of Intel AP-485,<ref name="ap485_rev037">Intel, [https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-037.pdf Processor Identification and the CPUID Instruction Application Note 485], order no. 241618-037, Jan 2011, pages 31-32. [https://web.archive.org/web/20231017194149/https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-037.pdf Archived] on 17 Oct 2023.</ref> but as an instruction TLB in rev 38 and all later Intel documentation.}}}} || {{shade|color=blue|35|(L1I: 16K,<br/>4A, 64L){{efn|name=leaf2_itanium2}}{{efn|name=cyrix3_leaf2}}}}
! 7x
| {{shade|color=blue|70|L2C: 1M,<br/>4A, 64L}} || {{shade|color=blue|70|L2C: 128K,<br/>8A, 64L, 2S}} || {{shade|color=blue|70|L2C: 256K,<br/>8A, 64L, 2S}} || {{shade|color=blue|70|L2C: 512K,<br/>8A, 64L, 2S}} || {{shade|color=blue|70|L2C: 1M,<br/>8A, 64L, 2S}} || {{shade|color=blue|70|L2C: 2M,<br/>8A, 64L}} || {{shade|color=blue|70|(L2C: 256K,<br/>8A, 128L){{efn|name=leaf2_itanium2}}}} || {{shade|color=blue|70|{{nowrap|L2C: 512K,}}<br/>2A, 64L}}
! 7x
|-
! 8x
| {{shade|color=blue|70|L2C: 512K,<br/>8A, 64L{{efn|name=cyrix_leaf2}}}} || {{shade|color=blue|70|(L2C: 128K,<br/>8A, 32L){{efn|name=cpuid2_winnt|Descriptor values <code>26h</code>,<code>27h</code>,<code>28h</code> and <code>81h</code> are not listed in Intel documentation and are not used in any known released CPU. (<code>81h</code> has been seen in engineering samples of the cancelled [[Engineering:Intel Timna|Intel Timna]].<ref>CPU-World forum, [https://www.cpu-world.com/forum/viewtopic.php?t=38677&postdays=0&postorder=asc&start=15 Working Timna desktop 2023, page 2] - lists a CPUID dump from a Timna engineering sample. [https://web.archive.org/web/20241109131327/https://www.cpu-world.com/forum/viewtopic.php?t=38677&postdays=0&postorder=asc&start=15 Archived] on 9 Nov 2024.</ref>) They have nevertheless been reported to be recognized by the Windows NT kernel v5.1 ([[Software:Windows XP|Windows XP]]) and higher. <code>81h</code> is also recognized by v5.0 ([[Software:Windows 2000|Windows 2000]]).<ref>Geoff Chappell, [https://www.geoffchappell.com/studies/windows/km/cpu/cpuid/00000002h/index.htm CPUID Leaf 2], 26 Jan 2020. [https://web.archive.org/web/20230904165020/https://www.geoffchappell.com/studies/windows/km/cpu/cpuid/00000002h/index.htm Archived] on Sep 4, 2023.</ref>}}}} || {{shade|color=blue|70|L2C: 256K,<br/>8A, 32L{{efn|name=cyrix3_leaf2}}}} || {{shade|color=blue|70|L2C: 512K,<br/>8A, 32L}} || {{shade|color=blue|70|L2C: 1M,<br/>8A, 32L}} || {{shade|color=blue|70|L2C: 2M,<br/>8A, 32L}} || {{shade|color=blue|70|L2C: 512K,<br/>4A, 64L}} || {{shade|color=blue|70|L2C: 1M,<br/>8A, 64L}} 
! 8x
| {{shade|color=blue|100|(L3C: 2M,<br/>{{nowrap|4A, 64L){{efn|name=leaf2_itanium}}}}}} || {{shade|color=blue|100|(L3C: 4M,<br/>4A, 64L){{efn|name=leaf2_itanium}}}} || {{shade|color=blue|100|(L3C: 8M,<br/>4A, 64L){{efn|name=leaf2_itanium}}}} ||   ||   || {{shade|color=blue|100|(L3C: 3M,<br/>{{nowrap|12A, 128L){{efn|name=leaf2_itanium2|Descriptors <code>77h</code>, <code>7Eh</code>, <code>8Dh</code> are documented for the IA-32 operation mode of Itanium 2 only.<ref>Intel, [https://web.archive.org/web/20061207103053/http://download.intel.com/design/Itanium2/manuals/25111003.pdf Itanium 2 Processor Reference Manual], order no. 251110-003, May 2004, page 192. Archived from [http://download.intel.com/design/Itanium2/manuals/25111003.pdf the original] on 7 Dec 2006.</ref>}}{{efn|Under the IA-32 operation mode of Itanium 2, the L3 cache size is always reported as 3&nbsp;MiB regardless of the actual size of the cache.<ref>Intel, [https://web.archive.org/web/20041125131937/http://developer.intel.com:80/design/itanium2/specupdt/25114101.pdf Itanium 2 Processor Specification Update], order.no. 251141-028, Nov 2004, erratum 6 on page 26. Archived from [http://developer.intel.com:80/design/itanium2/specupdt/25114101.pdf the original] on 25 Nov 2004.</ref>}}}}}} ||   ||  
! 8x
|-
! 9x
| {{shade|color=gold|25|{{nowrap|(ITLB: 64E,FA,}}<br/>4K-256Mp){{efn|name=leaf2_itanium}}}} ||   ||   ||   ||   ||   || {{shade|color=gold|25|{{nowrap|(DTLB: 32E,FA,}}<br/>4K-256Mp){{efn|name=leaf2_itanium}}}} ||  
! 9x
|   ||   ||   || {{shade|color=gold|25|{{nowrap|(DTLB: 96E,FA,}}<br/>4K-256Mp){{efn|name=leaf2_itanium}}}} ||   ||   ||   ||  
! 9x
|-
! Ax
| {{shade|color=gold|25|DTLB: 32E,<br/>4Kp, FA}} ||   ||   ||   ||   ||   ||   ||  
! Ax
|   ||   ||   ||   ||   ||   ||   ||  
! Ax
|-
! Bx
| {{shade|color=gold|25|ITLB: 128E,<br/>4Kp, 4A}} || {{shade|color=gold|25|ITLB: 8E,<br/>2M/4Mp, 4A{{efn|For descriptor <code>B1h</code>, the TLB capacity is 8 elements when using 2&nbsp;MiB pages, but reduced to 4 elements when using 4&nbsp;MiB pages.}}}} || {{shade|color=gold|25|ITLB: 64E,<br/>4Kp, 4A}} || {{shade|color=gold|25|DTLB: 128E,<br/>4Kp, 4A}} || {{shade|color=gold|25|DTLB: 256E,<br/>4Kp, 4A}} || {{shade|color=gold|25|ITLB: 64E,<br/>4Kp, 8A}} || {{shade|color=gold|25|ITLB: 128E,<br/>4Kp, 8A}} ||  
! Bx
|   ||   || {{shade|color=gold|25|DTLB: 64E,<br/>4Kp, 4A}} ||   ||   ||   ||   ||  
! Bx
|-
! Cx
| {{shade|color=gold|25|DTLB: 8E,<br/>4K/4Mp, 4A}}<!-- SDM CPUID listing says 4K/4M, but this doesn't seem to be corroborated elsewhere; descriptor C0 appears to be a largepage-only DTLB for Bonnell-->
| {{shade|color=gold|80|{{nowrap|L2TLB: 1024E,}}<br/>4K/2Mp, 8A}}
| {{shade|color=gold|25|DTLB: 16E,<br/>{{nowrap|2M/4Mp, 4A<ref>Intel, [https://cdrdv2-public.intel.com/336345/336345_C3000_SU_Rev020.pdf Atom C3000 Processor Product Family Specification Update], order no. 336345-020, page 16, Mar 2023. [https://web.archive.org/web/20231007230100/https://cdrdv2-public.intel.com/336345/336345_C3000_SU_Rev020.pdf Archived] on 7 Oct 2023.</ref><!-- descriptor type C2h is mis-specified in the SDM, at least in rev 80-->}}}}
| {{shade|color=gold|80|style=line-height:1.2|{{small|Two L2 STLBs:<br/>{{nowrap|1536E, 4K/2Mp, 6A{{efn|1=For descriptor <code>C3h</code>, many Intel processors that use this descriptor have an L2 TLB that is 12-way set-associative, not 6-way set-associative. This applies to at least Skylake<ref>Intel, [https://web.archive.org/web/20230308232303/https://cdrdv2-public.intel.com/332689/332689_030.pdf 6th Generation Intel Processor Specification Update], order no. 332689-030, July 2023, see erratum SKL148 on page 66. Archived from the [https://cdrdv2-public.intel.com/332689/332689_030.pdf original] on 8 mar 2023.</ref> and Whiskey/Kaby/Coffee/Comet Lake<ref>Intel, [https://cdrdv2-public.intel.com/615213/615213_013.pdf 10th Generation Intel Core Processor Specification Update], order no. 615213-013, apr 2023, see erratum CML081 on page 41. [https://web.archive.org/web/20240719042916/https://cdrdv2-public.intel.com/615213/615213_013.pdf Archived] on 19 Jul 2024.</ref> CPUs.}}}}<br/>+ 16E, 1Gp, 4A}}}}
| {{shade|color=gold|25|DTLB: 32E,<br/>2M/4Mp, 4A}} ||   ||   ||  
! Cx
|   ||   || {{shade|color=gold|80|{{nowrap|L2TLB: 512E,}}<br/>4Kp, 4A}} ||   ||   ||   ||   ||  
! Cx
|-
! Dx
| {{shade|color=blue|100|L3C: 512K,<br/>4A, 64L}} || {{shade|color=blue|100|L3C: 1M,<br/>4A, 64L}} || {{shade|color=blue|100|L3C: 2M,<br/>4A, 64L}} ||   ||   ||   || {{shade|color=blue|100|L3C: 1M,<br/>8A, 64L}} || {{shade|color=blue|100|L3C: 2M,<br/>8A, 64L}}
! Dx
| {{shade|color=blue|100|L3C: 4M,<br/>8A, 64L}}||   ||   ||   || {{shade|color=blue|100|L3C: 1.5M,<br/>12A, 64L}} || {{shade|color=blue|100|L3C: 3M,<br/>12A, 64L}} || {{shade|color=blue|100|L3C: 6M,<br/>12A, 64L}} ||  
! Dx
|-
! Ex
|   ||   || {{shade|color=blue|100|L3C: 2M,<br/>16A, 64L}} || {{shade|color=blue|100|L3C: 4M,<br/>16A, 64L}} || {{shade|color=blue|100|L3C: 8M,<br/>16A, 64L}} ||   ||   ||  
! Ex
|   ||   || {{shade|color=blue|100|L3C: 12M,<br/>24A, 64L}} || {{shade|color=blue|100|L3C: 18M,<br/>24A, 64L<!--unusual because the cache size described does not have a power-of-2 number of sets, but it is listed consistently as not-power-of-2 in the SDM, AP-485, CPU datasheets and CPUID leaf 4, so must be presumed to be real--><ref>Intel, [https://www.intel.com.tw/content/dam/www/public/us/en/documents/datasheets/xeon-processor-7500-series-vol-2-datasheet.pdf Xeon Processor 7500 Series Datasheet], order no. 323341-001, March 2010, page 150. [https://web.archive.org/web/20231008003617/https://www.intel.com.tw/content/dam/www/public/us/en/documents/datasheets/xeon-processor-7500-series-vol-2-datasheet.pdf Archived] on Oct 8, 2023.</ref>}} || {{shade|color=blue|100|L3C: 24M,<br/>24A, 64L}} ||   ||   ||  
! Ex
|-
! Fx
| {{yes|64-byte<br/>prefetch{{efn|name=leaf2_prefetch|The prefetch specified by descriptors <code>F0h</code> and <code>F1h</code> is the recommended stride for memory prefetching with the <code>PREFETCHNTA</code> instruction.<ref>Intel, [https://cdrdv2-public.intel.com/814198/248966-Optimization-Reference-Manual-V1-049.pdf Optimization Reference Manual, volume 1], order no. 248966-049, jan 2024, chapter 9.6.3.3, p. 361. [https://web.archive.org/web/20240419195044/https://cdrdv2-public.intel.com/814198/248966-Optimization-Reference-Manual-V1-049.pdf Archived] on 19 Apr 2024.</ref>}}}} || {{yes|128-byte<br/>prefetch{{efn|name=leaf2_prefetch}}}} ||   ||   ||   ||   ||   ||  
! Fx
|   ||   ||   ||   ||   ||   || {{yes|Leaf 2 has<br/>no TLB info,<br/>use leaf 18h}} || {{yes|Leaf 2 has<br/>no cache info,<br/>use leaf 4}}
! Fx
|-
! !! x0 !! x1 !! x2 !! x3 !! x4 !! x5 !! x6 !! x7 !! !! x8 !! x9 !! xA !! xB !! xC !! xD !! xE !! xF !! 
|}
</div>
{{notelist}}
{{vpad}}

== EAX=3: Processor Serial Number ==
This returns the processor's serial number. The processor serial number was introduced on Intel [[Engineering:Pentium III|Pentium III]], but due to privacy concerns, this feature is no longer implemented on later models (the PSN feature bit is always cleared). [[Company:Transmeta|Transmeta's]] Efficeon and Crusoe processors also provide this feature. AMD CPUs however, do not implement this feature in any CPU models.

For Intel Pentium III CPUs, leaf 3 returns the bottom 64 bits of the 96-bit Processor Serial Number in EDX:ECX - the top 32 bits of the serial number are taken from the CPU signature returned in EAX when <code>CPUID</code> is called with EAX=1.<ref>Intel, [https://web.archive.org/web/20040121100718/http://wwwp.intel.com/design/pentiumiii/applnots/24512501.pdf AP-909 Application Note: Processor Serial Number], order no. 245125-001, March 1999. Archived from the [http://wwwp.intel.com:80/design/pentiumiii/applnots/24512501.pdf original] on 21 Jan 2004.</ref>.

For Transmeta Crusoe and Efficeon CPUs, leaf 3 returns a 128-bit Processor Serial Number in EAX:EBX:ECX:EDX<ref>Transmeta, [https://web.archive.org/web/20030319055403/http://www.transmeta.com/crusoe_docs/Crusoe_CPUID_5-7-02.pdf Processor Recognition], 7 May 2002, page 4. Archived from the [http://www.transmeta.com:80/crusoe_docs/Crusoe_CPUID_5-7-02.pdf original] on 19 March 2003.</ref> (The top 32 bits of this serial number, delivered in EAX, is always 0 on Crusoe processors<ref>Transmeta, [https://web.archive.org/web/20050513232437/http://www.transmeta.com/crusoe_docs/tm5900_bisoguide_040123.pdf Crusoe BIOS Programmer's Guide], 23 Jan 2004, page 12. Archived from the [http://www.transmeta.com:80/crusoe_docs/tm5900_bisoguide_040123.pdf original] on 13 May 2005.</ref> but is known to be nonzero on at least some Efficeon processors.<ref>InstlatX64, [http://users.atw.hu/instlatx64/GenuineTMx86/GenuineTMx860000F24_Efficeon_CPUID.txt Transmeta Efficieon 86x0 CPUID dump], see CPUID 00000003. [https://web.archive.org/web/20191207171306/http://users.atw.hu/instlatx64/GenuineTMx86/GenuineTMx860000F24_Efficeon_CPUID.txt Archived] on 7 Dec 2019.</ref>)   

Note that the processor serial number feature must be enabled in the [[BIOS]] setting in order to function.

== EAX=4 and EAX=8000'001Dh: Cache Hierarchy and Topology ==
These two leaves are used to provide information about the [[Cache hierarchy|cache hierarchy]] levels available to the processor core on which the <code>CPUID</code> instruction is run. Leaf <code>4</code> is used on Intel processors and leaf <code>8000'001Dh</code> is used on AMD processors - they both return data in EAX, EBX, ECX and EDX, using the same data format except that leaf <code>4</code> returns a few additional fields that are considered "reserved" for leaf <code>8000'001Dh</code>. They both provide CPU cache information in a series of sub-leaves selected by ECX - to get information about all the cache levels, it is necessary to invoke <code>CPUID</code> repeatedly, with EAX=<code>4</code> or <code>8000'001Dh</code> and ECX set to increasing values starting from 0 (0,1,2,...) until a sub-leaf not describing any caches (EAX[4:0]=0) is found. The sub-leaves that do return cache information may appear in any order, but all of them will appear before the first sub-leaf not describing any caches.

In the below table, fields that are defined for leaf <code>4</code> but not for leaf <code>8000'001Dh</code> are highlighted with yellow cell coloring and a '''(#4)''' item.

{| class="wikitable"
|+CPUID EAX=4 and 8000'001Dh: Cache property information in EAX, EBX and EDX
! Bit
! EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="15" |
! EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="15" |
! EDX{{efn|text=Intel AP-485, revisions 31<ref>Intel, [https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-031.pdf Processor Identification and the CPUID Instruction], order no. 241618-031, sep 2006, page 32.</ref> and 32, list bits 9:0 of EDX as a "Prefetch Stride" field - this was removed in revision 33 and all later Intel documentation, and no processor is known to use EDX in this manner.}} 
! Bit
|-
! 0
| rowspan=5 | Cache Type:
* 0: (No more caches)
* 1: Data Cache
* 2: Instruction Cache
* 3: Unified Cache
* 4-31: (reserved)
| rowspan=10 | System [[False sharing|coherency line size]] in bytes, {{nowrap|minus 1}}
| <code>WBINVD</code> cache invalidation execution scope.<br>A value of 0 indicates that the <code>INVD</code>/<code>WBINVD</code> instructions will invalidate all lower-levels caches of this cache, including caches that belong to sibling processors sharing this cache. A value of 1 indicates that lower-level caches of sibling processors that are sharing this cache are not guaranteed to be all cleared.
! 0
|-
! 1
| Cache inclusiveness. If 1, then cache is inclusive of lower-level caches.
! 1
|-
! 2
| {{maybe|Complex cache indexing. If 1, then cache uses a complex function for cache indexing, else the cache is direct-mapped. '''(#4)'''}}
! 2
|-
! 3
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 3
|-
! 4
| style="text-align:center; background:lightgrey;" | ''(reserved)''<!-- Bit used for unknown purpose for L2 cache of Xeon Phi "Knights Landing" processors -->
! 4
|-
! 7:5
| Cache Level (starting from 1)
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 7:5
|-
! 8
| Self initializing cache level (1=doesn't need software initialization after reset)
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 8
|-
! 9
| Fully Associative Cache
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 9
|-
! 10
| {{maybe|(<code>WBINVD</code> cache invalidation execution scope){{efn|name=leaf4_knc|For CPUID leaf 4, bits 11:10 of EAX are documented for the Xeon Phi "Knights Corner" (<code>GenuineIntel</code> Family <code>0Bh</code>) processor only.<ref name="intel_knc_ref" /> For other processors, bits 1:0 of EDX should be used instead.}} '''(#4)'''}}
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 10
|-
! 11
| {{maybe|(Cache Inclusiveness){{efn|name=leaf4_knc}} '''(#4)'''}}
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 11
|-
! 13:12
| style="text-align:center; background:lightgrey;" | ''(reserved)''
| rowspan=2 | Physical line partitions (number of cache lines that share a cache address tag), {{nowrap|minus 1}}
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 13:12
|-
! 21:14
| rowspan=2 | Maximum number of addressable IDs for logical processors sharing this cache, {{nowrap|minus 1}}
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 21:14
|-
! 25:22
| rowspan=2 | Ways of [[Cache placement policies#Set-associative cache|cache associativity]], {{nowrap|minus 1}}
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 25:22
|-
! 31:26
| {{maybe|Maximum number of addressable IDs for processor cores in physical package, {{nowrap|minus 1}} '''(#4)'''}}
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 31:26
|}
{{notelist}}
{{vpad}}
For any caches that are valid and not fully-associative, the value returned in ECX is the number of sets in the cache minus 1. (For fully-associative caches, ECX should be treated as if it return the value 0.)
For any given cache described by a sub-leaf of <code>CPUID</code> leaf <code>4</code> or <code>8000'001Dh</code>, the total cache size in bytes can be computed as:

<code>CacheSize = (EBX[11:0]+1) * (EBX[21:12]+1) * (EBX[31:22]+1) * (ECX+1)</code>

For example, on Intel Crystalwell CPUs, executing CPUID with EAX=4 and ECX=4 will cause the processor to return the following size information for its level-4 cache in EBX and ECX: <code>EBX=03C0F03F</code> and <code>ECX=00001FFF</code> - this should be taken to mean that this cache has a cache line size of 64 bytes (EBX[11:0]+1), has 16 cache lines per tag (EBX[21:12]+1), is 16-way set-associative (EBX[31:22]+1) with 8192 sets (ECX+1), for a total size of 64*16*16*8192=134217728 bytes, or 128 mebibytes.
{{vpad}}

== EAX=4 and EAX=Bh: Intel Thread/Core and Cache Topology ==
These two leaves are used for processor topology (thread, core, package) and cache hierarchy enumeration in Intel multi-core (and hyperthreaded) processors.<ref name="topo">{{cite web|url=https://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/|title=Intel 64 Architecture Processor Topology Enumeration|author=Shih Kuo|date=Jan 27, 2012}}</ref> {{As of|2013}} AMD does not use these leaves but has alternate ways of doing the core enumeration.<ref>{{cite web |url=http://developer.amd.com/resources/documentation-articles/articles-whitepapers/processor-and-core-enumeration-using-cpuid/ |title=Processor and Core Enumeration Using CPUID {{pipe}} AMD |publisher=Developer.amd.com |access-date=2014-07-10 |archive-url=https://web.archive.org/web/20140714221717/http://developer.amd.com/resources/documentation-articles/articles-whitepapers/processor-and-core-enumeration-using-cpuid/ |archive-date=2014-07-14 |url-status=dead }}</ref>

Unlike most other CPUID leaves, leaf Bh will return different values in EDX depending on which logical processor the CPUID instruction runs; the value returned in EDX is actually the x2APIC id of the logical processor. The x2APIC id space is not continuously mapped to logical processors, however; there can be gaps in the mapping, meaning that some intermediate x2APIC ids don't necessarily correspond to any logical processor. Additional information for mapping the x2APIC ids to cores is provided in the other registers. Although the leaf Bh has sub-leaves (selected by ECX as described further below), the value returned in EDX is only affected by the logical processor on which the instruction is running but not by the subleaf.

The processor(s) topology exposed by leaf Bh is a hierarchical one, but with the strange caveat that the order of (logical) levels in this hierarchy doesn't necessarily correspond to the order in the physical hierarchy ([[Simultaneous multithreading|SMT]]/core/package). However, every logical level can be queried as an ECX subleaf (of the Bh leaf) for its correspondence to a "level type", which can be either SMT, core, or "invalid". The level id space starts at 0 and is continuous, meaning that if a level id is invalid, all higher level ids will also be invalid. The level type is returned in bits 15:08 of ECX, while the number of logical processors at the level queried is returned in EBX. Finally, the connection between these levels and x2APIC ids is returned in EAX[4:0] as the number of bits that the x2APIC id must be shifted in order to obtain a unique id at the next level.

As an example, a dual-core [[Engineering:Westmere (microarchitecture)|Westmere]] processor capable of hyperthreading (thus having two cores and four threads in total) could have x2APIC ids 0, 1, 4 and 5 for its four logical processors. Leaf Bh (=EAX), subleaf 0 (=ECX) of CPUID could for instance return 100h in ECX, meaning that level 0 describes the SMT (hyperthreading) layer, and return 2 in EBX because there are two logical processors (SMT units) per physical core. The value returned in EAX for this 0-subleaf should be 1 in this case, because shifting the aforementioned x2APIC ids to the right by one bit gives a unique core number (at the next level of the level id hierarchy) and erases the SMT id bit inside each core. A simpler way to interpret this information is that the last bit (bit number 0) of the x2APIC id identifies the SMT/hyperthreading unit inside each core in our example. Advancing to subleaf 1 (by making another call to CPUID with EAX=Bh and ECX=1) could for instance return 201h in ECX, meaning that this is a core-type level, and 4 in EBX because there are 4 logical processors in the package; EAX returned could be any value greater than 3, because it so happens that bit number 2 is used to identify the core in the x2APIC id. Note that bit number 1 of the x2APIC id is not used in this example. However, EAX returned at this level could well be 4 (and it happens to be so on a Clarkdale Core i3 5x0) because that also gives a unique id at the package level (=0 obviously) when shifting the x2APIC id by 4 bits. Finally, you may wonder what the EAX=4 leaf can tell us that we didn't find out already. In EAX[31:26] it returns the APIC mask bits ''reserved'' for a package; that would be 111b in our example because bits 0 to 2 are used for identifying logical processors inside this package, but bit 1 is also reserved although not used as part of the logical processor identification scheme. In other words, APIC ids 0 to 7 are reserved for the package, even though half of these values don't map to a logical processor.

The cache hierarchy of the processor is explored by looking at the sub-leaves of leaf 4. The APIC ids are also used in this hierarchy to convey information about how the different levels of cache are shared by the SMT units and cores. To continue our example, the L2 cache, which is shared by SMT units of the same core but not between physical cores on the Westmere is indicated by EAX[26:14] being set to 1, while the information that the L3 cache is shared by the whole package is indicated by setting those bits to (at least) 111b. The cache details, including cache type, size, and associativity are communicated via the other registers on leaf 4.

Beware that older versions of the Intel app note 485 contain some misleading information, particularly with respect to identifying and counting cores in a multi-core processor;<ref>{{cite web|url=https://software.intel.com/en-us/forums/topic/352709#comment-1719904 |title=Sandybridge processors report incorrect core number? |publisher=Software.intel.com |date=2012-12-29 |access-date=2014-07-10}}</ref> errors from misinterpreting this information have even been incorporated in the Microsoft sample code for using CPUID, even for the 2013 edition of Visual Studio,<ref>{{cite web|url=http://msdn.microsoft.com/en-us/library/hskdteyh.aspx |title=cpuid, __cpuidex |publisher=Msdn.microsoft.com |date=2014-06-20 |access-date=2014-07-10}}</ref> but the Intel code sample for identifying processor topology<ref name="topo"/> has the correct interpretation, and the current Intel Software Developer's Manual has a more clear language. The (open source) cross-platform production code<ref name="wildfire">{{cite web|url=http://trac.wildfiregames.com/browser/ps/trunk/source/lib/sysdep/arch/x86_x64/topology.cpp |title=topology.cpp in ps/trunk/source/lib/sysdep/arch/x86_x64 – Wildfire Games |publisher=Trac.wildfiregames.com |date=2011-12-27 |access-date=2014-07-10 |archive-url=https://web.archive.org/web/20210309001211/http://trac.wildfiregames.com/browser/ps/trunk/source/lib/sysdep/arch/x86_x64/topology.cpp |archive-date=2021-03-09}}</ref> from [[Company:Wildfire Games|Wildfire Games]] also implements the correct interpretation of the Intel documentation.

Topology detection examples involving older (pre-2010) Intel processors that lack x2APIC (thus don't implement the EAX=Bh leaf) are given in a 2010 Intel presentation.<ref>[https://software.intel.com/en-us/articles/hyper-threading-technology-and-multi-core-processor-detection Hyper-Threading Technology and Multi-Core Processor Detection]</ref> Beware that using that older detection method on 2010 and newer Intel processors may overestimate the number of cores and logical processors because the old detection method assumes there are no gaps in the APIC id space, and this assumption is violated by some newer processors (starting with the Core i3 5x0 series), but these newer processors also come with an x2APIC, so their topology can be correctly determined using the EAX=Bh leaf method.

== EAX=5: MONITOR/MWAIT Features ==
This returns feature information related to the <code>MONITOR</code> and <code>MWAIT</code> instructions in the EAX, EBX, ECX and EDX registers.
{| class="wikitable"
|+CPUID EAX=5: MONITOR/MWAIT feature information in EAX, EBX, EDX
! Bit
! EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="9" |
! EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="9" |
! EDX
! Bit
|-
! 3:0
| rowspan="4" | Smallest monitor-line size in bytes
| rowspan="4" | Largest monitor-line size in bytes
| Number of C0{{efn|1=The C0 to C7 states are processor-specific C-states, which do not necessarily correspond 1:1 to [[ACPI#Processor states|ACPI C-states]].}} sub-states supported for <code>MWAIT</code>
! 3:0
|-
! 7:4
| Number of C1 sub-states supported for <code>MWAIT</code>
! 7:4
|-
! 11:8
| Number of C2 sub-states supported for <code>MWAIT</code>
! 11:8
|-
! 15:12
| Number of C3 sub-states supported for <code>MWAIT</code>
! 15:12
|-
! 19:16
| rowspan="4" style="text-align:center; background:lightgrey;" | ''(reserved)''
| rowspan="4" style="text-align:center; background:lightgrey;" | ''(reserved)''
| Number of C4 sub-states supported for <code>MWAIT</code>
! 19:16
|-
! 23:20
| Number of C5 sub-states supported for <code>MWAIT</code>
! 23:20
|-
! 27:24
| Number of C6 sub-states supported for <code>MWAIT</code>
! 27:24
|-
! 31:28
| Number of C7 sub-states supported for <code>MWAIT</code>
! 31:28
|}
{{notelist}}
{| class="wikitable"
|+CPUID EAX=5: MONITOR/MWAIT extension enumeration in ECX
! rowspan="2" | Bit
! colspan="2" | ECX
|-
! Short
! Feature
|-
! 0
| EMX || Enumeration of MONITOR/MWAIT extensions in ECX and EDX supported
|-
! 1
| IBE || Supports treating interrupts as break-events for <code>MWAIT</code> even when interrupts are disabled
|-
! 2
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
|-
! 3
| Monitorless_&shy;MWAIT || Allow <code>MWAIT</code> to be used for power management without setting up memory monitoring with <code>MONITOR</code><ref>Intel, [https://cdrdv2-public.intel.com/819680/architecture-instruction-set-extensions-programming-reference.pdf Architecture Instruction Set Extensions Programming Reference], order no. 319433-052, March 2024, chapter 17. [https://web.archive.org/web/20240407230452/https://cdrdv2-public.intel.com/819680/architecture-instruction-set-extensions-programming-reference.pdf Archived] on Apr 7, 2024.</ref>
|-
! <br/>31:4<br/>&nbsp;
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
|}

== EAX=6: Thermal and Power Management ==
This returns feature bits in the EAX register and additional information in the EBX, ECX and EDX registers.
{| class="wikitable"
|+CPUID EAX=6: Thermal/power management feature bits in EAX
! rowspan="2" | Bit
! colspan="2" | EAX
|-
! Short
! Feature
|-
! 0
| DTS || Digital Thermal Sensor capability
|-
! 1
| TURBO_BOOST || [[Engineering:Intel Turbo Boost|Intel Turbo Boost]] Technology capability
|-
! 2
| ARAT{{efn|text=On Intel Pentium 4 family processors (<code>GenuineIntel</code> family 0Fh) only, bit 2 of EAX is used to indicate OPP (Operating Point Protection)<ref>Intel, [https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-030.pdf Intel Processor Identification and the CPUID Instruction (AP-485, rev 30)], order no. 241618-030, Jan 2006, page 19.</ref><!-- OPP mentioned only in rev 30 of AP-485, not any other revision --> instead of ARAT.}} || Always Running [[Advanced Programmable Interrupt Controller|APIC]] Timer capability
|-
! 3
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
|-
! 4
| PLN || Power Limit Notification capability
|-
! 5
| ECMD || Extended Clock Modulation Duty capability
|-
! 6
| PTM || Package Thermal Management capability
|-
! 7
| HWP || Hardware-controlled [[ACPI#Performance state|Performance States]]. MSRs added:
* <code>IA32_PM_ENABLE</code>(<code>770h</code>)
* <code>IA32_HWP_CAPABILITIES</code>(<code>771h</code>)
* <code>IA32_HWP_REQUEST</code>(<code>774h</code>)
* <code>IA32_HWP_STATUS</code>(<code>777h</code>)
|-
! 8
| HWP_Notification || HWP notification of dynamic guaranteed performance change - <code>IA32_HWP_INTERRUPT</code>(<code>773h</code>) MSR
|-
! 9
| HWP_Activity_&shy;Window || HWP Activity Window control - bits 41:32 of <code>IA32_HWP_REQUEST</code> MSR
|-
! 10
| HWP_Energy_&shy;Performance_&shy;Preference || HWP Energy/performance preference control - bits 31:24 of <code>IA32_HWP_REQUEST</code> MSR
|-
! 11
| HWP_Package_&shy;Level_Request || HWP Package-level control - <code>IA32_HWP_REQUEST_PKG</code>(<code>772h</code>) MSR
|-
! 12
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
|-
! 13
| HDC || Hardware [[Engineering:Duty cycle|Duty Cycling]] supported. MSRs added:
* <code>IA32_PKG_HDC_CTL</code> (<code>DB0h</code>)
* <code>IA32_PM_CTL1</code> (<code>DB1h</code>)
* <code>IA32_THREAD_STALL</code> (<code>DB2h</code>)
|-
! 14
| TURBO_&shy;BOOST_MAX || [[Engineering:Intel Turbo Boost|Intel Turbo Boost]] Max Technology 3.0 available
|-
! 15
| HWP_CAP || Interrupts upon changes to <code>IA32_HWP_CAPABILITIES</code>.Highest_Performance (bits 7:0) supported<!-- SDM 352462-079 volume 3B, section 15.4.6, page 3506 -->
|-
! 16
| HWP_PECI_&shy;OVERRIDE || HWP [[Platform Environment Control Interface|PECI]] override supported - bits 63:60 of <code>IA32_HWP_PECI_REQUEST_INFO</code>(<code>775h</code>) MSR
|-
! 17
| FLEXIBLE_&shy;HWP || Flexible HWP - bits 63:59 of <code>IA32_HWP_REQUEST</code> MSR<!-- SDM 352462-079 volume 3B, section 15.4.4.1 -->
|-
! 18
| HWP_REQUEST_&shy;FAST_ACCESS || Fast access mode for <code>IA32_HWP_REQUEST</code> MSR supported{{efn|To enable fast (non-serializing) access mode for the <code>IA32_HWP_REQUEST</code> MSR on CPUs that support it, it is necessary to set bit 0 of the <code>FAST_UNCORE_MSRS_CTL</code>(<code>657h</code>) MSR.}}
|-
! 19
| HW_FEEDBACK || Hardware Feedback Interface. Added MSRs:
* <code>IA32_HW_FEEDBACK_PTR</code>(<code>17D0h</code>)
* <code>IA32_HW_FEEDBACK_CONFIG</code>(<code>17D1h</code>) (bit 0 enables HFI, bit 1 enables Intel Thread Director)
|-
! 20
| HWP_REQUEST_&shy;IGNORE_IDLE || <code>IA32_HWP_REQUEST</code> of idle logical processor ignored when only one of two logical processors that share a physical processor is active. 
|-
! 21
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
|-
! 22
| HWP Control MSR || <code>IA32_HWP_CTL</code>(<code>776h</code>) MSR supported<ref>Intel, [https://kib.kiev.ua/x86docs/Intel/SDMs/325462-079.pdf Intel 64 and IA-32 Architecture Software Developer's Manual], order no. 352462-079, volume 3B, section 15.4.4.4, page 3503</ref><!-- SDM 352462-079: bit 22 is listed as "reserved" by the CPUID section in volume 2A, but is described as a feature-bit for this MSR in section 15.4.4.4 of volume 3B (page 3503) and table 2-2 of volume 4 (page 4568) -->
|-
! 23
| THREAD_&shy;DIRECTOR || Intel Thread Director supported. Added MSRs:
* <code>IA32_THREAD_FEEDBACK_CHAR</code>(<code>17D2h</code>)<!-- SDM 352462-079: volume 4, table 2.2 - uses a different name than the CPUID section in volume 2A --> 
* <code>IA32_HW_FEEDBACK_THREAD_CONFIG</code>(<code>17D4h</code>)
|-
! 24
| style="background:lightgrey;" | || style="background:lightgrey;" | ({{mono|IA32_THERM_INTERRUPT}} MSR bit 25 supported){{efn|1=The CPUID.(EAX=6):EAX[24] bit is listed in revisions 078 to 087 of the Intel SDM, but was removed from revision 088 onwards. It is not set in any known processor.}}
|-
! <br/>31:25<br/>&nbsp;
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
|}
{{notelist}}
{{vpad}}
{| class="wikitable"
|+CPUID EAX=6: Thermal/power management feature fields in EBX, ECX and EDX
! Bit
! EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="9" |
! ECX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="9" |
! EDX
! Bit
|-
! 0
| rowspan="4" | Number of Interrupt Thresholds in Digital Thermal Sensor
| Effective frequency interface supported - <code>IA32_MPERF</code>(<code>0E7h</code>) and <code>IA32_APERF</code>(<code>0E8h</code>) MSRs
| Hardware Feedback reporting: Performance Capability Reporting supported
! 0
|-
! 1
| (ACNT2 Capability){{efn|text=The "ACNT2 Capability" bit is listed in Intel AP-485 rev 038<ref>Intel, [https://kib.kiev.ua/x86docs/Intel/AppNote485/241618-038.pdf Processor Identification and the CPUID Instruction], order no. 241618-038, apr 2012, p.38</ref> and 039, but not listed in any revision of the Intel SDM. The feature is known to exist in only a few Intel CPUs, e.g. Xeon "Harpertown" stepping E0.<ref>Intel, [https://web.archive.org/web/20230511191706/https://qdms.intel.com/dm/d.aspx/4E8B0DA3-C0C1-49FF-8592-F3C36E417233/PCN108701-00.pdf Product Change Notification 108701], 1 aug 2008. Archived on May 11, 2023</ref>}}
| Hardware Feedback reporting: Efficiency Capability Reporting supported
! 1
|-
! 2
| style="text-align:center; background:lightgrey;" | ''(reserved)''
| rowspan="3" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 2
|-
! 3
| Performance-Energy Bias capability - <code>IA32_ENERGY_PERF_BIAS</code>(<code>1B0h</code>) MSR
! 3
|-
! 7:4
| rowspan="4" style="text-align:center; background:lightgrey;" | ''(reserved)''
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 7:4
|-
! 11:8
| rowspan="2" | Number of Intel Thread Director classes supported by hardware
| Size of Hardware Feedback interface structure (in units of 4&nbsp;KiB) minus 1
! 11:8
|-
! 15:12
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 15:12
|-
! <br/>31:16<br/>&nbsp;
| style="text-align:center; background:lightgrey;" | ''(reserved)''<!-- ECX Bit 30 set for unknown purpose in AMD 4800S Desktop Kit : http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0880F40_K17_CPUID.txt -->
| Index of this logical processor's row in hardware feedback interface structure
! <br/>31:16<br/>&nbsp;
|}
{{notelist}}
{{vpad}}

== EAX=7, ECX=0: Extended Features ==
This returns extended feature flags in EBX, ECX, and EDX. Returns the maximum ECX value for EAX=7 in EAX.

{| class="wikitable"
|+ CPUID EAX=7,ECX=0: Extended feature bits in EBX, ECX and EDX
! rowspan="2" | Bit 
! colspan="2" | EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="34" |
! colspan="2" | ECX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="34" |
! colspan="2" | EDX
! rowspan="2" | Bit
|-
! Short
! Feature
! Short
! Feature
! Short
! Feature
|-
! 0
| fsgsbase || Access to base of %fs and %gs
| prefetchwt1 || <code>PREFETCHWT1</code> instruction
| style="background:lightgrey;" | (sgx-tem){{efn|name=leaf7_0_tdx}} || style="background:lightgrey;" | ?
! 0
|-
! 1
| tsc_adjust || IA32_TSC_ADJUST MSR
| avx512-vbmi || [[AVX-512]] Vector Bit Manipulation Instructions
| sgx-keys || Attestation Services for [[Software Guard Extensions|Intel SGX]]
! 1
|-
! 2
| sgx || [[Software Guard Extensions]]
| umip || User-mode Instruction Prevention
| avx512-4vnniw || [[AVX-512#4FMAPS and 4VNNIW|AVX-512]] 4-register Neural Network Instructions 
! 2
|-
! 3
| bmi1 || [[Bit Manipulation Instruction Sets#BMI1|Bit Manipulation Instruction Set 1]]
| pku || Memory Protection Keys for User-mode pages
| avx512-4fmaps || [[AVX-512#4FMAPS and 4VNNIW|AVX-512]] 4-register Multiply Accumulation Single precision
! 3
|-
! 4
| hle || [[Transactional Synchronization Extensions|TSX]] Hardware Lock Elision
| ospke || PKU enabled by OS
| fsrm || Fast Short {{nowrap|<code>REP MOVSB</code>}}
! 4
|-
! 5
| avx2 || Advanced Vector Extensions 2
| waitpkg || Timed pause and user-level monitor/wait instructions (<code>TPAUSE</code>, <code>UMONITOR</code>, <code>UMWAIT</code>)
| uintr || User Inter-processor Interrupts
! 5
|-
! 6
| fdp-excptn-only || [[X87|x87]] FPU data pointer register updated on exceptions only
| avx512-vbmi2 || [[AVX-512#VBMI2|AVX-512]] Vector Bit Manipulation Instructions 2
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 6
|-
! 7
| smep || Supervisor Mode Execution Prevention
| cet_ss/shstk || Control flow enforcement (CET): shadow stack (SHSTK alternative name)
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 7
|-
! 8
| bmi2 || [[Bit Manipulation Instruction Sets#BMI2|Bit Manipulation Instruction Set 2]]
| gfni || Galois Field instructions
| avx512-vp2intersect || [[AVX-512#VP2INTERSECT|AVX-512]] vector intersection instructions on 32/64-bit integers
! 8
|-
! 9
| erms || Enhanced {{nowrap|<code>REP MOVSB/STOSB</code>}}
| vaes || Vector [[AES instruction set]] (VEX-256/EVEX)
| srbds-ctrl || Special Register Buffer Data Sampling Mitigations
! 9
|-
! 10
| invpcid || <code>INVPCID</code> instruction
| vpclmulqdq || [[CLMUL instruction set]] (VEX-256/EVEX)
| md-clear || <code>VERW</code> instruction clears CPU buffers 
! 10
|-
! 11
| rtm || [[Transactional Synchronization Extensions|TSX]] Restricted Transactional Memory
| avx512-vnni || [[AVX-512]] Vector Neural Network Instructions
| rtm-always-abort<ref name="tsx-memory-ordering">{{Cite web |date=June 2023 |title=Performance Monitoring Impact of Intel Transactional Synchronization Extension Memory Ordering Issue |url=https://cdrdv2.intel.com/v1/dl/getContent/604224 |access-date=8 May 2024 |website=[[Company:Intel|Intel]] |page=8 |format=PDF}}</ref> || All TSX transactions are aborted
! 11
|-
! 12
| rdt-m/pqm || Intel Resource Director (RDT) Monitoring ''or'' AMD Platform QOS Monitoring
| avx512-bitalg || [[AVX-512]] BITALG instructions
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 12
|-
! 13
| fcs_fds_&shy;deprecation|| [[X87|x87]] FPU CS and DS deprecated
| tme_en || Total Memory Encryption MSRs available 
| rtm-force-abort<ref name="tsx-memory-ordering" /> || TSX_FORCE_ABORT (MSR <code>0x10f</code>) is available
! 13
|-
! 14
| mpx || [[Intel MPX]] (Memory Protection Extensions)
| avx512-vpopcntdq || AVX-512 Vector Population Count Double and Quad-word
| serialize || <code>SERIALIZE</code> instruction
! 14
|-
! 15
| rdt-a/pqe || Intel Resource Director (RDT) Allocation ''or'' AMD Platform QOS Enforcement
| style="background:lightgrey;" | (fzm){{efn|name=leaf7_0_tdx|text=As of April 2024, the FZM, MPRR and SGX_TEM bits are listed only in Intel [[Trust Domain Extensions|TDX]] documentation<ref name="intel_tdx_2020">Intel, [https://web.archive.org/web/20210729201408/https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-module-1eas.pdf Architecture Specification: Intel Trust Domain Extensions (Intel TDX) Module], order no. 344425-001, sep 2020,<!-- some CPUID bits in revision 001 of this documented are omitted from later revisions--> pages 120-122. Archived from the [https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-module-1eas.pdf original] on Jul 29, 2021.</ref> and are not set in any known processor.}} || style="background:lightgrey;" | ?
| hybrid || Mixture of CPU types in processor topology (e.g. [[Engineering:Alder Lake|Alder Lake]])
! 15
|-
! 16
| avx512-f || [[AVX-512]] Foundation
| la57 || [[Intel 5-level paging|5-level paging]] (57 address bits)
| tsxldtrk || [[Transactional Synchronization Extensions|TSX]] load address tracking suspend/resume instructions (<code>TSUSLDTRK</code> and <code>TRESLDTRK</code>)
! 16
|-
! 17
| avx512-dq || [[AVX-512]] Doubleword and Quadword Instructions
| rowspan="5" | mawau || rowspan="5" | The value of userspace MPX Address-Width Adjust used by the <code>BNDLDX</code> and <code>BNDSTX</code> [[Intel MPX]] instructions in 64-bit mode
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 17
|-
! 18
| rdseed || <code>RDSEED</code> instruction
| pconfig || Platform configuration (Memory Encryption Technologies Instructions) 
! 18
|-
! 19
| adx || [[Intel ADX]] (Multi-Precision Add-Carry Instruction Extensions)
| lbr || Architectural Last Branch Records
! 19
|-
! 20
| smap || [[Supervisor Mode Access Prevention]]
| cet-ibt || Control flow enforcement (CET): indirect branch tracking
! 20
|-
! 21
| avx512-ifma || [[AVX-512#IFMA|AVX-512]] Integer Fused Multiply-Add Instructions
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 21
|-
! 22
| style="background:lightgrey;" | (pcommit) || style="background:lightgrey;" | ({{mono|PCOMMIT}} instruction, deprecated)<ref>Intel, [https://www.intel.com/content/www/us/en/developer/articles/technical/deprecate-pcommit-instruction.html Deprecating the PCOMMIT instruction], sep 12, 2016. [https://web.archive.org/web/20240305173122/https://www.intel.com/content/www/us/en/developer/articles/technical/deprecate-pcommit-instruction.html Archived] on Mar 5, 2024.</ref>
| rdpid || <code>RDPID</code> (Read Processor ID) instruction and IA32_TSC_AUX MSR
| amx-bf16 || [[Advanced Matrix Extensions|AMX]] tile computation on [[Bfloat16 floating-point format|bfloat16]] numbers
! 22
|-
! 23
| clflushopt || <code>CLFLUSHOPT</code> instruction
| kl || AES Key Locker
| avx512-fp16 || [[AVX-512]] half-precision floating-point arithmetic instructions<ref>Intel, [https://cdrdv2-public.intel.com/678970/intel-avx512-fp16.pdf AVX512-FP16 Architecture Specification] (PDF), document number 347407-001, June 2021. [https://web.archive.org/web/20221026062138/https://cdrdv2-public.intel.com/678970/intel-avx512-fp16.pdf Archived] on Oct 26, 2022</ref>
! 23
|-
! 24
| clwb || <code>CLWB</code> (Cache line writeback) instruction
| bus-lock-detect || Bus lock debug exceptions
| amx-tile || [[Advanced Matrix Extensions|AMX]] tile load/store instructions
! 24
|-
! 25
| pt || Intel Processor Trace
| cldemote || <code>CLDEMOTE</code> (Cache line demote) instruction
| amx-int8 || [[Advanced Matrix Extensions|AMX]] tile computation on 8-bit integers
! 25
|-
! 26
| avx512-pf || [[AVX-512]] Prefetch Instructions
| style="background:lightgrey;" | (mprr){{efn|name=leaf7_0_tdx}} || style="background:lightgrey;" | ?
| ibrs / spec_ctrl || Speculation Control, part of Indirect Branch Control (IBC):<br />Indirect Branch Restricted Speculation (IBRS) and<br />Indirect Branch Prediction Barrier (IBPB)<ref name="Intel_2018_SESEM">{{cite web |title=Speculative Execution Side Channel Mitigations |version=Revision 2.0 |date=May 2018 |orig-year=January 2018 |id=Document Number: 336996-002 |publisher=[[Company:Intel|Intel]] |url=https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf |access-date=2018-05-26}}</ref><ref>{{Cite web | url=https://lwn.net/Articles/743019/ | title=IBRS patch series [LWN.net]}}</ref>
! 26
|-
! 27
| avx512-er || [[AVX-512]] Exponential and Reciprocal Instructions
| movdiri || <code>MOVDIRI</code> instruction
| stibp || Single Thread Indirect Branch Predictor, part of IBC<ref name="Intel_2018_SESEM"/>
! 27
|-
! 28
| avx512-cd || [[AVX-512]] Conflict Detection Instructions
| movdir64b || <code>MOVDIR64B</code> (64-byte direct store) instruction
| L1D_FLUSH || IA32_FLUSH_CMD MSR
! 28
|-
! 29
| sha || [[Intel SHA extensions|SHA-1 and SHA-256 extensions]]
| enqcmd || Enqueue Stores and <code>EMQCMD</code>/<code>EMQCMDS</code> instructions
| arch_&shy;capabilities || IA32_ARCH_CAPABILITIES MSR (lists speculative side channel mitigations<ref name="Intel_2018_SESEM"/>)
! 29
|-
! 30
| avx512-bw || [[AVX-512]] Byte and Word Instructions
| sgx-lc || [[Software Guard Extensions|SGX]] Launch Configuration
| core_&shy;capabilities || IA32_CORE_CAPABILITIES MSR (lists model-specific core capabilities)
! 30
|-
! 31
| avx512-vl || [[AVX-512]] Vector Length Extensions
| pks || Protection keys for supervisor-mode pages
| ssbd || Speculative Store Bypass Disable,<ref name="Intel_2018_SESEM"/> as mitigation for [[Speculative Store Bypass]] (IA32_SPEC_CTRL)
! 31
|}
{{notelist}}
{{vpad}}

== <span id="IBC"></span><span id="IBPB"></span><span id="IBRS"></span><span id="STIBP"></span><span id="SSBD"></span>EAX=7, ECX=1: Extended Features ==
This returns extended feature flags in all four registers.

{| class="wikitable"
|+ CPUID EAX=7,ECX=1: Extended feature bits in EAX, EBX, ECX, and EDX
! rowspan="2" | Bit
! colspan="2" | EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="34" |
! colspan="2" | EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="34" |
! colspan="2" | ECX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="34" |
! colspan="2" | EDX
! rowspan="2" | Bit
|-
! Short || Feature
! Short || Feature
! Short || Feature
! Short || Feature
|-
! 0
| sha512 || [[Intel SHA extensions|SHA-512 extensions]]
| ppin || Intel PPIN (Protected Processor Inventory Number): IA32_PPIN_CTL (<code>04Eh</code>) and IA32_PPIN (<code>04Fh</code>) MSRs.
| RDT_M_&shy;ASYM || Asymmetric RDT Monitoring capability  
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 0
|-
! 1
| sm3 || [[SM3 (hash function)|SM3 hash extensions]]
| pbndkb || Total Storage Encryption: <code>PBNDKB</code> instruction and TSE_CAPABILITY (<code>9F1h</code>) MSR.
| RDT_A_&shy;ASYM || Asymmetric RDT Allocation capability
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 1
|-
! 2
| sm4 || SM4 cipher extensions
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| style="background:lightgrey;" | (legacy_&shy;reduced_&shy;isa) || style="background:lightgrey;" | (X86S,<ref>Intel, [https://web.archive.org/web/20241002150150/https://cdrdv2-public.intel.com/776648/x86s-eas-external-1.2.pdf X86S External Architecture Specification] v1.2, June 2024, order no. 351407-002, section 3.5, page 13. Archived from the [https://cdrdv2-public.intel.com/776648/x86s-eas-external-1.2.pdf original] on 2 Oct 2024.</ref> cancelled<ref>Intel, [https://www.intel.com/content/www/us/en/developer/articles/technical/envisioning-future-simplified-architecture.html Envisioning a Simplified Intel Architecture] - as of 20 Dec 2024, contains a mention that Intel has chosen not to pursue X86S. [https://web.archive.org/web/20241220104422/https://www.intel.com/content/www/us/en/developer/articles/technical/envisioning-future-simplified-architecture.html Archived] on 20 Dec 2024.</ref>)
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 2
|-
! 3
| rao-int || Remote Atomic Operations on integers: <code>AADD</code>, <code>AAND</code>, <code>AOR</code>, <code>AXOR</code> instructions
| CPUID&shy;MAXVAL_&shy;LIM_RMV || If 1, then bit 22 of <code>IA32_MISC_ENABLE</code> cannot be set to 1 to limit the value returned by <code>CPUID.(EAX=0):EAX[7:0]</code>.
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 3
|-
! 4
| avx-vnni || [[Advanced Vector Extensions|AVX]] Vector Neural Network Instructions (VNNI) (VEX encoded)
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| style="background:lightgrey;" | (sipi64) || style="background:lightgrey;" | 64-bit SIPI (Startup InterProcessor Interrupt) (part of cancelled X86S)
| avx-vnni-int8 || AVX VNNI INT8 instructions
! 4
|-
! 5
| avx512-bf16 || [[AVX-512]] instructions for [[Bfloat16 floating-point format|bfloat16]] numbers
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| MSR_IMM || Immediate forms of the <code>RDMSR</code> and <code>WRMSRNS</code> instructions
| avx-ne-convert || AVX no-exception FP conversion instructions (bfloat16↔FP32 and FP16→FP32)
! 5
|-
! 6
| lass || Linear Address Space Separation (CR4 bit 27)
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 6
|-
! 7
| cmpccxadd || <code>CMPccXADD</code> instructions
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 7
|-
! 8
| archperf&shy;monext || Architectural Performance Monitoring Extended Leaf (EAX=23h)
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| amx-complex || [[Advanced Matrix Extensions|AMX]] support for "complex" tiles (<code>TCMMIMFP16PS</code> and <code>TCMMRLFP16PS</code>)
! 8
|-
! 9
| style="background:lightgrey;" | (dedup){{efn|text=As of April 2024, the DEDUP bit is listed only in Intel [[Trust Domain Extensions|TDX]] documentation<ref name="intel_tdx_2020" /> and is not set in any known processor.}} || style="background:lightgrey;" | ?
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 9
|-
! 10
| fzrm || Fast zero-length {{nowrap|<code> REP MOVSB</code>}}
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| avx-vnni-int16 || AVX VNNI INT16 instructions
! 10
|-
! 11
| fsrs || Fast short {{nowrap|<code>REP STOSB</code>}}
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 11
|-
! 12
| rsrcs || Fast short {{nowrap|<code>REP CMPSB</code>}} and {{nowrap|<code>REP SCASB</code>}}
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 12
|-
! 13
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| utmr || User-timer events: IA32_UINTR_TIMER (<code>1B00h</code>) MSR
! 13
|-
! 14
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| prefetchi || Instruction-cache prefetch instructions (<code>PREFETCHIT0</code> and <code>PREFETCHIT1</code>){{efn|1=On AMD processors, support for the instruction-cache prefetch instructions is not indicated by {{nowrap|1=<code>CPUID.(EAX=7,ECX=1):EDX[14]</code>}} but instead by {{nowrap|1=<code>CPUID.(EAX=8000_0021h):EAX[20]</code>.}}}}
! 14
|-
! 15
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| user_msr || User-mode MSR access instructions (<code>URDMSR</code> and <code>UWRMSR</code>)
! 15
|-
! 16
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 16
|-
! 17
| fred || Flexible Return and Event Delivery<ref name="intel_fred_spec">Intel, [https://cdrdv2-public.intel.com/795033/346446-flexible-return-and-event-delivery.pdf Flexible Return and Event Delivery (FRED) Specification], rev 6.1, December 2023, order no. 346446-007, page 14. [https://web.archive.org/web/20231222195250/https://cdrdv2-public.intel.com/795033/346446-flexible-return-and-event-delivery.pdf Archived] on Dec 22, 2023.</ref>
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| uiret-uif-from-rflags || If 1, the <code>UIRET</code> (User Interrupt Return) instruction will set UIF (User Interrupt Flag) to the value of bit 1 of the RFLAGS image popped off the stack.
! 17
|-
! 18
| lkgs || <code>LKGS</code> Instruction<ref name="intel_fred_spec"/>
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| cet-sss || If 1, then Control-Flow Enforcement (CET) Supervisor Shadow Stacks (SSS) are guaranteed not to become prematurely busy as long as shadow stack switching does not cause page faults on the stack being switched to.<ref>Intel, [https://kib.kiev.ua/x86docs/Intel/SDMs/325462-080.pdf Software Developer's Manual], order no. 325462-080, June 2023 - information about prematurely busy shadow stacks provided in Volume 1, section 17.2.3 on page 410; Volume 2A, table 3.8 (CPUID EAX=7,ECX=2) on page 820; Volume 3C, table 25-14 on page 3958 and section 26.4.3 on page 3984.</ref><ref>Intel, [https://cdrdv2-public.intel.com/785687/356628-complex-shadow-stack-updates-2.pdf Complex Shadow-Stack Updates (Intel Control-Flow Enforcement Technology)], order no. 356628-001, August 2023. [https://web.archive.org/web/20240402080946/https://cdrdv2-public.intel.com/785687/356628-complex-shadow-stack-updates-2.pdf Archived] on 2 Apr 2024.</ref><ref>LKML, [https://lkml.org/lkml/2023/6/16/1194 Re: (PATCH v3 00/21) Enable CET Virtualization], Jun 16, 2023 - provides additional discussion of how the CET-SSS prematurely-busy stack issue interacts with virtualization. [https://web.archive.org/web/20230807130831/https://lkml.org/lkml/2023/6/16/1194 Archived] on 7 Aug 2023.</ref>
! 18
|-
! 19
| wrmsrns || <code>WRMSRNS</code> instruction (non-serializing write to [[Model-specific register|MSR]]s)
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| avx10 || AVX10 Converged Vector ISA (see also leaf 24h)<ref name="intel_avx10_1">Intel, [https://cdrdv2-public.intel.com/784267/355989-intel-avx10-spec.pdf Advanced Vector Extensions 10], rev 1.0, July 2023, order no. 355989-001. [https://web.archive.org/web/20230724201235/https://cdrdv2-public.intel.com/784267/355989-intel-avx10-spec.pdf Archived] on Jul 24, 2023.</ref>
! 19
|-
! 20
| nmi_src || [[Non-maskable interrupt|NMI]] source reporting<ref name="intel_fred_spec"/>
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 20
|-
! 21
| amx-fp16 || AMX instructions for [[Half-precision floating-point format|FP16]] numbers
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| APX_F || [[X86#APX (Advanced Performance Extensions)|Advanced Performance Extensions]], Foundation (adds REX2 and extended [[EVEX prefix]] encodings to support 32 GPRs, as well as some new instructions)<ref name="intel_apx20">Intel, [https://cdrdv2-public.intel.com/786223/355828-intel-apx-spec.pdf Advanced Performance Extensions - Architecture Specification], rev 2.0, Aug 2023, order no. 355828-002, page 37. [https://web.archive.org/web/20230910083914/https://cdrdv2-public.intel.com/786223/355828-intel-apx-spec.pdf Archived] on Sep 10, 2023.</ref>
! 21
|-
! 22
| hreset || <code>HRESET</code> instruction, IA32_HRESET_ENABLE (<code>17DAh</code>) MSR, and Processor History Reset Leaf (EAX=20h)
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| SEC_TEE_&shy;ATTESTATION || If 1, then [[Trusted execution environment|trusted execution environment]] technologies ([[Trust Domain Extensions|Intel TDX]] and [[Software Guard Extensions|Intel SGX]]) support attestation rooted in the on-chip Security Engine.
! 22
|-
! 23
| avx-ifma || AVX IFMA instructions
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| mwait || MWAIT instruction{{efn|1=Support for the <code>MWAIT</code> instruction may be indicated by either {{nowrap|1=CPUID.(EAX=1).ECX[3]}} or {{nowrap|1=CPUID.(EAX=7,ECX=1).EDX[23].}} (One or both may be set.) The former indicates support for the <code>MONITOR</code> instruction as well, while the latter does not indicate one way or another whether the <code>MONITOR</code> instruction is present. <code>MWAIT</code> without <code>MONITOR</code> may be present in systems that support the "Monitorless MWAIT" feature (which is itself indicated by {{nowrap|1=CPUID.(EAX=5).ECX[3]}}.)}} 
! 23
|-
! 24
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| slsm || Static Lockstep Mode (bit 0 of <code>IA32_INTEGRITY_STATUS</code> MSR is available)
! 24
|-
! 25
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 25
|-
! 26
| lam || Linear Address Masking
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 26
|-
! 27
| msrlist || <code>RDMSRLIST</code> and <code>WRMSRLIST</code> instructions, and the IA32_BARRIER (<code>02Fh</code>) MSR
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 27
|-
! 28
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 28
|-
! 29
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 29
|-
! 30
| invd_&shy;disable_&shy;post_&shy;bios_done || If 1, supports <code>INVD</code> instruction execution prevention after BIOS Done.
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 30
|-
! 31
| MOVRS || <code>MOVRS</code> and <code>PREFETCHRST2</code> instructions supported (memory read/prefetch with read-shared hint)
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 31
|}
{{notelist}}
{{vpad}}

== EAX=7, ECX=2: Extended Features ==
This returns extended feature flags in EDX.

EAX, EBX and ECX are reserved.
{| class="wikitable"
|+ CPUID EAX=7,ECX=2: Extended feature bits in EDX
! rowspan="2" | Bit
! colspan="2" | EDX
|-
! Short || Feature
|-
! 0
| psfd || Fast Store Forwarding Predictor<ref>Intel, [https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/fast-store-forwarding-predictor.html Fast Store Forwarding Predictor], 8 Feb 2022. [https://web.archive.org/web/20240406120655/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/fast-store-forwarding-predictor.html Archived] on 6 Apr 2024.</ref> disable supported. (<code>SPEC_CTRL</code> (MSR <code>48h</code>) bit 7)
|-
! 1
| ipred_ctrl || IPRED_DIS controls<ref name="intel_bhi" /> supported. (<code>SPEC_CTRL</code> bits 3 and 4)

IPRED_DIS prevents instructions at an indirect branch target from speculatively executing until the branch target address is resolved.
|-
! 2
| rrsba_ctrl || RRSBA behavior<ref>Intel, [https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/return-stack-buffer-underflow.html Return Stack Buffer Underflow / CVE-2022-29901, CVE-2022-28693 / INTEL-SA-00702], 12 Jul 2022. [https://web.archive.org/web/20240703175513/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/return-stack-buffer-underflow.html Archived] on 3 Jul 2024.</ref><ref name="intel_bhi"/> disable supported. (<code>SPEC_CTRL</code> bits 5 and 6)
|-
! 3
| ddpd_u || Data Dependent Prefetcher<ref>Intel, [https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/data-dependent-prefetcher.html Data Dependent Prefetcher], 10 Nov 2022. [https://web.archive.org/web/20240804163643/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/data-dependent-prefetcher.html Archived] on 4 Aug 2024.</ref>  disable supported. (<code>SPEC_CTRL</code> bit 8)
|-
! 4
| bhi_ctrl || BHI_DIS_S behavior<ref name="intel_bhi">Intel, [https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598], 4 Aug 2022. [https://web.archive.org/web/20240211174839/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html Archived] on 11 Feb 2024.</ref> enable supported. (<code>SPEC_CTRL</code> bit 10)

BHI_DIS_S prevents predicted targets of indirect branches executed in ring0/1/2 from being selected based on branch history from branches executed in ring 3.
|-
! 5
| mcdt_no || If set, the processor does not exhibit [[Streaming SIMD Extensions|MXCSR]] configuration dependent timing.
|-
! 6
| UC_LOCK_&shy;DISABLE || UC-lock disable feature (with UC-lock exceptions reported as #AC) supported.
|-
! 7
| monitor_&shy;mitg_no || If set, indicates that the <code>MONITOR</code>/<code>UMONITOR</code> instructions are not affected by performance/power issues caused by the instructions exceeding the capacity of an internal monitor tracking table.<ref>Intel, [https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/monitor-umonitor-performance-guidance.html MONITOR and UMONITOR Performance Guidance], 10 Jul 2024. [https://web.archive.org/web/20241127041155/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/monitor-umonitor-performance-guidance.html Archived] on 27 Nov 2024.</ref>
|-
! <br/>31:8<br/>&nbsp;
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
|}

{{vpad}}

== EAX=0Dh: XSAVE Features and State Components ==

This leaf is used to enumerate XSAVE features and state components.

The XSAVE instruction set extension is designed to save/restore CPU extended state (typically for the purpose of [[Context switch|context switch]]ing) in a manner that can be extended to cover new instruction set extensions without the OS context-switching code needing to understand the specifics of the new extensions. This is done by defining a series of ''state-components'', each with a size and offset within a given save area, and each corresponding to a subset of the state needed for one CPU extension or another. The <code>EAX=0Dh</code> CPUID leaf is used to provide information about which state-components the CPU supports and what their sizes/offsets are, so that the OS can reserve the proper amount of space and set the associated enable-bits.

The state-components can be subdivided into two groups: user-state (state-items that are visible to the application, e.g. [[AVX-512]] vector registers), and supervisor-state (state items that affect the application but are not directly user-visible, e.g. user-mode interrupt configuration). The user-state items are enabled by setting their associated bits in the <code>XCR0</code> control register, while the supervisor-state items are enabled by setting their associated bits in the <code>IA32_XSS</code> (<code>0DA0h</code>) MSR - the indicated state items then become the state-components that can be saved and restored with the <code>XSAVE</code>/<code>XRSTOR</code> family of instructions.
{{vpad}}
The XSAVE mechanism can handle up to 63 state-components in this manner. State-components 0 and 1 ([[X87|x87]] and [[Streaming SIMD Extensions|SSE]], respectively) have fixed offsets and sizes — for state-components 2 to 62, their sizes, offsets and a few additional flags can be queried by executing <code>CPUID</code> with <code>EAX=0Dh</code> and <code>ECX</code> set to the index of the state-component. This will return the following items in EAX, EBX and ECX (with EDX being reserved):
{| class="wikitable"
|+ CPUID EAX=0Dh, ECX≥2: XSAVE state-component information
! Bit || EAX || EBX || ECX || Bit
|-
! 0
| rowspan="4" | Size (in bytes) of state-component
| rowspan="4" | Offset (in bytes) of state-component from the start of the <code>XSAVE</code>/<code>XRSTOR</code> save area

(This offset is 0 for supervisor state-components, since these can only be saved/restored with the <code>XSAVES</code>/<code>XRSTORS</code> instructions, which always use compacting.)
| User/supervisor state-component:
* 0=user-state (enabled through <code>XCR0</code>)
* 1=supervisor-state (enabled through <code>IA32_XSS</code>)
! 0
|-
! 1
| 64-byte alignment enable when state save compaction is used.

If this bit is set for a state-component, then, when storing state with compaction, padding will be inserted between the preceding state-component and this state-component as needed to provide 64-byte alignment. If this bit is not set, the state-component will be stored directly after the preceding one.
! 1
|-
! 2
| XFD Faulting supported for state-component.
! 2
|-
! <br/>31:3<br/>&nbsp;
| style="text-align:center; background:lightgrey;"| ''(reserved)''
! <br/>31:3<br/> 
|}

Attempting to query an unsupported state-component in this manner results in EAX,EBX,ECX and EDX all being set to 0.

Sub-leaves 0 and 1 of <code>CPUID</code> leaf <code>0Dh</code> are used to provide feature information:
{| class="wikitable"
|+ CPUID EAX=0Dh,ECX=0: XSAVE features
! EBX || ECX || EDX:EAX
|-
| Maximum size (in bytes) of XSAVE save area for the set of state-components currently set in <code>XCR0</code>.
| Maximum size (in bytes) of XSAVE save area if all state-components supported by <code>XCR0</code> on this CPU were enabled at the same time.
| 64-bit bitmap of state-components supported by <code>XCR0</code> on this CPU.
|}
{{vpad}}
{| class="wikitable"
|+ CPUID EAX=0Dh,ECX=1: XSAVE extended features
! EAX || EBX || EDX:ECX
|-
| XSAVE feature flags (see below table)
| Size (in bytes) of XSAVE area containing all the state-components currently set in <code>XCR0</code> and <code>IA32_XSS</code> combined.
| 64-bit bitmap of state-components supported by <code>IA32_XSS</code> on this CPU.
|}
{{vpad}}
{| class="wikitable"
|+ CPUID EAX=0Dh,ECX=1: XSAVE feature flags in EAX
!rowspan=2| Bit ||colspan=2| EAX 
|-
! Short || Feature
|-
! 0
| xsaveopt || <code>XSAVEOPT</code> instruction: save state-components that have been modified since last <code>XRSTOR</code>
|-
! 1
| xsavec || <code>XSAVEC</code> instruction: save/restore state with compaction
|-
! 2
| xgetbv_ecx1 || <code>XGETBV</code> with <code>ECX=1</code> support
|-
! 3
| xss || <code>XSAVES</code> and <code>XRSTORS</code> instructions and <code>IA32_XSS</code> MSR: save/restore state with compaction, including supervisor state.
|-
! 4
| xfd || XFD (Extended Feature Disable) supported
|-
! <br/>31:5<br/>&nbsp;
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
|}

{{vpad}}
As of July 2023, the XSAVE state-components that have been architecturally defined are:
{| class="wikitable"
|+ XSAVE State-components
! Index || Description || Enabled with
|-
! 0
| [[X87|x87]] state || {{yes|XCR0{{efn|Bit 0 of <code>XCR0</code> is hardwired to 1, so that the XSAVE instructions will always support save/restore of x87 state.}}}}
|-
! 1
| [[Streaming SIMD Extensions|SSE]] state: <code>XMM0</code>-<code>XMM15</code> and <code>MXCSR</code> || rowspan=7 {{yes|XCR0}}
|-
! 2
| [[Advanced Vector Extensions|AVX]] state: top halves of <code>YMM0</code> to <code>YMM15</code>
|-
! 3
| [[Intel MPX|MPX]] state: <code>BND0</code>-<code>BND3</code> bounds registers
|-
! 4
| MPX state: <code>BNDCFGU</code> and <code>BNDSTATUS</code> registers
|-
! 5
| [[AVX-512]] state: opmask registers <code>k0</code>-<code>k7</code>
|-
! 6
| AVX-512 "ZMM_Hi256" state: top halves of <code>ZMM0</code> to <code>ZMM15</code>
|-
! 7
| AVX-512 "Hi16_ZMM" state: <code>ZMM16</code>-<code>ZMM31</code>
|-
! 8
| Processor Trace state || {{no|IA32_XSS}}
|-
! 9
| PKRU (User Protection Keys) register || {{yes|XCR0}}
|-
! 10
| PASID (Process Address Space ID) state || rowspan="7" {{no|IA32_XSS}}
|-
! 11
| CET_U state (Control-flow Enforcement Technology: user-mode functionality MSRs)
|-
! 12
| CET_S state (CET: [[Shadow stack|shadow stack]] pointers for rings 0,1,2)
|-
! 13
| HDC (Hardware Duty Cycling) state
|-
! 14
| UINTR (User-Mode Interrupts) state
|-
! 15
| LBR (Last Branch Record) state
|-
! 16
| HWP (Hardware P-state control) state
|-
! 17
| [[Advanced Matrix Extensions|AMX]] tile configuration state: <code>TILECFG</code> || rowspan="3" {{yes|XCR0}}
|-
! 18
| AMX tile data registers: <code>tmm0</code>-<code>tmm7</code>
|-
! 19
| [[X86#APX (Advanced Performance Extensions)|APX]] extended general-purpose registers: <code>r16</code>-<code>r31</code><ref name="intel_apx20"/>
|-
! <br/>20 to 61<br/>&nbsp;
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
|-
! 62
| Lightweight Profiling (LWP) (AMD only) || {{yes|XCR0}}
|-
! 63
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''{{efn|For the <code>XCR0</code> and <code>IA32_XSS</code> registers, bit 63 is reserved specifically for bit vector expansion - this precludes the existence of a state-component 63.}}
|}
{{notelist}}
{{vpad}}

== EAX=12h: SGX Capabilities ==
This leaf provides information about the supported capabilities of the Intel [[Software Guard Extensions]] (SGX) feature. The leaf provides multiple sub-leaves, selected with ECX.

Sub-leaf 0 provides information about supported SGX leaf functions in EAX and maximum supported SGX enclave sizes in EDX; ECX is reserved. EBX provides a bitmap of bits that can be set in the MISCSELECT field in the SECS (SGX Enclave Control Structure) - this field is used to control information written to the MISC region of the SSA (SGX Save State Area) when an AEX (SGX Asynchronous Enclave Exit) occurs.
{| class="wikitable"
|+ CPUID EAX=12h,ECX=0: [[Software Guard Extensions|SGX]] leaf functions, MISCSELECT and maximum-sizes
! rowspan=2 | Bit
! colspan=2 | EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="19" |
! colspan=2 | EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="19" |
! colspan=2 | EDX
! rowspan=2 | Bit
|-
! Short || Feature
! Short || Feature
! Short || Feature
|-
! 0
| sgx1 || SGX1 leaf functions
| EXINFO || MISCSELECT: report information about page fault and general protection exception that occurred inside enclave
| rowspan=8 | MaxEnclave&shy;Size_Not64|| rowspan=8 | Log2 of maximum enclave size supported in non-64-bit mode
! 0
|-
! 1
| sgx2 || SGX2 leaf functions
| CPINFO || MISCSELECT: report information about control protection exception that occurred inside enclave
! 1
|-
! 2
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 2
|-
! 3
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 3
|-
! 4
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 4
|-
! 5
| OSS{{efn|name=sgx_oversub|text=The SGX Oversubscription Extensions bits (CPUID.(EAX=12h,ECX=0):EAX[bits 5 and 6]) are listed in revisions 065 to 087 of the Intel SDM, but were removed from revision 088 onwards. These bits are known to have been set in at least some [[Engineering:Ice Lake (microprocessor)|IceLake-U]] processors.<ref>InstLatx64, [http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00706E5_IceLakeY_CPUID.txt Intel Core i7-1065G7 CPUID dump] — has the SGX oversubscription feature bits set ([[CPUID#EAX=12h: SGX Capabilities|CPUID.(EAX=12h,ECX=0)]].EAX[6:5]). [https://web.archive.org/web/20191206041304/http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00706E5_IceLakeY_CPUID.txt Archived] on 6 Dec 2019.</ref>}} || <code>ENCLV</code> leaves: <code>EINCVIRTCHILD</code>, <code>EDECVIRTCHILD</code>, and <code>ESETCONTEXT</code>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 5
|-
! 6
| ENCLS_C{{efn|name=sgx_oversub}}<ref>[https://www.linux-kvm.org/images/e/e8/KVM_Forum_2018_-_Intel_SGX.pdf Intel SGX Virtualization], KVM Forum 2018, p.19. [https://web.archive.org/web/20191117015943/https://www.linux-kvm.org/images/e/e8/KVM_Forum_2018_-_Intel_SGX.pdf Archived] on 17 Nov 2019.</ref> || <code>ENCLS</code> leaves: <code>ETRACKC</code>, <code>ERDINFO</code>, <code>ELDBC</code>, <code>ELDUC</code>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 6
|-
! 7
| EVERIFY&shy;REPORT2|| <code>ENCLU</code> leaf: <code>EVERIFYREPORT2</code>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 7
|-
! 8
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| rowspan=8 | MaxEnclave&shy;Size_64 || rowspan=8 | Log2 of maximum enclave size supported in 64-bit mode
! 8
|-
! 9
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 9
|-
! 10
| EUPDATESVN || <code>ENCLS</code> leaf: <code>EUPDATESVN</code>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 10
|-
! 11
| EDECCSSA || <code>ENCLU</code> leaf: <code>EDECCSSA</code>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 11
|-
! 12
| 256BITSGX || <code>ENCLU</code> leaf functions <code>EGETKEY256</code> and <code>EREPORT2</code>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 12
|-
! 13
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 13
|-
! 14
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 14
|-
! 15
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 15
|-
! <br/>31:16<br/>&nbsp;
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! <br/>31:16<br/>&nbsp;
|}
{{notelist}}
{{vpad}}
Sub-leaf 1 provides a bitmap of which bits can be set in the 128-bit ATTRIBUTES field of SECS in EDX:ECX:EBX:EAX (this applies to the SECS copy used as input to the <code>ENCLS[ECREATE]</code> leaf function). The top 64 bits (given in EDX:ECX) are a bitmap of which bits can be set in the XFRM (X-feature request mask) - this mask is a bitmask of which CPU state-components (see leaf 0Dh) will be saved to the SSA in case of an AEX; this has the same layout as the <code>XCR0</code> control register. The other bits are given in EAX and EBX, as follows:
{| class="wikitable"
|+ CPUID EAX=12h,ECX=1: [[Software Guard Extensions|SGX]] settable bits in SECS.ATTRIBUTES
! rowspan=2 | Bit
! colspan=2 | EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="14" |
! colspan=2 | EBX
! rowspan=2 | Bit
|-
! Short || Feature
! Short || Feature
|-
! 0
| style="background:lightgrey" | (INIT) || style="text-align:center; background:lightgrey;" | ''(must be 0)''{{efn|text=For the copy of the SECS that exists inside an exclave, bit 0 (INIT) of SECS.ATTRIBUTES is used to indicate that the enclave has been initialized with <code>ENCLS[EINIT]</code>. This bit must be 0 in the SECS copy that is given as input to <code>ENCLS[CREATE]</code>.}}
| rowspan=12 colspan=2 style="text-align:center; background:lightgrey;"| ''(reserved)''
! 0
|-
! 1
| DEBUG || Permit debugger to read and write enclave data using <code>EDBGRD</code> and <code>EDBGWR</code>
! 1
|-
! 2
| MODE64BIT || 64-bit-mode enclave
! 2
|-
! 3
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 3
|-
! 4
| PROVISIONKEY || Provisioning key available from <code>EGETKEY</code>
! 4
|-
! 5
| EINITTOKEN_KEY || <code>EINIT</code> token key available from <code>EGETKEY</code>
! 5
|-
! 6
| CET || CET (Control-Flow Enforcement Technology) attributes enable
! 6
|-
! 7
| KSS || Key Separation and Sharing
! 7
|-
! 8
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 8
|-
! 9
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 9
|-
! 10
| AEXNOTIFY || Threads inside enclave may receive AEX notifications<ref>Intel, [https://cdrdv2-public.intel.com/736463/aex-notify-white-paper-public.pdf Asynchronous Enclave Exit Notify and the EDECCSSA User Leaf Function], 30 Jun 2022. [https://web.archive.org/web/20221121073302/https://cdrdv2-public.intel.com/736463/aex-notify-white-paper-public.pdf Archived] on 21 Nov 2022.</ref> 
! 10
|-
! <br/>31:11<br/>&nbsp;
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! <br/>31:11<br/>&nbsp;
|}
{{notelist}}
{{vpad}}
Sub-leaves 2 and up are used to provide information about which physical memory regions are available for use as EPC (Enclave Page Cache) sections under SGX.
{| class="wikitable"
|+ CPUID EAX=12h,ECX≥2: [[Software Guard Extensions|SGX]] Enclave Page Cache section information
|-
! Bits
! EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5" |
! EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5" |
! ECX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5" |
! EDX
! Bits
|-
! 3:0
| Sub-leaf type:
* 0000: Invalid
* 0001: EPC section
* other: reserved
| rowspan=3 | Bits 51:32 of physical base address of EPC section
| EPC Section properties:
* 0000: Invalid
* 0001: Has confidentiality, integrity, and replay protection
* 0010: Has confidentiality protection only
* 0011: Has confidentiality and integrity protection
* other: reserved
| rowspan=3 | Bits 51:32 of size of EPC section
! 3:0
|-
! <br/>11:4<br/>&nbsp;
| style="text-align:center; background:lightgrey;"| ''(reserved)''
| style="text-align:center; background:lightgrey;"| ''(reserved)''
! <br/>11:4<br/>&nbsp;
|-
! <br/>19:12<br/>&nbsp;
| rowspan=2 | Bits 31:12 of physical base address of EPC section
| rowspan=2 | Bits 31:12 of size of EPC section
! <br/>19:12<br/>&nbsp;
|-
! <br/>31:20<br/>&nbsp;
| style="text-align:center; background:lightgrey;"| ''(reserved)''
| style="text-align:center; background:lightgrey;"| ''(reserved)''
! <br/>31:20<br/>&nbsp;
|}
{{vpad}}

== EAX=14h: Processor Trace ==
This leaf provides feature information for Intel [[Branch trace|Processor Trace]] (also known as Real Time Instruction Trace).

For sub-leaf 0, the value returned in EAX is the index of the highest sub-leaf supported for CPUID with EAX=14h. EBX and ECX provide feature flags, EDX is reserved.
<!-- Intel SDM, vol 3, section 33.3.1-->
{| class="wikitable"
|+ CPUID EAX=14h,ECX=0: Processor Trace feature bits in EBX and ECX
! rowspan=2 | Bit 
! colspan=2 | EBX
! rowspan=14 |
! colspan=2 | ECX
! rowspan=2 | Bit
|-
! Short || Feature
! Short || Feature
|-
! 0
| cr3_filter || [[Control register#CR3|CR3]] filtering supported
| topaout || ToPA (Table of Physical Addresses) output mechanism for trace packets supported
! 0
|-
! 1
| cyc_acc || Configurable PSB (Packet Stream Boundary) packet rate and Cycle-Accurate Mode (CYC packets) supported
| mentry || ToPA tables can contain hold multiple output entries
! 1
|-
! 2
| ip_filter || IP filtering, TraceStop filtering and preservation of PT MSRs across warm reset supported
| sngl_&shy;rng_out || Single-Range Output scheme supported
! 2
|-
! 3
| mtc || MTC (Mini Time Counter) timing packets supported, and suppression of COFI (Change of Flow Instructions) packets supported.
| trace_&shy;transport_&shy;subsystem || Output to Trace Transport subsystem supported
! 3
|-
! 4
| ptwrite || <code>PTWRITE</code> instruction supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 4
|-
! 5
| pwr_evt_&shy;trace || Power Event Trace supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 5
|-
! 6
| pmi_preserve || Preservation of PSB and PMI (performance monitoring interrupt) supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 6
|-
! 7
| event_trace || Event Trace packet generation supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 7
|-
! 8
| tnt_dis || TNT (Branch Taken-Not-Taken) packet generation disable supported.
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 8
|-
! 9
| PTTT || PTTT (Processor Trace Trigger Tracing) supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 9
|-
! <br/>30:10<br/>&nbsp;
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! <br/>30:10<br/>&nbsp;
|-
! 31
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| lip
| IP (Instruction Pointer) format for trace packets that contain IP payloads:
* 0=RIP (effective-address IP)
* 1=LIP (linear-address IP, with CS base address added)
! 31
|}
{{vpad}}

{| class="wikitable"
|+ CPUID EAX=14h,ECX=1: Processor Trace packet generation information in EAX, EBX and ECX
! rowspan=2 | Bit 
! colspan=2 | EAX
! rowspan=10 |
! colspan=2 | EBX
! rowspan=10 |
! colspan=2 | ECX
! rowspan=2 | Bit
|-
! Short || Feature
! Short || Feature
! Short || Feature
|-
! 0
| rowspan=3 | rangecnt || rowspan=3 | Number of configurable address ranges for filtering
| rowspan=7 | cyc_thresholds || rowspan=7 | Bitmap of supported cycle threshold value encodings
| ICNT || Trigger Action EN_ICNT supported
! 0
|-
! 1
| TRIGGER_&shy;PAUSE || Trigger actions TRACE_PAUSE and TRACE_RESUME supported
! 1
|-
! 2
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 2
|-
! 7:3
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 7:3
|-
! 10:8
| TRIGGER_&shy;CFG_CNT || Number of IA32_RTIT_TRIGGERx_CFG MSRs.
(Number of triggers supported is 4x this value)
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 10:8
|-
! 14:11
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 14:11
|-
! 15
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| TRIGGER_&shy;DR_MATCH || Trigger input DR match supported
! 15
|-
! 31:16
| mtc_rate || Bitmap of supported MTC period encodings
| psb_rate || Bitmap of supported Configurable PSB frequency encodings
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 31:16
|}
{{vpad}}

== EAX=15h and EAX=16h: CPU, TSC, Bus and Core Crystal Clock Frequencies ==

These two leaves provide information about various frequencies in the CPU in EAX, EBX and ECX (EDX is reserved in both leaves).
{| class="wikitable"
|+ CPUID EAX=15h: TSC and Core [[Engineering:Crystal oscillator|Crystal]] frequency information
! EAX !! EBX !! ECX
|-
| Ratio of TSC frequency to Core Crystal Clock frequency, denominator
| Ratio of TSC frequency to Core Crystal Clock frequency, numerator{{efn|name=unsupp_1516|Field not enumerated if zero.}}
| Core Crystal Clock frequency, in units of [[Hertz|Hz]]{{efn|name=unsupp_1516}}
|}
{| class="wikitable"
|+ CPUID EAX=16h: Processor and Bus specification frequencies{{efn|The frequency values reported by leaf 16h are the processor's specification frequencies - they are constant for the given processor and do not necessarily reflect the actual CPU clock speed at the time CPUID is called.}}
! Bits !! EAX !! EBX !! ECX !! Bits
|-
! 15:0
| Processor Base Frequency (in MHz){{efn|name=unsupp_1516}}
| Processor Maximum Frequency (in MHz){{efn|name=unsupp_1516}}
| Bus/Reference frequency (in MHz){{efn|name=unsupp_1516}}
! 15:0
|-
! 31:16
| style="text-align:center; background:lightgrey;" | ''(reserved)''
| style="text-align:center; background:lightgrey;" | ''(reserved)''
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 31:16
|}
{{notelist}}
{{vpad}}
If the returned values in EBX and ECX of leaf 15h are both nonzero, then the TSC ([[Time Stamp Counter]]) frequency in Hz is given by <code>TSCFreq = ECX*(EBX/EAX)</code>.

On some processors (e.g. Intel [[Skylake (microarchitecture)|Skylake]]), CPUID_15h_ECX is zero but CPUID_16h_EAX is present and not zero. On all known processors where this is the case,<ref>Linux kernel git commit 604dc91, [https://github.com/torvalds/linux/commit/604dc9170f2435d27da5039a3efd757dceadc684 x86/tsc: Use CPUID.0x16 to calculate missing crystal frequency], 9 May 2019 - contains notes on computing the Core Crystal Clock frequency on CPUs that don't specify it, and corresponding C code.</ref> the TSC frequency is equal to the Processor Base Frequency, and the Core Crystal Clock Frequency in Hz can be computed as <code>CoreCrystalFreq = (CPUID_16h_EAX * 10000000) * (CPUID_15h_EAX/CPUID_15h_EBX)</code>.

On processors that enumerate the TSC/Core Crystal Clock ratio in CPUID leaf 15h, the [[Advanced Programmable Interrupt Controller|APIC]] timer frequency will be the Core Crystal Clock frequency divided by the divisor specified by the APIC's Divide Configuration Register.<ref>Intel, [https://kib.kiev.ua/x86docs/Intel/SDMs/253668-083.pdf SDM Volume 3A], order no 253668-083, March 2024, chapter 11.5.4, page 408</ref>
{{vpad}}

== EAX=17h: SoC Vendor Attribute Enumeration ==
This leaf is present in systems where an x86 CPU [[Engineering:Semiconductor intellectual property core|IP core]] is implemented in an SoC (System on chip) from another vendor - whereas the other leaves of <code>CPUID</code> provide information about the x86 CPU core, this leaf provides information about the SoC. This leaf takes a sub-leaf index in ECX.

Sub-leaf 0 returns a maximum sub-leaf index in EAX (at least 3), and SoC identification information in EBX/ECX/EDX:
{| class="wikitable"
|+ CPUID EAX=17h,ECX=0: SoC identification information
! Bit
! EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4" |
! ECX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4" |
! EDX
! Bit
|-
! 15:0
| SoC Vendor ID
| rowspan=3 | SoC Project ID
| rowspan=3 | SoC Stepping ID within an SoC project
! 15:0
|-
! 16
| SoC Vendor ID scheme
* 0 : Vendor IDs assigned by Intel{{efn|text=As of May 2024, the following Vendor IDs are known to have been assigned by Intel:
{{(!}} class="wikitable sortable"
! ID !! Vendor
{{!}}-
{{!}} 1 {{!!}} [[Company:Spreadtrum|Spreadtrum]]<ref>instlatx64, [http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel007065A_Spreadtrum_CPUID.txt Spreadtrum SC9853I-IA CPUID dump]</ref>
{{!)}}}}
* 1 : Industry standard enumeration scheme{{efn|text=As of May 2024, Intel documentation does not specify which "Industry Standard" enumeration scheme to use for the Vendor ID in EBX[15:0] if EBX[16] is set.<!--possible candidates include e.g. PCI Vendor-ID or USB Vendor-ID, both of which are 16-bit - but neither appears to be verifiable-->}}
! 16
|-
! 31:17
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 31:17
|}
{{notelist}}
{{vpad}}
Sub-leaves 1 to 3 return a 48-byte SoC vendor brand string in [[UTF-8]] format. Sub-leaf 1 returns the first 16 bytes in EAX,EBX,ECX,EDX (in that order); sub-leaf 2 returns the next 16 bytes and sub-leaf 3 returns the last 16 bytes. The string is allowed but not required to be [[Null-terminated string|null-terminated]].
{{vpad}}

== EAX=19h: Intel Key Locker Features ==

This leaf provides feature information for Intel Key Locker in EAX, EBX and ECX. EDX is reserved.
{| class="wikitable"
|+ CPUID EAX=19h: Key Locker feature bits in EAX, EBX and ECX
! rowspan=2 | Bit
! colspan=2 | EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="8" |
! colspan=2 | EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="8" |
! colspan=2 | ECX
! rowspan=2 | Bit
|-
! Short || Feature
! Short || Feature
! Short || Feature
|-
! 0
| cpl0_&shy;restrict || Key Locker restriction of CPL0-only supported
| aes_kle || [[Advanced Encryption Standard|AES]] "Key Locker" Instructions enabled
| nobackup || No-backup parameter to <code>LOADIWKEY</code> supported
! 0
|-
! 1
| no_encrypt_&shy;restrict|| Key Locker restriction of no-encrypt supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| rand_&shy;iwkey || KeySource encoding of 1 (randomization of internal wrapping key) supported
! 1
|-
! 2
| no_decrypt_&shy;restrict || Key Locker restriction of no-decrypt supported
| aes_wide_kl || [[Advanced Encryption Standard|AES]] "Wide Key Locker" Instructions supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 2
|-
! 3
| style="background:lightgrey;" | || style="background:lightgrey;" | (Process Restriction){{efn|text=As of April 2024, the "Process Restriction" bit is listed only in Intel [[Trust Domain Extensions|TDX]] documentation<ref name="intel_tdx_2020" /> and is not set in any known processor.}}
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 3
|-
! 4
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| iwkey&shy;backup || "Key Locker" MSRs and backup of internal wrapping key supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 4
|-
! <br/>31:5<br/>&nbsp;
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! <br/>31:5<br/>&nbsp;
|}
{{notelist}}
{{vpad}}

<!-- TODO: EAX=1Ah, ECX=0: Native Model ID Enumeration -->
<!-- TODO: EAX=1Bh: PCONFIG -->
<!-- TODO: EAX=1Ch: Last Branch Records -->

== EAX=1Dh: Intel AMX Tile Information ==
When <code>ECX=0</code>, the highest supported "palette" subleaf is enumerated in EAX. When <code>ECX≥1</code>, information on palette ''n'' is returned.

{| class="wikitable"
|+ CPUID EAX=1Dh,ECX≥1: AMX Tile Palette ''n'' Information
! rowspan="2" | Bits
! colspan="2" | EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4" |
! colspan="2" | EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4" |
! colspan="2" | ECX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="4" |
! colspan="2" | EDX
! rowspan="2" | Bits
|-
! Short !! Feature
! Short !! Feature
! Short !! Feature
! Short !! Feature
|-
! 15:0
| total_tile_bytes || Size of all tile registers, in bytes (8192)
| bytes_per_row || (64)
| max_rows || (16)
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 15:0
|-
! 31:16
| bytes_per_tile || Size of one tile, in bytes (1024)
| max_names || Number of tile registers (8)
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 31:16
|}
{{vpad}}

== EAX=1Eh: Intel AMX Tile Multiplier (<code>TMUL</code>) Information ==
This leaf returns information on the [[Advanced Matrix Extensions|AMX]] <code>TMUL</code> (tile multiplier) unit. The leaf provides multiple sub-leaves, selected with ECX.

Subleaf 0 returns maximum supported sub-leaf in EAX and basic TMUL information in EBX; subleaf 1 returns additional feature information in EAX.

{| class="wikitable"
|+ CPUID EAX=1Eh,ECX=0: AMX <code>TMUL</code> Information Main Leaf
! rowspan="2" | Bits
! colspan="2" | EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="6" |
! colspan="2" | ECX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="6" |
! colspan="2" | EDX
! rowspan="2" | Bits
|-
! Short !! Feature
! Short !! Feature
! Short !! Feature
|-
! 7:0
| tmul_maxk || Maximum number of rows or columns (16)
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 7:0
|-
! 23:8
| tmul_maxn || Maximum number of bytes per column (64)
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 23:8
|-
! 31:24
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 31:24
|}
{{vpad}}

{| class="wikitable"
|+ CPUID EAX=1Eh,ECX=1: AMX <code>TMUL</code> feature information
! rowspan="2" | Bits
! colspan="2" | EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="12" |
! colspan="2" | EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="12" |
! colspan="2" | ECX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="12" |
! colspan="2" | EDX
! rowspan="2" | Bits
|-
! Short !! Feature
! Short !! Feature
! Short !! Feature
! Short !! Feature
|-
! 0
| amx-int8 || 8-bit integer support
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 0
|-
! 1
| amx-bf16 || bfloat16 support
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 1
|-
! 2
| amx-complex || Complex number support
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 2
|-
! 3
| amx-fp16 || float16 support
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 3
|-
! 4
| amx-fp8 || float8 support
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 4
|-
! 5
| style="text-align:center; background:lightgrey;" | (amx-transpose){{efn|Previously listed as a future extension,<ref>{{Cite web |date=Jun 2025 |title=Intel® Architecture Instruction Set Extensions and Future Features |url=https://cdrdv2-public.intel.com/859029/319433-058-architecture-instruction-set-extensions-programming-reference.pdf |url-status=live |page=41 |archive-url=https://web.archive.org/web/20250717053237/https://cdrdv2-public.intel.com/859029/319433-058-architecture-instruction-set-extensions-programming-reference.pdf |archive-date=17 Jul 2025 |archive-format=PDF |access-date=30 Oct 2025 |edition=58th |id=319433-058}}</ref> but was removed in version 059.<ref>{{Cite web |date=2 Oct 2025 |title=Intel® Architecture Instruction Set Extensions and Future Features |url=https://cdrdv2-public.intel.com/865891/319433-059-architecture-instruction-set-extensions-programming-reference_2025-0930.pdf |url-status=live |page=41 |archive-url=https://web.archive.org/web/20251003163003/https://cdrdv2-public.intel.com/865891/319433-059-architecture-instruction-set-extensions-programming-reference_2025-0930.pdf |archive-date=3 Oct 2025 |archive-format=PDF |access-date=3 Oct 2025 |edition=59th |id=319433-059}}</ref>}}
| style="text-align:center; background:lightgrey;" | (Transposition instruction support)
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 5
|-
! 6
| amx-tf32 || tf32/fp19 support
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 6
|-
! 7
| amx-avx512 || AMX-AVX512 support
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 7
|-
! 8
| amx-movrs || AMX-MOVRS support
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 8
|-
! 31:9
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 31:9
|}
{{notelist}}
{{vpad}}

<!-- TODO: EAX=1Fh: V2 Extended Topology Enumeration -->
<!-- TODO: EAX=20h,ECX=0: Processor History Reset -->

== EAX=21h: Reserved for TDX enumeration ==
When Intel TDX ([[Trust Domain Extensions]]) is active, attempts to execute the <code>CPUID</code> instruction by a TD (Trust Domain) guest will be intercepted by the TDX module.
This module will, when <code>CPUID</code> is invoked with <code>EAX=21h</code> and <code>ECX=0</code> (leaf <code>21h</code>, sub-leaf 0), return the index of the highest supported sub-leaf for leaf <code>21h</code> in <code>EAX</code> and a TDX module vendor ID string as a 12-byte ASCII string in EBX,EDX,ECX (in that order). Intel's own module implementation returns the vendor ID string <code>"IntelTDX{{spaces|4}}"</code> (with four trailing spaces)<ref>Intel, [https://cdrdv2-public.intel.com/733568/tdx-module-1.0-public-spec-344425005.pdf Architecture Specification: Intel Trust Domain Extensions (Intel TDX) Module], order no. 344425-005, page 93, Feb 2023.<!-- CPUID leaf 21h information missing from some earlier revisions of 3444425--> [https://web.archive.org/web/20230720220842/https://cdrdv2-public.intel.com/733568/tdx-module-1.0-public-spec-344425005.pdf Archived] on 20 Jul 2023.</ref> - for this module, additional feature information is not available through <code>CPUID</code> and must instead be obtained through the TDX-specific <code>TDCALL</code> instruction.

This leaf is reserved in hardware and will (on processors whose highest basic leaf is <code>21h</code> or higher) return 0 in EAX/EBX/ECX/EDX when run directly on the CPU.
{{vpad}}

== EAX=24h, ECX=0: AVX10 Converged Vector ISA ==
This returns a maximum supported sub-leaf in EAX and AVX10 feature information in EBX.<ref name="intel_avx10_1"/> (ECX and EDX are reserved.)

{| class="wikitable"
|+ CPUID EAX=24h, ECX=0: AVX10 feature bits in EBX
! rowspan=2 | Bit
! colspan=2 | EBX
|-
! Short
! Feature
|-
! 7:0
| vector_&shy;isa_&shy;version || AVX10 Converged Vector ISA version (≥1)
|-
! 15:8
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
|-
! 18:16
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved as 111b)''{{efn|These three bits were originally designed to indicate the "supported vector width", with bit 16 indicating 128-bit vector support, bit 17 for 256-bit, and bit 18 for 512-bit. 128-bit maximum CPUs were said to have {{nowrap|"AVX10/128"}} support, 256-bit maximum to have {{nowrap|"AVX10/256"}} support, and 512-bit maximum to have {{nowrap|"AVX10/512"}} support; The number after the slash indicated the maximum supported vector width. Shortly after the announcement of AVX10.1, Intel dropped plans for {{nowrap|AVX10/128}},<ref>Intel, [https://cdrdv2-public.intel.com/828964/355989-intel-avx10.1-spec.pdf Intel Advanced Vector Extensions 10 Architecture Specification], order no. 355989-003US, July 2024, see revision history on page 13. [https://web.archive.org/web/20241008214903/https://cdrdv2-public.intel.com/828964/355989-intel-avx10.1-spec.pdf Archived] on 8 Oct 2024.</ref> likely after [https://chipsandcheese.com/p/avx10-128-is-a-silly-idea-and-should-be-completely-removed-from-the-specification pushback from developers], leaving only 256-bit and 512-bit maximum vector widths as supported. With AVX10.2, Intel dropped the vector width distinction entirely, instead mandating 512-bit vector support. As the only shipping AVX10.1 CPUs were based on [[Engineering:Granite Rapids|Granite Rapids]], a P-core-only design (and subsequently has had {{nowrap|AVX10/512}}), no {{nowrap|AVX10/256}} CPUs were ever shipped. In other words, the only shipped CPUs with AVX10 had 128-, 256-, and 512-bit support, putting all three bits as 111b. These bits are now documented as reserved, but reading 111b.}}
|-
! 31:19
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
|}
{{notelist}}
{{vpad}}

== EAX=24h, ECX=1: Discrete AVX10 Features ==
Subleaf 1 is reserved for AVX10 features not bound to a version.

{| class="wikitable"
|+ CPUID EAX=24h, ECX=1: Discrete AVX10 features in ECX
! rowspan=2 | Bit
! colspan=2 | ECX
|-
! Short
! Feature
|-
! 0
| (VPMM) || (Vector-Extension Packed Matrix Multiplication)<ref>Intel, [https://cdrdv2-public.intel.com/853286/intel-tdx-module-base-spec-348549006.pdf Trust Domain Extensions (Intel TDX) Module Base Architecture Specification], order no. 348549-006US, April 2025, p. 116. [https://web.archive.org/web/20250424190213/https://cdrdv2-public.intel.com/853286/intel-tdx-module-base-spec-348549006.pdf Archived] on 24 Apr 2025.</ref>
|-
! 1
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
|-
! 2
| AVX10_VNNI_INT || AVX10.2 VNNI instructions{{efn|1=The AVX10.2 VNNI instructions are present if either the AVX10 version is 2 or higher (see CPUID.(EAX=24h).EBX[7:0]) or the AVX10_VNNI_INT bit is set.}}<ref>Intel, [https://cdrdv2-public.intel.com/855340/361050-004-intel-avx10.2-spec.pdf Advanced Vector Extensions 10.2 Architecture Specification], revision 4.0, order no. 361050-004US, May 2025, p. 16. [https://web.archive.org/web/20250525115030/https://cdrdv2-public.intel.com/855340/361050-004-intel-avx10.2-spec.pdf Archived] on 25 May 2025.</ref>
|-
! 31:3
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
|}
{{notelist}}
{{vpad}}

== EAX=2000'0000h: Highest Xeon Phi Function Implemented ==

The highest function is returned in EAX.
This leaf is only present on [[Engineering:Xeon Phi|Xeon Phi]] processors<!-- which ones? -->.<ref name="intel_knc_cpuid_ref">Intel, [https://www.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf Intel Xeon Phi Coprocessor Instruction Set Architecture Reference Manual], Sep 2012, order no. 327364-001, appendix B.8, pages 677. [https://web.archive.org/web/20210804022347/https://software.intel.com/content/dam/develop/external/us/en/documents/327364001en.pdf Archived] on 4 Aug 2021.</ref>

== EAX=2000'0001h: Xeon Phi Feature Bits ==

This function returns feature flags.

{| class="wikitable"
|+ CPUID EAX=2000'0001h: Xeon Phi feature bits
! rowspan="2" | Bit
! colspan="2" | EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5" |
! colspan="2" | EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5" |
! colspan="2" | ECX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5" |
! colspan="2" | EDX
! rowspan="2" | Bit
|-
! Short
! Feature
! Short
! Feature
! Short
! Feature
! Short
! Feature
|-
! 3:0
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 3:0
|-
! 4
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| k1om || K1OM<ref name="intel_knc_cpuid_ref" />
! 4
|-
! 31:5
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 31:5
|-
|}

== EAX=4000'0000h-4FFFF'FFFh: Reserved for [[Hypervisor]]s ==
When the <code>CPUID</code> instruction is executed under [[X86 virtualization|Intel VT-x or AMD-v virtualization]], it will be intercepted by the hypervisor, enabling the hypervisor to return <code>CPUID</code> feature flags that differ from those of the underlying hardware. <code>CPUID</code> leaves <code>40000000h</code> to <code>4FFFFFFFh</code> are not implemented in hardware, and are reserved for use by hypervisors to provide hypervisor-specific identification and feature information through this interception mechanism.

For leaf <code>40000000h</code>, the hypervisor is expected to return the index of the highest supported hypervisor CPUID leaf in EAX, and a 12-character hypervisor ID string in EBX,ECX,EDX (in that order). For leaf <code>40000001h</code>, the hypervisor may return an interface identification signature in EAX - e.g. hypervisors that wish to advertise that they are [[Software:Hyper-V|Hyper-V]] compatible may return <code>0x31237648</code>—<code>"Hv#1"</code> in EAX.<ref name="microsoft_tlfs"/><ref>Geoff Chappell, [https://www.geoffchappell.com/studies/windows/km/ntoskrnl/inc/shared/hvgdk_mini/hv_hypervisor_interface.htm HV_HYPERVISOR_INTERFACE], 10 Dec 2022. [https://web.archive.org/web/20230201083111/https://www.geoffchappell.com/studies/windows/km/ntoskrnl/inc/shared/hvgdk_mini/hv_hypervisor_interface.htm Archived] on 1 Feb 2023.</ref> The formats of leaves <code>40000001h</code> and up to the highest supported leaf are otherwise hypervisor-specific. Hypervisors that implement these leaves will normally also set bit 31 of ECX for CPUID leaf 1 to indicate their presence.
{{vpad}}
Hypervisors that expose more than one hypervisor interface may provide additional sets of CPUID leaves for the additional interfaces, at a spacing of <code>100h</code> leaves per interface.<ref>David Woodhouse, [https://david.woodhou.se/ExtDestId.pdf Extended Destination ID: Supporting x86 virtual machines with many vCPUs], 20 Aug 2025, page 4. [https://web.archive.org/web/20250823221104/https://david.woodhou.se/ExtDestId.pdf Archived] on 23 Aug 2025.</ref> Examples of hypervisors that do this include:
* When [[Software:QEMU|QEMU]] is configured to provide both [[Software:Hyper-V|Hyper-V]] and [[Software:Kernel-based Virtual Machine|KVM]] interfaces, it will provide Hyper-V information starting from CPUID leaf <code>40000000h</code> and KVM information starting from leaf <code>40000100h</code>.<ref>QEMU documentation, [https://www.qemu.org/docs/master/system/i386/hyperv.html Hyper-V Enlightenments]. [https://web.archive.org/web/20240417230400/https://www.qemu.org/docs/master/system/i386/hyperv.html Archived] on 17 Apr 2024.</ref><ref>Linux 6.8.7 kernel source, [https://elixir.bootlin.com/linux/v6.8.7/source/arch/x86/kvm/cpuid.c /source/arch/x86/kvm/cpuid.c], lines 1482-1488</ref>
* When [[Software:Xen|Xen]] is configured to provide Hyper-V emulation, it will provide Hyper-V information starting from CPUID leaf <code>40000000h</code> and Xen information starting from leaf <code>40000100h</code>.<ref name="xen_cpuid" />
{{vpad}}
Some hypervisors that are known to return a hypervisor ID string in leaf <code>40000000h</code> include:
{| class="wikitable"
|+ CPUID EAX=4000'0000h: 12-character Hypervisor ID string in EBX,ECX,EDX
! Hypervisor
! ID String (ASCII)
! Notes
|-
| {{nowrap|Microsoft [[Software:Hyper-V|Hyper-V]]}}<!-- this page used to list Windows Virtual PC as returning "Microsoft Hv", however this appears to be false, as indicated by http://git.annexia.org/?p=virt-what.git;a=blob;f=virt-what.in;h=61481d352693e97e0f14f05d99d0f3d175f30d5e;hb=HEAD#l174 -->
| <code>"Microsoft Hv"</code><ref name="microsoft_tlfs">Microsoft, [https://learn.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/feature-discovery Hyper-V Feature and Interface Discovery], 8 Jul 2022. [https://web.archive.org/web/20231118222643/https://learn.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/feature-discovery Archived] on 18 Nov 2023.</ref>
|
|-
| rowspan="2" | Linux [[Software:Kernel-based Virtual Machine|KVM]]
| <code>"KVMKVMKVM\0\0\0"</code><ref>Linux kernel documentation, [https://docs.kernel.org/virt/kvm/x86/cpuid.html KVM CPUID bits]. [https://web.archive.org/web/20220822051320/https://docs.kernel.org/virt/kvm/x86/cpuid.html Archived] on 22 Aug 2022.</ref>
| \0 denotes an ASCII NUL character.
|-
| <code>"Linux KVM Hv"</code><ref>Linux 6.8.7 kernel source, [https://elixir.bootlin.com/linux/v6.8.7/source/arch/x86/kvm/hyperv.c#L2793 /arch/x86/kvm/hyperv.c, line 2793]</ref>
| Hyper-V emulation<ref>Linux kernel documentation, [https://docs.kernel.org/virt/kvm/api.html#kvm-get-supported-hv-cpuid Virtualization support: 4.118 KVM_GET_SUPPORTED_HV_CPUID]. [https://web.archive.org/web/20240316062357/https://docs.kernel.org/virt/kvm/api.html#kvm-get-supported-hv-cpuid Archived] on 26 Mar 2024.</ref>
|-
| [[Software:Bhyve|bhyve]]
| <code>"BHyVE BHyVE "</code>,<br/><code>"bhyve bhyve "</code>
| ID string changed from mixed-case to lower-case in 2013.<ref>FreeBSD [https://github.com/freebsd/freebsd-src/commit/560d5eda2cb0861d11dd055fc63199e21116f6e5 commit 560d5ed], 28 Jun 2013, see file /sys/amd64/vmm/x86.c, line 48. [https://web.archive.org/web/20240422224954/https://github.com/freebsd/freebsd-src/commit/560d5eda2cb0861d11dd055fc63199e21116f6e5 Archived] on 22 Apr 2024.</ref>

Lower-case string also used in bhyve-derived hypervisors such as xhyve and HyperKit.<ref>HyperKit source code, [https://github.com/moby/hyperkit/blob/45c0ba15f100871ba29d0bd227ca58e5426a4a50/src/lib/vmm/x86.c#L42 /src/lib/vmm/x86.c line 42], 8 May 2021.</ref>
|-
| [[Software:Xen|Xen]]
| <code>"XenVMMXenVMM"</code><ref name="xen_cpuid">Xen, [https://xenbits.xen.org/docs/unstable/hypercall/x86_32/include,public,arch-x86,cpuid.h.html CPUID Interface to Xen]. [https://web.archive.org/web/20240422225902/https://xenbits.xen.org/docs/unstable/hypercall/x86_32/include,public,arch-x86,cpuid.h.html Archived] on 22 Apr 2024.</ref>
| Only when using HVM (hardware virtual machine) mode.
|-
| [[Software:QEMU|QEMU]]
| <code>"TCGTCGTCGTCG"</code><ref>QEMU source code, [https://github.com/qemu/qemu/blob/2cc68629a6fc198f4a972698bdd6477f883aedfb/target/i386/cpu.c#L6475 fb/target/i386/cpu.c, line 6475], 18 Mar 2024.</ref>
| Only when the TCG (Tiny Code Generator) is enabled.
|-
| [[Company:Parallels|Parallels]]
| <code>"prl hyperv{{spaces|2}}"</code>,<br/><code>" lrpepyh{{spaces|2}}vr"</code>
| The {{nowrap|<code>" lrpepyh{{spaces|2}}vr"</code>}} string is an [[Endianness|endianness]]-swapped version of the {{nowrap|<code>"prl hyperv{{spaces|2}}"</code>}} string, observed in some versions of Parallels Workstation.<ref>Xakep, [https://xakep.ru/2013/11/08/61563/ Детектим виртуалки &#91;Detecting Virtual Machines&#93;] (in Russian), 8 Nov 2013 - lists the values returned in EBX/ECX/EDX for {{nowrap|1=CPUID.(EAX=40000000)}} on Parallels Workstation as 0x70726c20, 0x68797065 and 0x72762020, respectively - which corresponds to the endianness-swapped {{nowrap|<code>" lrpepyh{{spaces|2}}vr"</code>}} string. [https://web.archive.org/web/20150325073450/https://xakep.ru/2013/11/08/61563/ Archived] on 25 Mar 2015.</ref> |-
| [[Company:VMware|VMware]]
| <code>"VMwareVMware"</code><ref>VMWare, [https://kb.vmware.com/s/article/1009458 Mechanisms to determine if software is running in a VMware virtual machine], 1 May 2015. [https://web.archive.org/web/20220123040706/https://kb.vmware.com/s/article/1009458 Archived] on 23 Jan 2022.</ref>
|
|-
| Project ACRN
| <code>"ACRNACRNACRN"</code><ref>Project ACRN, [https://projectacrn.github.io/latest/developer-guides/hld/hv-cpu-virt.html#cpuid-virtualization CPUID Virtualization], 20 Oct 2022. [https://web.archive.org/web/20230325163003/https://projectacrn.github.io/latest/developer-guides/hld/hv-cpu-virt.html#cpuid-virtualization Archived] on 25 Mar 2023.</ref>
|
|-
| [[Software:VirtualBox|VirtualBox]]
| <code>"VBoxVBoxVBox"</code><ref>VirtualBox documentation, [https://www.virtualbox.org/manual/ch09.html#gimdebug 9.30 Paravirtualized Debugging]. [https://web.archive.org/web/20240422140649/https://www.virtualbox.org/manual/ch09.html#gimdebug Archived] on 22 Apr 2024.</ref>
| Only when configured to use the "hyperv" paravirtualization provider.
|-
| [[QNX]] Hypervisor
| <code>"QXNQSBMV"</code>
| The QNX hypervisor detection method provided in the official QNX documentation<ref>QNX, [https://www.qnx.com/developers/docs/7.1/#com.qnx.doc.hypervisor.safety.user/topic/qhs/guest_check.html Hypervisor - Checking the guest's environment], 25 Mar 2022. [https://web.archive.org/web/20240422005549/https://www.qnx.com/developers/docs/7.1/#com.qnx.doc.hypervisor.safety.user/topic/qhs/guest_check.html Archived] on 22 Apr 2024.</ref> checks only the first 8 characters of the string, as provided in EBX and ECX (including an endianness swap) - EDX is ignored and may take any value.
|-
| [[Software:NetBSD#Virtualization|NetBSD NVMM]]
| <code>"___ NVMM ___"</code><ref>NetBSD source code, [https://github.com/NetBSD/src/blob/90116d8fc2f0c32a7863c868afa8d77e9a865cc7/sys/dev/nvmm/x86/nvmm_x86_vmx.c#L1430 /sys/dev/nvmm/x86/nvmm_x86_vmx.c, line 1430], 6 Nov 2023.</ref>
|-
| [[Software:OpenBSD|OpenBSD]] VMM
| <code>"OpenBSDVMM58"</code><ref>OpenBSD source code, [https://github.com/openbsd/src/blob/1ebbcee88fd42e4612c9e2e6d12b4aad159f7741/sys/arch/amd64/include/vmmvar.h#L24 /sys/arch/amd64/include/vmmvar.h, line 24], 9 Apr 2024.</ref>
|
|-
| Siemens Jailhouse
| <code>"Jailhouse\0\0\0"</code><ref>Siemens Jailhouse hypervisor documentation, [https://github.com/siemens/jailhouse/blob/e57d1eff6d55aeed5f977fe4e2acfb6ccbdd7560/Documentation/hypervisor-interfaces.txt hypervisor-interfaces.txt, line 39], 27 Jan 2020. [https://web.archive.org/web/20240705104235/https://github.com/siemens/jailhouse/blob/e57d1eff6d55aeed5f977fe4e2acfb6ccbdd7560/Documentation/hypervisor-interfaces.txt Archived] on Jul 5, 2024.</ref>
| \0 denotes an ASCII NUL character.
|-
| [[Company:Bitdefender|Bitdefender]] Napoca
| <code>"Napocahv{{spaces|4}}"</code><ref>Bitdefender Napoca source code, [https://github.com/bitdefender/napoca/blob/c97d26c672ac9dba5373385fc69be32a856a4d02/napoca/kernel/guestenlight.c#L293 /napoca/kernel/guestenlight.c, line 293], 30 Jul 2020.</ref>
|
|-
| FEX-Emu
| <code>"FEXIFEXIEMU\0"</code><ref>FEX-Emu documentation, [https://github.com/FEX-Emu/FEX/blob/9d2f557666e4fdce73ccfead37a911efdd562b62/docs/CPUID.md FEXCore custom CPUID functions], 24 May 2024.</ref>
| \0 denotes an ASCII NUL character.
|-
| Intel HAXM
| <code>"HAXMHAXMHAXM"</code><ref>Intel HAXM source code, [https://github.com/intel/haxm/blob/cc86e90b5ed959e6904c13b54e21ad45b9ad12ce/core/cpuid.c#L979 /core/cpuid.c, line 979], 20 Jan 2023. [https://archive.today/20240422234829/https://github.com/intel/haxm/blob/cc86e90b5ed959e6904c13b54e21ad45b9ad12ce/core/cpuid.c%23L979 Archived] on 22 Apr 2024.</ref>
| Project discontinued.
|-
| Intel KGT (Trusty)
| <code>"EVMMEVMMEVMM"</code><ref name="ikgt-source">Intel KGT source code (trusty branch), [https://github.com/intel/ikgt-core/blob/7dfd4d1614d788ec43b02602cce7a272ef8d5931/vmm/vmexit/vmexit_cpuid.c /vmm/vmexit/vmexit_cpuid.c, lines 17-75], 15 May 2019</ref>
| On "trusty" branch of KGT only, which is used for the [https://www.intel.com/content/www/us/en/developer/topic-technology/open/trusty/overview.html Intel x86 Architecture Distribution of Trusty OS] ([https://web.archive.org/web/20230821024540/https://www.intel.com/content/www/us/en/developer/topic-technology/open/trusty/overview.html archive])

(KGT also returns a signature in <code>CPUID</code> leaf 3: ECX=<code>0x4D4D5645 "EVMM"</code> and EDX=<code>0x43544E49 "INTC"</code>)
|-
| [[Company:Unisys|Unisys]] s-Par
| <code>"UnisysSpar64"</code><ref>Linux kernel v5.18.19 source code, [https://elixir.bootlin.com/linux/v5.18.19/source/drivers/visorbus/visorchipset.c /source/drivers/visorbus/visorchipset.c, line 28]</ref>
|
|-
| {{nowrap|[[Company:Lockheed Martin|Lockheed Martin]] LMHS}}
| <code>"SRESRESRESRE"</code><ref>N. Moore, [https://github.com/systemd/systemd/pull/25594/commits/edc028437def5c1e005ce1b965ecf400a7c1498a virt: Support detection of LMHS SRE guests #25594], 1 Dec 2022 - Lockheed Martin-provided pull-request for systemd, adding CPUID hypervisor ID string for the LMHS SRE hypervisor. [https://web.archive.org/web/20240423204315/https://github.com/systemd/systemd/pull/25594/commits/edc028437def5c1e005ce1b965ecf400a7c1498a Archived] on 23 Apr 2024.</ref>
|}

{{vpad}}

== EAX=8000'0000h: Highest Extended Function Implemented ==
The highest calling parameter is returned in EAX.

EBX/ECX/EDX return the manufacturer ID string (same as EAX=0) on AMD but not Intel CPUs.

== EAX=8000'0001h: Extended Processor Info and Feature Bits ==
This returns extended feature flags in EDX and ECX.

Many of the bits in <code>EDX</code> (bits 0 through 9, 12 through 17, 23, and 24) are duplicates of <code>EDX</code> from the <code>EAX=1</code> leaf - these bits are highlighted in light yellow. (These duplicated bits are present on AMD but not Intel CPUs.)

'''AMD feature flags''' are as follows:<ref>{{Citation |url=http://developer.amd.com/wordpress/media/2012/10/25481.pdf |title=CPUID Specification, publication no.25481, rev 2.34 |publisher=[[Engineering:AMD|AMD]] |date=September 2010 |archive-url=https://web.archive.org/web/20220818192714/http://developer.amd.com/wordpress/media/2012/10/25481.pdf |archive-date=18 Aug 2022 |url-status=dead}}</ref><ref>[https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/x86/include/asm/cpufeatures.h?id=HEAD Linux kernel source code]</ref>
{| class="wikitable"
|+ CPUID EAX=8000'0001h: Feature bits in EDX and ECX
! rowspan=2 | Bit 
! colspan=2 | EDX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="34" |
! colspan=2 | ECX
! rowspan=2 | Bit
|-
! Short
! Feature 
! Short
! Feature
|-
! 0
| fpu || {{some|align=left|Onboard [[X87|x87]] FPU}}
| lahf_lm || <code>LAHF</code>/<code>SAHF</code> in long mode
! 0
|-
! 1
| vme || {{some|align=left|Virtual mode extensions (VIF)}}
| cmp_legacy || Hyperthreading not valid
! 1
|-
! 2
| de || {{some|align=left|Debugging extensions ([[Control register#CR4|CR4]] bit 3)}}
| svm || Secure Virtual Machine
! 2
|-
! 3
| pse || {{some|align=left|[[Page Size Extension]]}}
| extapic || Extended [[Advanced Programmable Interrupt Controller|APIC]] space
! 3
|-
! 4
| tsc || {{some|align=left|[[Time Stamp Counter]]}}
| cr8_legacy || [[Control register#CR8|CR8]] in 32-bit mode
! 4
|-
! 5
| msr || {{some|align=left|[[Model-specific register]]s}}
| abm/lzcnt || Advanced bit manipulation <code>(LZCNT</code> and <code>POPCNT</code>)
! 5
|-
! 6
| pae || {{some|align=left|[[Physical Address Extension]]}}
| sse4a || SSE4a
! 6
|-
! 7
| mce || {{some|align=left|Machine Check Exception}}
| misalignsse || Misaligned [[Streaming SIMD Extensions|SSE]] mode
! 7
|-
! 8
| cx8 || {{some|align=left|<code>CMPXCHG8B</code> ([[Compare-and-swap|compare-and-swap]]) instruction}}
| 3dnowprefetch || <code>PREFETCH</code> and <code>PREFETCHW</code> instructions
! 8
|-
! 9
| apic || {{some|align=left|Onboard [[Advanced Programmable Interrupt Controller]]}}
| osvw || OS Visible Workaround
! 9
|-
! 10
| (syscall){{efn|text=The use of EDX bit 10 to indicate support for <code>SYSCALL</code>/<code>SYSRET</code> is only valid on <code>AuthenticAMD</code> [[Engineering:List of AMD CPU microarchitectures|Family 5]] Model 7 CPUs ([[Engineering:AMD K6|AMD K6]], 250nm "Little Foot") — for all other processors, EDX bit 11 should be used instead. These instructions were first introduced on Model 7<ref>AMD, [https://www.ardent-tool.com/CPU/docs/AMD/K6/20695.pdf AMD-K6 Processor Data Sheet], order no. 20695H/0, march 1998, section 24.2, page 283</ref> — the CPUID bit to indicate their support was moved<ref>AMD, [https://www.ardent-tool.com/CPU/docs/AMD/K6/revs/21846h.pdf AMD-K6 Processor Revision Guide], order no. 21846H/0, June 1999, section 3.2.1, page 17</ref> to EDX bit 11 from Model 8 ([[Engineering:AMD K6-2|AMD K6-2]]) onwards.<p>The version of <code>SYSCALL</code> present in Model 7 (indicated by EDX bit 10) is not fully compatible with the version of <code>SYSCALL</code> present in Model 8 and later CPUs (indicated by EDX bit 11) in later processors (the Model 7 version doesn't allow <code>IRET</code> after <code>SYSCALL</code> while later versions do).<ref>Brian Gerst, [https://groups.google.com/g/fa.linux.kernel/c/COqRnq7Y7FE/m/dwWuu0ly5qIJ syscall w/6 args support?], Linux kernel mailing list, 8-9 Dec 1999. [https://web.archive.org/web/20260310105923/https://groups.google.com/g/fa.linux.kernel/c/COqRnq7Y7FE/m/dwWuu0ly5qIJ Archived] on 10 Mar 2026.</ref></p>}}
| (<code>SYSCALL</code>/<code>SYSRET</code>, K6 only)
| ibs || [[Hardware performance counter#Instruction based sampling|Instruction Based Sampling]]
! 10
|-
! 11
| syscall{{efn|On Intel CPUs, the CPUID bit for <code>SYSCALL</code>/<code>SYSRET</code> is only set if the <code>CPUID</code> instruction is executed in 64-bit mode.<ref>Intel, [https://kib.kiev.ua/x86docs/Intel/SDMs/325462-079.pdf Intel 64 and IA-32 Architectures Software Developer's Manual], order no. 325462-079, march 2023, table 3-8 on page 3-238</ref>}} || <code>SYSCALL</code> and <code>SYSRET</code> instructions
| xop || [[XOP instruction set]]
! 11
|-
! 12
| mtrr || {{some|align=left|Memory Type Range Registers}}
| skinit || <code>SKINIT</code>/<code>STGI</code> instructions
! 12
|-
! 13
| pge || {{some|align=left|Page Global Enable bit in [[Control register#CR4|CR4]]}}
| wdt || [[Watchdog timer]]
! 13
|-
! 14
| mca || {{some|align=left|Machine check architecture}}
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''<!-- recognized as "TBM0 Instruction Support" by HWiNFO 8.24, but not set in any known processor or listed in any known public documentation -->
! 14
|-
! 15
| cmov || {{some|align=left|Conditional move and <code>[[FCMOV]]</code> instructions}}
| lwp || Light Weight Profiling<ref>{{Citation |url=http://support.amd.com/us/Processor_TechDocs/43724.pdf |title=Lightweight Profiling Specification |publisher=[[Engineering:AMD|AMD]] |date=August 2010 |access-date=2013-04-03 |url-status=dead |archive-url=https://web.archive.org/web/20121127061327/http://support.amd.com/us/Processor_TechDocs/43724.pdf | archive-date=2012-11-27 }}</ref>
! 15
|-
! 16
| pat{{efn|name=ext1_edx_16_24|text=On some processors − Cyrix [[Engineering:MediaGX|MediaGX]]m,<ref>Cyrix, [http://datasheets.chipdb.org/Cyrix/detect.pdf Cyrix CPU Detection Guide], rev 1.01, oct 2, 1997, page 12</ref> several [[Engineering:Geode (processor)|Geode]]s (NatSemi Geode GXm, GXLV, GX1; AMD Geode GX1<ref>AMD, [https://www.amd.com/system/files/TechDocs/goede_gx1_databook-rev5.pdf Geode GX1 Processor Data Book], rev 5.0, december 2003, pages 202 and 226. [https://web.archive.org/web/20200420011559/https://www.amd.com/system/files/TechDocs/goede_gx1_databook-rev5.pdf Archived] on 20 Apr 2020.</ref>) and [[Engineering:Transmeta Crusoe|Transmeta Crusoe]]<ref>Transmeta, [http://datasheets.chipdb.org/Transmeta/Crusoe/Crusoe_CPUID_5-7-02.pdf Processor Recognition], 2002-05-07, page 5</ref> (<code>CyrixInstead</code>/{{nowrap|<code>Geode by NSC</code>}}/<code>GenuineTMx86</code> Family 5 Model 4) — EDX bits 16 and 24 have a different meaning:
* Bit 16: Floating-point Conditional Move (<code>[[FCMOV]]</code>) supported
* Bit 24: Cyrix [[List of discontinued x86 instructions#Cyrix EMMI instructions|EMMI]] ([[Extended MMX|extended MMX]]) instructions supported. (The EMMI instructions are also present on <code>CyrixInstead</code> Family 6 processors, such as the 6x86MX and MII, even though they don't set this bit.)
}}
| {{some|align=left|Page Attribute Table}}
| fma4 || [[FMA instruction set#FMA4 instruction set|4-operand fused multiply-add instructions]]
! 16
|-
! 17
| pse36 || {{some|align=left|[[PSE-36|36-bit page size extension]]}}
| tce || Translation Cache Extension
! 17
|-
! 18
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 18
|-
! 19
| ecc || "Athlon MP" / "[[Engineering:Sempron|Sempron]]" CPU brand identification{{efn|text=EDX bit 19 is used for CPU brand identification on <code>AuthenticAMD</code> Family 6 processors only - the bit is, combined with processor signature and [[Engineering:Front-side bus|FSB]] speed, used to identify processors as either multiprocessor-capable or carrying the [[Engineering:Sempron|Sempron]] brand name.<ref name="amd_20734_313">AMD, [https://web.archive.org/web/20060626212818/http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf Processor Recognition Application Note], pub.no. 20734, rev. 3.13, december 2005. Section 2.2.2 (p.20) and Section 3 (pages 33 to 40) provide details on how {{nowrap|1=CPUID.(EAX=8000_0001):EDX[bit 19]}} should be used to identify processors. Section 3 also provides information on AMD's brand name string MSRs. Archived from the [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf original] on Jun 26, 2006.</ref>}}
| nodeid_msr || NodeID MSR (<code>C001_100C</code>)<ref>AMD, [https://www.amd.com/system/files/TechDocs/31116.pdf Family 10h BKDG], document no. 31116, rev 3.62, jan 11, 2013, p. 388 - lists the NodeId bit. [https://web.archive.org/web/20190116230101/https://www.amd.com/system/files/TechDocs/31116.pdf Archived] on 16 Jan 2019.</ref>
! 19
|-
! 20
| nx || [[NX bit]] (page-table no-execute bit)
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 20
|-
! 21
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| tbm || [[Bit Manipulation Instruction Sets#TBM|Trailing Bit Manipulation]]
! 21
|-
! 22
| mmxext || [[Engineering:3DNow!#3DNow extensions|Extended MMX]] (non-XMM subset of [[Streaming SIMD Extensions|SSE1]])
| topoext || Topology Extensions
! 22
|-
! 23
| mmx || {{some|align=left|[[MMX (instruction set)|MMX]] instructions}}
| perfctr_core || Core performance counter extensions
! 23
|-
! 24
| fxsr{{efn|name=ext1_edx_16_24}} || {{some|align=left|<code>FXSAVE</code>, <code>FXRSTOR</code> instructions, [[Control register#CR4|CR4]] bit 9}}
| perfctr_nb || Northbridge performance counter extensions
! 24
|-
! 25
| fxsr_opt || <code>FXSAVE</code>/<code>FXRSTOR</code> optimizations
| (StreamPerfMon) || (Streaming performance monitor architecture){{efn|text=ECX bit 25 is listed as StreamPerfMon in revision 3.20 of AMD APM<ref>AMD, [https://kib.kiev.ua/x86docs/AMD/AMD64/24594_APM_v3-r3.20.pdf AMD64 Architecture Programmer's Manual Volume 3], pub. no. 24594, rev 3.20, may 2013, page 579 - lists the StreamPerfMon bit</ref> only - it is listed as reserved in later revisions. The bit is set on Excavator and Steamroller CPUs only.}}
! 25
|-
! 26
| pdpe1gb || [[Gibibyte]] pages
| dbx || Data breakpoint extensions
! 26
|-
! 27
| rdtscp || <code>RDTSCP</code> instruction
| perftsc ||Performance timestamp counter (PTSC) <!-- not the same as TSC -->
! 27
|-
! 28
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| pcx_l2i || L2I perf counter extensions
! 28
|-
! 29
| lm || [[Long mode]] ([[X86-64|x86-64]])
| monitorx || <code>MONITORX</code> and <code>MWAITX</code> instructions
! 29
|-
! 30
| 3dnowext || [[Engineering:3DNow!#3DNow extensions|Extended 3DNow!]]
| addr_mask_ext || Address mask extension to 32 bits for instruction breakpoints
! 30
|-
! 31
| 3dnow || [[Engineering:3DNow!|3DNow!]]
| colspan="2" style="text-align:center; background:lightgrey;" | ''(reserved)'' <!-- used for unknown purpose on AMD 4700S Desktop Kit -->
! 31
|}
{{notelist}}
{{vpad}}

== EAX=8000'0002h,8000'0003h,8000'0004h: Processor Brand String ==
These return the processor brand string in EAX, EBX, ECX and EDX. <code>CPUID</code> must be issued with each parameter in sequence to get the entire 48-byte ASCII processor brand string.<ref name="intel1">{{cite web|url=http://download.intel.com/design/processor/applnots/24161832.pdf |title=Intel Processor Identification and the CPUID Instruction |publisher=Download.intel.com |date=2012-03-06 |access-date=2013-04-11}}</ref> It is necessary to check whether the feature is present in the CPU by issuing <code>CPUID</code> with <code>EAX = 80000000h</code> first and checking if the returned value is not less than <code>80000004h</code>.

The string is specified in Intel/AMD documentation to be [[Null-terminated string|null-terminated]], however this is not always the case (e.g. DM&P [[Vortex86#Vortex86DX3|Vortex86DX3]] and AMD [[Engineering:List of AMD Ryzen processors#Ryzen 6000 series|Ryzen 7 6800HS]] are known to return non-null-terminated brand strings in leaves <code>80000002h</code>-<code>80000004h</code><ref>InstLatx64, [http://users.atw.hu/instlatx64/Vortex86_SoC/Vortex86%20SoC0000611_Vortex86DX3_CPUID.txt Vortex86DX3 CPUID dump], 27 Sep 2021. [https://web.archive.org/web/20211021212842/http://users.atw.hu/instlatx64/Vortex86_SoC/Vortex86%20SoC0000611_Vortex86DX3_CPUID.txt Archived] on 21 Oct 2021.</ref><ref>InstLatx64, [http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0A40F41_K19_Rembrandt_01_CPUID.txt AMD Ryzen 7 6800HS CPUID dump], 21 Feb 2022. [https://web.archive.org/web/20230324010348/http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0A40F41_K19_Rembrandt_01_CPUID.txt Archived] on 24 Mar 2023.</ref>), and software should not rely on it.

<syntaxhighlight lang="c">
#include <stdio.h>
#include <string.h>
#include <cpuid.h>

int main()
{
    unsigned int regs[12];
    char str[sizeof(regs)+1];

    __cpuid(0x80000000, regs[0], regs[1], regs[2], regs[3]);

    if (regs[0] < 0x80000004)
        return 1;

    __cpuid(0x80000002, regs[0], regs[1], regs[2], regs[3]);
    __cpuid(0x80000003, regs[4], regs[5], regs[6], regs[7]);
    __cpuid(0x80000004, regs[8], regs[9], regs[10], regs[11]);

    memcpy(str, regs, sizeof(regs));
    str[sizeof(regs)] = '\0';
    printf("%s\n", str);

    return 0;
}
</syntaxhighlight>

On AMD processors, from [[Engineering:List of AMD Athlon processors#Athlon (Model 2, K75 "Pluto/Orion", 180 nm)|180nm Athlon]] onwards (<code>AuthenticAMD</code> Family 6 Model 2 and later), it is possible to modify the processor brand string returned by CPUID leaves <code>80000002h</code>-<code>80000004h</code> by using the <code>WRMSR</code> instruction to write a 48-byte replacement string to MSRs <code>C0010030h</code>-<code>C0010035h</code>.<ref name="amd_20734_313"/><ref>Chips and Cheese, [https://chipsandcheese.com/2022/10/27/why-you-cant-trust-cpuid/ Why you can't trust CPUID], 27 Oct 2022. [https://web.archive.org/web/20221103061909/https://chipsandcheese.com/2022/10/27/why-you-cant-trust-cpuid/ Archived] on 3 Nov 2022.</ref> This can also be done on AMD Geode GX/LX, albeit using MSRs <code>300Ah</code>-<code>300Fh</code>.<ref>AMD, [https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/datasheets/33234H_LX_databook.pdf Geode LX Databook], pub.id. 33234H, Feb 2009, page 207.</ref>
{{vpad}}
The string returned by CPUID leaves <code>80000002h</code>-<code>80000004h</code> frequently contains multiple leading, trailing or middle spaces — a few examples of Processor Brand Strings with many consecutive spaces that have appeared in Intel/AMD CPUs include:
* {{nowrap|<code>{{spaces|7}}Intel(R) Core(TM) i7-3960X CPU @ 3.30GHz</code><ref>InstLatx64, [https://instlatx64.github.io/InstLatx64/GenuineIntel/GenuineIntel00206D6_SandyBridgeE_CPUID.txt HexaCore Intel Core i7-3960X Extreme Edition] CPUID dump</ref>}}
* {{nowrap|<code>Intel(R) Xeon(R) CPU{{spaces|11}}W3670{{spaces|2}}@ 3.20GHz</code><ref>InstLatx64, [https://instlatx64.github.io/InstLatx64/GenuineIntel/GenuineIntel00206C2_Gulftown_01_CPUID.txt HexaCore Intel Xeon W3670] CPUID dump</ref>}}
* {{nowrap|<code>AMD EPYC 9655 96-Core Processor{{spaces|16}}</code><ref>InstLatx64, [https://instlatx64.github.io/InstLatx64/AuthenticAMD/AuthenticAMD0B00F21_K20_Turin_01_CPUID.txt AMD EPYC 9655] CPUID dump</ref>}}
{{vpad}}
In some cases, determining the CPU vendor requires examining not just the Vendor ID in CPUID leaf 0 and the CPU signature in leaf 1, but also the Processor Brand String in leaves <code>80000002h</code>-<code>80000004h</code>. Known cases include:
* Montage Jintide CPUs can be distinguished from the Intel Xeon CPU models they're based on by the presence of the substring <code>Montage</code> in the brand string of the Montage CPUs (e.g. Montage Jintide C2460<ref>InstLatx64, [http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0050654_SkylakeXeon_Jintide_CPUID1.txt 2x 24-core Montage Jintide C2460] CPUID dump</ref> and Intel Xeon Platinum 8160<ref>InstLatx64, [http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0050654_SkylakeXeon_20_CPUID.txt 2x 24-core Intel Xeon Platinum 8160] CPUID dump</ref> - both of which identify themselves as <code>GenuineIntel</code> Family 6 Model 55h Stepping 4 - can be distinguished in this manner.)
* <code>CentaurHauls</code> Family 6 CPUs may be either VIA or Zhaoxin CPUs - these can be distinguished by the presence of the substring <code>ZHAOXIN</code> in the brand string of the Zhaoxin CPUs (e.g. Zhaoxin KaiXian ZX-C+ C4580<ref>InstLatx64, [http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls00006FE_CNR_Isaiah_CPUID3.txt Zhaoxin KaiXian ZX-C+ C4580] CPUID dump</ref> and VIA Eden X4 C4250<ref>InstLatx64, [http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls00006FE_CNR_Isaiah_CPUID.txt VIA Eden X4 C4250] CPUID dump</ref> - both of which identify themselves as <code>CentaurHauls</code> Family 6 Model 0Fh Stepping 0Eh - can be distinguished in this manner.)
* Apple's Rosetta 2 x86 emulator — which identifies itself as <code>GenuineIntel</code> Family 6 — can be distinguished from the Intel Xeon processor it is emulating by the presence of the substring <code>VirtualApple</code> in the brand string of Rosetta 2.<ref name="mihocka_2024"/>
* Microsoft's x86-on-ARM emulator — which, in 64-bit mode, identifies itself as <code>AuthenticAMD</code> Family 0Fh — can be distinguished from the AMD processor it is emulating by the presence of the substring {{nowrap|<code>Virtual CPU</code>}} in the emulator's brand string.<ref name="mihocka_2024"/>
{{vpad}}

== EAX=8000'0005h: L1 Cache and TLB Identifiers ==
This provides information about the processor's level-1 cache and [[Translation lookaside buffer|TLB]] characteristics in EAX, EBX, ECX and EDX as follows:{{efn|text=On some older Cyrix and Geode CPUs (specifically, <code>CyrixInstead</code>/{{nowrap|<code>Geode by NSC</code>}} Family 5 Model 4 CPUs only), leaf <code>80000005h</code> exists but has a completely different format, similar to that of leaf 2.<ref>Cyrix, [https://www.ardent-tool.com/CPU/docs/Cyrix/112.pdf Application Note 112: Cyrix CPU Detection Guide], page 17, 21 July 1998.</ref>}}
* EAX: information about L1 hugepage TLBs (TLBs that hold entries corresponding to 2M/4M pages){{efn|text=On processors that can only handle small-pages in their TLBs, this leaf will return 0 in EAX. (On such processors, which include e.g. AMD K6 and Transmeta Crusoe, hugepage entries in the page-tables are broken up into 4K pages as needed upon entry into the TLB.)<br/>On some processors, e.g. VIA Cyrix III "Samuel",<ref>Instlatx64, [http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls0000663_C5A_Samuel_CPUID.txt VIA Cyrix III "Samuel" CPUID dump]</ref> this leaf returns <code>0x80000005</code> in EAX. This has the same meaning as EAX=0, i.e. no hugepage TLBs.}}
* EBX: information about L1 small-page TLBs (TLBs that hold entries corresponding to 4K pages) 
* ECX: information about L1 data cache
* EDX: information about L1 instruction cache
{| class="wikitable"
|+ CPUID EAX=8000'0005h: L1 Cache/TLB information in EAX,EBX,ECX,EDX
! Bits
! EAX !! EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5" |
! ECX !! EDX
! Bits
|-
! 7:0
| colspan=2 | Number of instruction TLB entries{{efn|name=tmta_tlbsize|On Transmeta CPUs, the value <code>FFh</code> is used to indicate a 256-entry TLB.}}
| colspan=2 | Cache line size in bytes
! 7:0
|-
! 15:8
| colspan=2 | instruction TLB associativity{{efn|name=ex2_assoc|text=For the associativity fields of leaf <code>80000005h</code>, the following values are used:
{{(!}} class="wikitable sortable"
! Value !! Meaning
{{!}}-
{{!}} 0 {{!!}} (reserved)
{{!}}-
{{!}} 1 {{!!}} Direct-mapped
{{!}}-
{{!}} 2 to <code>FEh</code> {{!!}} N-way set-associative (field encodes N)
{{!}}-
{{!}} <code>FFh</code> {{!!}} Fully-associative
{{!)}}
}}
| colspan=2 | Number of cache lines per tag
! 15:8
|-
! 23:16
| colspan=2 | Number of data TLB entries{{efn|name=tmta_tlbsize}}
| colspan=2 | Cache associativity{{efn|name=ex2_assoc}}
! 23:16
|-
! 31:24
| colspan=2 | Data TLB associativity{{efn|name=ex2_assoc}}
| colspan=2 | Cache size in kibibytes
! 31:24
|}
{{notelist}}
{{vpad}}

== EAX=8000'0006h: Extended L2 Cache Features ==
Returns details of the L2 cache in ECX, including the line size in bytes (Bits 07 - 00), type of associativity (encoded by a 4 bits field; Bits 15 - 12) and the cache size in KiB (Bits 31 - 16).
<syntaxhighlight lang="c">
#include <stdio.h>
#include <cpuid.h>

int main()
{
    unsigned int eax, ebx, ecx, edx;
    unsigned int lsize, assoc, cache;

    __cpuid(0x80000006, eax, ebx, ecx, edx);
    
    lsize = ecx & 0xff;
    assoc = (ecx >> 12) & 0x0f;
    cache = (ecx >> 16) & 0xffff;

    printf("Line size: %d B, Assoc. type: %d, Cache size: %d KiB.\n", lsize, assoc, cache);

    return 0;
}

</syntaxhighlight>
{{vpad}}

== EAX=8000'0007h: Processor Power Management Information and RAS Capabilities ==
This function provides information about power management, power reporting and RAS ([[Reliability, availability and serviceability]]) capabilities of the CPU.

{| class="wikitable"
|+ CPUID EAX=8000'0007h: RAS features in EBX and power management features in EDX
! rowspan=2 | Bit 
! colspan=2 | EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="22" |
! colspan=2 | EDX
! rowspan=2 | Bit
|-
! Short || Feature
! Short || Feature
|-
! 0
| MCAOverflowRecov || MCA (Machine Check Architecture) overflow recovery support
| TS || Temperature Sensor
! 0
|-
! 1
| SUCCOR || Software uncorrectable error containment and recovery capability
| FID || Frequency ID Control
! 1
|-
! 2
| HWA || Hardware assert support (MSRs <code>C001_10C0</code> to <code>C001_10DF</code>)
| VID || Voltage ID Control
! 2
|-
! 3
| ScalableMca || Scalable MCA supported
| TTP || THERMTRIP
! 3
|-
! 4
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''<!-- used for unknown purpose on Zen2 and later -->
| TM || Hardware thermal control (HTC) supported
! 4
|-
! 5
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''<!-- used for unknown purpose on Zen4 -->
| STC || Software thermal control (STC) supported<ref>AMD, [https://www.amd.com/system/files/TechDocs/31116.pdf BKDG for AMD Family 10h Processors], pub.no. 31116, rev 3.62, jan 11, 2013, page 392. [https://web.archive.org/web/20190116230101/https://www.amd.com/system/files/TechDocs/31116.pdf Archived] on 16 Jan 2019.</ref>
! 5
|-
! 6
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| 100MHzSteps || 100&nbsp;MHz multiplier control
! 6
|-
! 7
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| HwPstate || Hardware P-state control (MSRs <code>C001_0061</code> to <code>C001_0063</code>)
! 7
|-
! 8
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| TscInvariant || Invariant TSC — TSC ([[Time Stamp Counter]]) rate is guaranteed to be invariant across all P-states, C-states, and stop grant transitions.
! 8
|-
! 9
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| CPB || Core Performance Boost
! 9
|-
! 10
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| EffFreqRO || Read-only effective frequency interface (MSRs <code>C000_00E7</code> and <code>C000_00E8</code>)
! 10
|-
! 11
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| ProcFeedback&shy;Interface || Processor Feedback Interface supported
! 11
|-
! 12
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| ProcPower&shy;Reporting || Processor power reporting interface supported
! 12
|-
! 13
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| Connected&shy;Standby || Connected Standby<ref name="amd_56713_p99">AMD, [https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip PPR For AMD Family 19h Model 61h rev B1 procesors], pub.no. 56713, rev 3.05, Mar 8, 2023, pages 99-100. [https://web.archive.org/web/20230425231817/https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip Archived] on 25 Apr 2023.</ref>
! 13
|-
! 14
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| RAPL || Running Average Power Limit<ref name="amd_56713_p99"/>
! 14
|-
! 15
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| FastCPPC || Fast CPPC (Collaborative Processor Performance Control) supported<ref name="amd_56713_p99"/>
! 15
|-
! 16
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| CppcPerfPriority || CPPC Performance Priority<ref name="cppc_69206_110"/>
! 16
|-
! <br/>26:17<br/>&nbsp;
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! <br/>26:17<br/>&nbsp;
|-
! 27
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''{{efn|1=Revision 1.00 of AMD's CPPC Performance Priority specification listed the feature as being indicated by bit 27 of EDX<ref>AMD, [https://docs.amd.com/api/khub/documents/GxcqEy4C6j3dRMU3DJpOcQ/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.41&download=true&locationValue=viewer AMD64 Collaborative Processor Performance Control (CPPC) Performance Priority], pub.no. 69206, rev 1.00, 25 Feb 2026. [https://web.archive.org/web/20260227053021/https://docs.amd.com/api/khub/documents/GxcqEy4C6j3dRMU3DJpOcQ/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.41&download=true&locationValue=viewer Archived] on 27 Feb 2026.</ref> - this was corrected to bit 16 in later revisions.<ref name="cppc_69206_110">AMD, [https://docs.amd.com/api/khub/documents/GxcqEy4C6j3dRMU3DJpOcQ/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.46&download=true&locationValue=viewer AMD64 Collaborative Processor Performance Control (CPPC) Performance Priority], pub.no. 69206, rev 1.10, 4 Mar 2026. [https://web.archive.org/web/20260309012337/https://docs.amd.com/api/khub/documents/GxcqEy4C6j3dRMU3DJpOcQ/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.46&download=true&locationValue=viewer Archived] on 9 Mar 2026.</ref>}}
! 27
|-
! <br/>31:28<br/>&nbsp;
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! <br/>31:28<br/>&nbsp;
|}
{{notelist}}
{{vpad}}


{| class="wikitable"
|+ CPUID EAX=8000'0007h: Processor Feedback info in EAX and power monitoring interface info in ECX
! rowspan=2 | Bits 
! colspan=2 | EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="5" |
! colspan=2 | ECX
! rowspan=2 | Bits
|-
! Short || Feature
! Short || Feature
|-
! 7:0
| NumberOfMonitors || Number of Processor Feedback MSR pairs available, starting from MSR <code>C001_0080</code> onwards<ref>AMD, [https://www.amd.com/system/files/TechDocs/48751_16h_bkdg.pdf BKDG for AMD Family 16h Models 00-0Fh processors], pub.no. 48571, rev 3.03, Feb 19, 2015, page 482. [https://web.archive.org/web/20190116230055/https://www.amd.com/system/files/TechDocs/48751_16h_bkdg.pdf Archived] on 16 Jan 2019.</ref>
| rowspan=3 | CpuPwrSample&shy;TimeRatio
| rowspan=3 | Ratio of compute unit power accumulator sample period to TSC counter period. 
! 7:0
|-
! 15:8
| Version || Processor Feedback Capabilities version
! 15:8
|-
! 31:16
| MaxWrapTime || Maximum time between reads (in milliseconds) that software should use to avoid two wraps.
! 31:16
|}
{{vpad}}

== EAX=8000'0008h: Virtual and Physical Address Sizes ==

{| class="wikitable"
|+ CPUID EAX=8000'0008h: Feature bits in EBX
! rowspan=2 | Bit 
! colspan=2 | EBX
|-
! Short || Feature
|-
! 0
| clzero || <code>CLZERO</code> instruction
|-
! 1
| retired_instr || Retired instruction count MSR (<code>C000_00E9h</code>) supported
|-
! 2
| xrstor_fp_err || <code>XRSTOR</code> restores FP errors
|-
! 3
| invlpgb || <code>INVLPGB</code> and <code>TLBSYNC</code> instructions
|-
! 4
| rdpru || <code>RDPRU</code> instruction
|-
! 5
|
| ([[Engineering:PlayStation 5|PS5]] "xotext" / Execute-Only Memory)<ref>SpecterDev, [https://hardwear.io/usa-2023/presentation/next-gen-exploitation-exploring-the-PS5-security-landscape.pdf Next-Gen Exploitation: Exploring the PS5 Security Landscape], June 2023 ''hardwear.io'' conference presentation slide deck, pages 34, 41 and 53. [https://web.archive.org/web/20230610172512/https://hardwear.io/usa-2023/presentation/next-gen-exploitation-exploring-the-PS5-security-landscape.pdf Archived] on 10 Jun 2023.</ref>{{efn|name=cpuid_4700s|1=As of June 2025, bits 5, 7, and 11 of {{nowrap|1=CPUID.(EAX=8000_0008):EBX}} are not listed in any known public AMD documentation, but have been observed to be set on AMD 4700S Desktop Kit processors.<ref>Instlatx64, [http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0840F70_K17_CPUID.txt AMD 4700S 8-core Processor Desktop Kit CPUID dump]</ref>}}
|-
! 6
| mbe || Memory Bandwidth Enforcement
|-
! 7
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''{{efn|name=cpuid_4700s}}
|-
! 8
| mcommit || <code>MCOMMIT</code> instruction
|-
! 9
| wbnoinvd || <code>WBNOINVD</code> instruction
|-
! 10
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)'' <!-- used for unknown purpose on Zen 2 and 3 -->
|-
! 11
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''{{efn|name=cpuid_4700s}}
|-
! 12
| IBPB || Indirect Branch Prediction Barrier (performed by writing 1 to bit 0 of <code>PRED_CMD</code> (MSR <code>049h</code>))
|-
! 13
| wbinvd_int || <code>WBINVD</code> and <code>WBNOINVD</code> are interruptible
|-
! 14
| IBRS || Indirect Branch Restricted Speculation
|-
! 15
| STIBP || Single Thread Indirect Branch Prediction mode
|-
! 16
| IbrsAlwaysOn || IBRS mode has enhanced performance and should be left always on
|-
! 17
| StibpAlwaysOn || STIBP mode has enhanced performance and should be left always on
|-
! 18
| ibrs_preferred || IBRS preferred over software
|-
! 19
| ibrs_same_mode_protection || IBRS provides Same Mode Protection
|-
! 20
| no_efer_lmsle || <code>EFER.LMSLE</code> is unsupported{{efn|text=The LMSLE (Long Mode Segment Limit Enable) feature does not have its own CPUID flag and is detected by checking CPU family and model. It was introduced in <code>AuthenticAMD</code> Family 0Fh Model 14h<ref>AMD, [https://www.amd.com/system/files/TechDocs/26094.PDF BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD Opteron Processors], publication #26094, rev 3.30, feb 2006, pages 29-30 (lists Athlon 64 revision differences, including LMSLE) ([https://web.archive.org/web/20190116230059/https://www.amd.com/system/files/TechDocs/26094.PDF archived] on 16 Jan 2019), and [https://www.amd.com/system/files/TechDocs/25759.pdf Revision Guide for AMD Athlon 64 and AMD Opteron Processors], publication #25759, rev 3.79, july 2009, pages 7-8 (lists Athlon 64 revision IDs) ([https://web.archive.org/web/20190118074904/https://www.amd.com/system/files/TechDocs/25759.pdf archived] on 18 Jan 2019).</ref>
 (90nm Athlon64/Opteron) CPUs and is present in all later AMD CPUs - except the ones with the 'no_efer_lmsle' flag set.}}
|-
! 21
| invlpgb_nested || <code>INVLPGB</code> support for nested pages
|-
! 22
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
|-
! 23
| ppin || Protected Processor Inventory Number -

<code>PPIN_CTL</code> (<code>C001_02F0</code>) and <code>PPIN</code> (<code>C001_02F1</code>) MSRs are present<ref name="amd_56713_p99"/>
|-
! 24
| ssbd || Speculative Store Bypass Disable
|-
! 25
| ssbd_legacy || Speculative Store Bypass Disable Legacy
|-
! 26
| ssbd_no || Speculative Store Bypass Disable Not Required
|-
! 27
| cppc || Collaborative Processor Performance Control
|-
! 28
| psfd || Predictive Store Forward Disable
|-
! 29
| btc_no || Branch Type Confusion: Processor not affected
|-
! 30
| IBPB_RET || IBPB (see bit 12) also clears return address predictor
|-
! 31
| branch_sampling || Branch Sampling Support<ref>AMD, [https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip PPR for AMD Family 19h Model 01h, Revision B1 Processors, Volume 1 of 2], document no. 55898, rev 0.50, may 27, 2021, page 98 - lists branch-sampling bit. [https://web.archive.org/web/20220724144832/https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Archived] on Jul 24, 2022</ref>
|}

{| class="wikitable"
|+ CPUID EAX=8000'0008h: Size and range fields in EAX, ECX, EDX
|-
! Bits
! EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="7" |
! ECX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="7" |
! EDX
! Bits
|-
! style="padding-top:1em; padding-bottom:1em" | 7:0
| Number of Physical Address Bits
| Number of Physical Threads in processor (minus 1)
| rowspan="3" style="max-width:18em" | Maximum page count for <code>INVLPGB</code> instruction
! style="padding-top:1em; padding-bottom:1em" | 7:0
|-
! 11:8
| rowspan="2" | Number of Linear Address Bits
| style="text-align:center; background:lightgrey;"| ''(reserved)''
! 11:8
|-
! 15:12
| APIC ID Size
! 15:12
|-
! 17:16
| rowspan="2" | Guest Physical Address Size{{efn|text=A value of 0 indicates that the "Guest Physical Address Size" is the same as the "Number Of Physical Address Bits", specified in EAX[7:0].}}
| Performance Timestamp Counter size
| rowspan="3" style="max-width:18em" | Maximum ECX value recognized by <code>RDPRU</code> instruction
! 17:16
|-
! 23:18
| rowspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 23:18
|-
! style="padding-top:1em; padding-bottom:1em" | 31:24
| style="text-align:center; background:lightgrey;"| ''(reserved)''
! style="padding-top:1em; padding-bottom:1em" | 31:24
|}
{{notelist}}
{{vpad}}

== EAX=8000'000Ah: SVM features ==
This leaf returns information about AMD SVM (Secure Virtual Machine) features in EAX, EBX, ECX and EDX.

{|class="wikitable"
|+ CPUID EAX=8000'000Ah: SVM information in EAX, EBX and ECX
|-
! Bits
! EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="9" |
! EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan="9" |
! ECX
! Bits
|-
! 2:0
| rowspan="6" | SVM Revision Number
| rowspan="8" | Number of available ASIDs <br/>(address space identifiers)
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 2:0
|-
! 3
| Guest PMC Event Filtering<ref>AMD, [https://docs.amd.com/api/khub/documents/2eieIP7KVNk7sKFJ9Ew~Ng/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.48&download=true&locationValue=viewer AMD64 Guest PMC Event Filtering], pub.no. 69202, rev 1.00, 27 Feb 2026. [https://web.archive.org/web/20260311175356/https://docs.amd.com/api/khub/documents/2eieIP7KVNk7sKFJ9Ew~Ng/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.48&download=true&locationValue=viewer Archived] on 11 Mar 2026.</ref>
! 3
|-
! 4
| Page Modification Logging<ref>AMD, [https://docs.amd.com/api/khub/documents/bSG~MCDnO9H2gPucB8UbFQ/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.48&download=true&locationValue=viewer AMD64 Page Modification Logging], pub.no. 69208, rev 1.00, 10 Mar 2026. [https://web.archive.org/web/20260311174145/https://docs.amd.com/api/khub/documents/bSG~MCDnO9H2gPucB8UbFQ/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.48&download=true&locationValue=viewer Archived] on 11 Mar 2026.</ref>
! 4
|-
! 5
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 5
|-
! 6
| x2AVIC_EXT (4096 vCPUs supported in x2AVIC mode)
! 6
|-
! 7
| rowspan="3" style="text-align:center; background:lightgrey;" | ''(reserved)''
! 7
|-
! 8
| style="text-align:center; background:lightgrey;" | ''(hypervisor)''{{efn|text=Early revisions of AMD's "Pacifica" documentation listed EAX bit 8 as an always-zero bit reserved for hypervisor use.<ref>AMD, [https://web.archive.org/web/20110613111809/http://www.mimuw.edu.pl/~vincent/lecture6/sources/amd-pacifica-specification.pdf AMD64 Virtualization Codenamed "Pacifica" Technology], publication no. 33047, rev 3.01, May 2005, appendix B, page 81. Archived on Jun 13, 2011.</ref><p>Later AMD documentation, such as #25481 "CPUID specification" rev 2.18<ref>AMD, [https://kib.kiev.ua/x86docs/AMD/AMD-CPUID-Spec/25481-r2.18.pdf CPUID specification], publication #25481, revision 2.18, jan 2006, page 18.</ref> and later, only lists the bit as reserved.</p><p>In rev 2.30<ref>AMD, [https://kib.kiev.ua/x86docs/AMD/AMD-CPUID-Spec/25481-r2.34.pdf CPUID specification], publication #25481, revision 2.34, sep 2010, pages 5 and 11.</ref> and later, a different bit is listed as reserved for hypervisor use: {{nowrap|1=CPUID.(EAX=1):ECX[bit 31].}}</p>}}
! 8
|-
! 31:9
| style="text-align:center; background:lightgrey;" | ''(reserved)''
! 31:9
|}
{{vpad}}

{| class="wikitable"
|+ CPUID EAX=8000'000Ah: SVM feature flags in EDX
! rowspan=2 | Bit 
! colspan=2 | EDX 
|-
! Short || Feature
|-
! 0
| NP || Rapid Virtualization Indexing ([[Second Level Address Translation|Nested Paging]])
|-
! 1
| LbrVirt || LBR (Last Branch Records) virtualization
|-
! 2
| SVML || SVM-Lock
|-
! 3
| NRIPS || nRIP (next sequential instruction pointer) save on #VMEXIT supported
|-
! 4
| TscRateMsr || MSR-based [[Time Stamp Counter|TSC]] rate control (MSR <code>C000_0104h</code>)
|-
! 5
| VmcbClean || VMCB (Virtual Machine Control Block) clean bits supported
|-
! 6
| FlushByAsid || [[Translation lookaside buffer|TLB]] flush events (e.g. [[Control register#CR3|CR3]] writes, CR4.PGE toggles) only flush the TLB entries of the current ASID (address space ID)
|-
! 7
| DecodeAssist || Decode assists supported
|-
! 8
| PmcVirt || PMC (Performance Monitoring Counters) virtualization
|-
! 9
| style="background:lightgrey;"| ''(SseIsa10Compat)''{{efn|text=EDX bit 9 is briefly listed in some older revisions of AMD's document #25481 "CPUID Specification", and is set only in some AMD [[Engineering:Bobcat (microarchitecture)|Bobcat]] CPUs.<ref>Instlatx64, [http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0500F10_K14_Bobcat_CPUID.txt AMD E-350 CPUID dump] - has CPUID.(EAX=8000000A):EDX[9] set.</ref><p>Rev 2.28 of #25481 lists the bit as "Ssse3Sse5Dis"<ref>AMD, [https://kib.kiev.ua/x86docs/AMD/AMD-CPUID-Spec/25481-r2.28.pdf CPUID specification], publication #25481, revision 2.28, apr 2008, page 21.</ref> - in rev 2.34, it is listed as having been removed from the spec at rev 2.32 under the name "SseIsa10Compat".<ref>AMD, [https://kib.kiev.ua/x86docs/AMD/AMD-CPUID-Spec/25481-r2.34.pdf CPUID specification], publication #25481, revision 2.34, sep 2010, page 5 - lists "SseIsa10Compat" as having been dropped in November 2009.</ref></p>}} 
| style="text-align:center; background:lightgrey;"| ''(reserved)''
|-
! 10
| PauseFilter || <code>PAUSE</code> intercept filter supported
|-
! 11
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
|-
! 12
| PauseFilter&shy;Threshold || <code>PAUSE</code> filter cycle count threshold supported
|-
! 13
| AVIC || AMD Advanced Virtualized Interrupt Controller supported
|-
! 14
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
|-
! 15
| VMSAVEvirt || <code>VMSAVE</code> and <code>VMLOAD</code> virtualization
|-
! 16
| VGIF || Global Interrupt Flag (GIF) virtualization
|-
! 17
| GMET || Guest Mode Execution Trap
|-
! 18
| x2AVIC || x2APIC mode supported for AVIC
|-
! 19
| SSSCheck || SVM Supervisor [[Shadow stack|shadow stack]] restrictions
|-
! 20
| SpecCtrl || <code>SPEC_CTRL</code> (MSR <code>2E0h</code>) virtualization
|-
! 21
| ROGPT || Read-Only Guest Page Table supported
|-
! 22
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
|-
! 23
| HOST_MCE_&shy;OVERRIDE || Guest mode [[Machine-check exception]]s when host <code>[[Control register#CR4|CR4.MCE]]=1</code> and guest <code>CR4.MCE=0</code> cause intercepts instead of shutdowns
|-
! 24
| TlbiCtl || <code>INVLPGB</code>/<code>TLBSYNC</code> hypervisor enable in VMCB and <code>TLBSYNC</code> intercept support
|-
! 25
| VNMI || NMI (Non-Maskable interrupt) virtualization
|-
! 26
| IbsVirt || IBS (Instruction-Based Sampling) virtualization
|-
! 27
| ExtLvtOffset&shy;FaultChg || Read/Write fault behavior for extended LVT offsets (APIC addresses <code>0x500-0x530</code>) changed to Read Allowed, Write #VMEXIT<ref name="amd_56713">AMD, [https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip PPR for AMD Family 19h Model 61h, Revision B1 processors], document no. 56713, rev 3.05, mar 8 2023, page 102. [https://web.archive.org/web/20230425231817/https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip Archived] on Apr 25, 2023.</ref> 
|-
! 28
| VmcbAddr&shy;ChkChg || VMCB address check change<ref name="amd_56713"/>
|-
! 29
| BusLock&shy;Threshold || Bus Lock Threshold
|-
! 30
| IdleHlt&shy;Intercept || Idle HLT (<code>HLT</code> instruction executed while no virtual interrupt is pending) intercept
|-
! 31
| Enhanced&shy;Shutdown&shy;Intercept || Support for EXITINFO1 on shutdown intercept, and nested shutdown intercepts will result in a non-interceptible shutdown.<ref name="amd_zen5_ppr"/>
|}
{{notelist}}

{{vpad}}

== EAX=8000'001Fh: Encrypted Memory Capabilities ==
{| class="wikitable"
|+ CPUID EAX=8000'001Fh: Encrypted Memory feature bits in EAX
! rowspan=2 | Bit 
! colspan=2 | EAX 
|-
! Short || Feature
|-
! 0
| SME || Secure Memory Encryption
|-
! 1
| SEV/<br/>CSV
|
* AMD: Secure Encrypted Virtualization
* Hygon: China Secure Virtualization (1st generation)<ref name=hygon_virt>OpenAnolis cloud kernel 6.6 documentation, [https://gitee.com/anolis/cloud-kernel/raw/devel-6.6/Documentation/arch/x86/hygon-secure-virtualization.rst Hygon Secure Virtualization]. [https://web.archive.org/web/20260312192853/https://gitee.com/anolis/cloud-kernel/raw/devel-6.6/Documentation/arch/x86/hygon-secure-virtualization.rst Archived] on 12 Mar 2026.</ref>
|-
! 2
| PageFlushMSR || Page flush MSR (<code>C001_011Eh</code>) supported
|-
! 3
| SEV-ES/<br/>CSV2&nbsp;(Hygon)
|
* AMD: SEV Encrypted State
* Hygon: China Secure Virtualization (2nd generation)<ref name=hygon_virt/>
|-
! 4
| SEV-SNP || SEV Secure Nested Paging
|-
! 5
| VMPL || VM Privilege Levels
|-
! 6
| RMPQUERY || <code>RMPQUERY</code> instruction supported
|-
! 7
| VmplSSS || VMPL Supervisor [[Shadow stack|shadow stack]] supported
|-
! 8
| SecureTSC || Secure [[Time Stamp Counter|TSC]] supported
|-
! 9
| TscAux&shy;Virtualization || Virtualization of <code>TSC_AUX</code> MSR (<code>C000_0103</code>) supported
|-
! 10
| HwEnfCacheCoh || Hardware cache coherency across encryption domains enforced
|-
! 11
| 64BitHost || SEV Guest execution only allowed from 64-bit host
|-
! 12
| Restricted&shy;Injection || SEV-ES guests can refuse all event-injections except #HV (Hypervisor Injection Exception)
|-
! 13
| Alternate&shy;Injection || SEV-ES guests can use an encrypted VMCB field for event-injection
|-
! 14
| DebugVirt || Full debug state virtualization supported for SEV-ES and SEV-SNP guests
|-
! 15
| PreventHostIBS || Prevent host IBS for a SEV-ES guest
|-
! 16
| VTE || Virtual Transparent Encryption for SEV
|-
! 17
| Vmgexit&shy;Parameter || <code>VMGEXIT</code> parameter is supported (using the RAX register)
|-
! 18
| VirtualTomMsr || Virtual TOM (top-of-memory) MSR (<code>C001_0135</code>) supported
|-
! 19
| IbsVirtGuestCtl || IBS virtualization is supported for SEV-ES and SEV-SNP guests
|-
! 20
| PmcVirtGuestCtl || PMC virtualization is supported for SEV-ES and SEV-SNP guests
|-
! 21
| RMPREAD || <code>RMPREAD</code> instruction supported
|-
! 22
| GuestIntercept&shy;Control || Guest Intercept control supported for SEV-ES guests
|-
! 23
| SegmentedRmp || Segmented RMP (Reverse-Map Table) supported
|-
! 24
| VmsaRegProt || VMSA (VM Save Area) register protection supported
|-
! 25
| SmtProtection || [[Simultaneous multithreading|SMT]] Protection supported
|-
! 26
| SecureAvic || Secure AVIC supported
|-
! 27
| AllowedSEV&shy;features || ALLOWED_SEV_FEATURES_MASK field in VMCB (offset <code>138h</code>) supported
|-
! 28
| SVSMComm&shy;PageMSR || SVSM (Secure VM Service Module<ref>AMD, [https://www.amd.com/system/files/TechDocs/58019_1.00.pdf Secure VM Service Module for SEV-SNP Guests], pub.no #58019, rev 1.00, Jul 2023, page 13. [https://web.archive.org/web/20230805094438/https://www.amd.com/system/files/TechDocs/58019_1.00.pdf Archived] on 5 Aug 2023.</ref>) communication page MSR (<code>C001_F000h</code>) supported
|-
! 29
| NestedVirt&shy;SnpMsr || <code>VIRT_RMPUPDATE</code> (<code>C001_F001h</code>) and <code>VIRT_PSMASH</code> (<code>C001_F002h</code>) MSRs supported
|-
! 30
| HvInUse&shy;WrAllowed/<br/>CSV3
|
* AMD: Writes to Hypervisor-owned paged allowed when marked in-use
* Hygon: China Secure Virtualization (3rd generation)<ref name=hygon_virt/>
|-
! 31
| IbpbOnEntry || IBPB on entry to virtual machine supported
|}

{| class="wikitable"
|+ CPUID EAX=8000'001Fh: Encrypted Memory feature information in EBX, ECX and EDX
! Bits 
! EBX
! ECX
! EDX
! Bits
|-
! 5:0
| C-bit (encryption enable bit) location in page table entry
| rowspan="4" style="max-width:18em" | Maximum ASID value that can be used for a SEV-enabled guest (maximum number of encrypted guests that can be supported simultaneously)
| rowspan="4" style="max-width:18em" | Minimum ASID value for a guest that is SEV-enabled but not SEV-ES-enabled
! 5:0
|-
! 11:6 
| Physical address width reduction when memory encryption is enabled
! 11:6
|-
! 15:12 
| Number of VMPLs (VM Privilege Levels) supported
! 15:12
|-
! 31:16
| style="text-align:center; background:lightgrey;"| ''(reserved)''
! 31:16
|}
{{vpad}}

== EAX=8000'0021h: Extended Feature Identification ==
{| class="wikitable"
|+ CPUID EAX=8000'0021h: Extended feature bits in EAX and ECX
! rowspan=2 | Bit 
! colspan=2 | EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan=34 |
! colspan=2 | ECX
! rowspan=2 | Bit
|-
! Short 
! Feature
! Short
! Feature
|-
! 0
| NoNestedDataBp || Processor ignores nested data breakpoints
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 0
|-
! 1
| FsGsKernelGsBase&shy;NonSerializing || <code>WRMSR</code> to the <code>FS_BASE</code>, <code>GS_BASE</code> and <code>KernelGSBase</code> MSRs is non-serializing<ref name="amd_56713_p116">AMD, [https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip PPR for AMD Family 19h Model 61h, Revision B1 processors], document no. 56713, rev 3.05, mar 8 2023, page 116. [https://web.archive.org/web/20230425231817/https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip Archived] on Apr 25, 2023.</ref> 
| TSA_SQ_NO || If set, then CPU is not vulnerable to {{nowrap|TSA-SQ<ref name="amd-tsa-2025" />}}
! 1
|-
! 2
| LFenceAlways&shy;Serializing || <code>LFENCE</code> is always dispatch serializing
| TSA_L1_NO || If set, then CPU is not vulnerable to {{nowrap|TSA-L1<ref name="amd-tsa-2025" />}}
! 2
|-
! 3
| SmmPgCfgLock || SMM paging configuration lock supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 3
|-
! 4
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 4
|-
! 5
| VERW_CLEAR || <code>VERW</code> instruction can, when executed with a memory operand in Ring 0, be used to clear microarchitectural data buffers to help mitigate TSA (Transient Scheduler Attacks).<ref name="amd-tsa-2025">AMD, [https://www.amd.com/content/dam/amd/en/documents/resources/bulletin/technical-guidance-for-mitigating-transient-scheduler-attacks.pdf Technical Guidance For Mitigating Transient Scheduler Attacks], rev 2.0, July 2025, page 3. [https://web.archive.org/web/20250814161211/https://www.amd.com/content/dam/amd/en/documents/resources/bulletin/technical-guidance-for-mitigating-transient-scheduler-attacks.pdf Archived] on 14 Aug 2025.</ref>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 5
|-
! 6
| NullSelect&shy;ClearsBase || Null segment selector loads also clear the destination segment register base and limit
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 6
|-
! 7
| UpperAddress&shy;Ignore || Upper Address Ignore (Version 1) is supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 7
|-
! 8
| AutomaticIBRS || Automatic IBRS
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 8
|-
! 9
| NoSmmCtlMSR || <code>SMM_CTL</code> MSR (<code>C0010116h</code>) is not supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 9
|-
! 10
| FSRS || Fast short {{nowrap|<code>REP STOSB</code>}} supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 10
|-
! 11
| FSRC || Fast short {{nowrap|<code>REPE CMPSB</code>}} supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 11
|-
! 12
| PMC2Precise&shy;Retire || PreciseRetire performance counter control bit (MSR <code>C0010002h</code> bit 43) supported<ref name="amd_zen5_ppr" />
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 12
|-
! 13
| PrefetchCtlMsr || PrefetchControl MSR (<code>C0000108h</code>) is supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 13
|-
! 14
| L2TlbSIzeX32 || If set, L2 TLB sizes (leaf <code>80000006h</code>) are encoded as multiples of 32
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 14
|-
! 15
| AMD_ERMSB || Processor supports AMD implementation of Enhanced {{nowrap|<code>REP MOVSB</code>}} and {{nowrap|<code>REP STOSB</code>}}
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 15
|-
! 16
| OPCODE_0F017_&shy;RECLAIM || Reserves opcode <code>0F 01 /7</code><!--INVLPG instruction?--> for AMD use, returning #UD.<ref name="amd_zen5_ppr">AMD, [https://docs.amd.com/api/khub/documents/fEY1GkRkcoEhenFftZyr8Q/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.24&download=true&locationValue=viewer Processor Programming Reference (PPR) for AMD Family 1Ah Model 70h, Revision B0 Processors], order no. 57930, rev 3.00, 30 Apr 2025, pages 103, 119 and 200. [https://web.archive.org/web/20260119024318/https://docs.amd.com/api/khub/documents/fEY1GkRkcoEhenFftZyr8Q/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.24&download=true&locationValue=viewer Archived] on 19 Jan 2026.</ref>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 16
|-
! 17
| CpuidUserDis || <code>CPUID</code> disable for non-privileged software (#GP)
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 17
|-
! 18
| EPSF || Enhanced Predictive Store Forwarding supported<ref name="amd_56713_p116"/>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 18
|-
! 19
| FAST_REP_SCASB || Fast Short <code>REP SCASB</code> supported
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 19
|-
! 20
| PREFETCHI || Instruction Cache prefetch instructions <code>PREFETCHIT0</code> and <code>PREFETCHIT1</code> supported{{efn|1=On Intel processors, support for the instruction-cache prefetch instructions is not indicated by {{nowrap|1=<code>CPUID.(EAX=8000_0021h):EAX[20]</code>}} but instead by {{nowrap|1=<code>CPUID.(EAX=7,ECX=1):EDX[14]</code>.}}}}
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 20
|-
! 21
| FP512_&shy;DOWNGRADE || Downgrade of 512-bit datapath to 256-bit supported.{{efn|text=If the downgrade from 512-bit to 256-bit datapath is enabled, then AVX-512 instructions that work on 512-bit data items will be split into two 256-bit parts that will be issued over two consecutive cycles. This datapath downgrade can help improve power efficiency for some workloads.<ref>AMD, [https://www.amd.com/content/dam/amd/en/documents/epyc-business-docs/white-papers/5th-gen-amd-epyc-processor-architecture-white-paper.pdf 5th Gen AMD EPYC Processor Architecture], First Edition, October 2024, page 9. [https://web.archive.org/web/20241228165850/https://www.amd.com/content/dam/amd/en/documents/epyc-business-docs/white-papers/5th-gen-amd-epyc-processor-architecture-white-paper.pdf Archived] on 28 Dec 2024.</ref>}}
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 21
|-
! 22
| WL_CLASS_&shy;SUPPORT || Support for workload-based heuristic feedback to OS for scheduling decisions<ref name="amd_zen5_ppr" />
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 22
|-
! 23
| AVX512_BMM || AVX-512 Bit Matrix Multiply and Bit Reverse instructions<ref>Binutils mailing list, [https://sourceware.org/pipermail/binutils/2025-November/145449.html &#91;PATCH&#93; Add AMD znver6 processor support], 7 Nov 2025.</ref><ref>AMD, [https://docs.amd.com/api/khub/documents/6upFnELfPCe3I15dmTr~0w/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.41&download=true&locationValue=viewer AMD64 Bit Matrix Multiply and Bit Reversal Instructions], pub.no. 69192, rev 1.00, 30 Jan 2026. [https://web.archive.org/web/20260227055323/https://docs.amd.com/api/khub/documents/6upFnELfPCe3I15dmTr~0w/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.41&download=true&locationValue=viewer Archived] on 27 Feb 2026.</ref>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 23
|-
! 24
| ERAPS || Enhanced Return Address Predictor Security (see also EBX[23:16] "RapSize")
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 24
|-
! 25
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 25
|-
! 26
| UpperAddress&shy;Ignore2 || Upper Address Ignore (Version 2) is supported<ref>AMD, [https://docs.amd.com/api/khub/documents/5t7QZnTuqL_0UAYGwkMUYg/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.48&download=true&locationValue=viewer AMD64 Upper Address Ignore Version 2], pub.no. 69207, rev 1.00, 10 Mar 2026. [https://web.archive.org/web/20260311174826/https://docs.amd.com/api/khub/documents/5t7QZnTuqL_0UAYGwkMUYg/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.48&download=true&locationValue=viewer Archived] on 11 Mar 2026.</ref>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 26
|-
! 27
| SBPB || Selective Branch Predictor Barrier supported<ref name="amd_srso">AMD, [https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf Technical Update Regarding Speculative Return Stack Overflow], rev 2.0, feb 2024. [https://web.archive.org/web/20240412225347/https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf Archived] on Apr 12, 2024.</ref>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 27
|-
! 28
| IBPB_BRTYPE || IBPB flushes all branch type predictions<ref name="amd_srso"/>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 28
|-
! 29
| SRSO_NO || CPU is not subject to SRSO (Speculative Return Stack Overflow) vulnerability<ref name="amd_srso"/>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 29
|-
! 30
| SRSO_USER_&shy;KERNEL_NO || CPU is not subject to SRSO vulnerability across user/kernel boundary<ref name="amd_srso"/>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 30
|-
! 31
| SRSO_MSR_FIX || SRSO can be mitigated by setting bit 4 of BP_CFG (<code>MSR C001_102E</code>)<ref name="amd_srso"/>
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 31
|}
{{notelist}}

{| class="wikitable"
|+ CPUID EAX=8000'0021h: Extended feature information in EBX
!rowspan=2| Bits ||colspan=2| EBX 
|-
! Short || Feature
|-
! 15:0
| Microcode&shy;PatchSize || The size of the Microcode patch in 16-byte multiples. If 0, the size of the patch is at most 5568 (15C0h) bytes
|-
! 23:16
| RapSize || Return Address Predictor Size.<br/>RapSize * 8 is the minimum number of <code>CALL</code> instructions without matching <code>RET</code> instructions that are needed to flush the Return Address Predictor.
|-
! 31:24
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
|}
{{vpad}}

== EAX=8000'0025h: Encrypted Memory Capabilities 2 ==
{| class="wikitable"
|+ CPUID EAX=8000'0025h: Encrypted memory feature information in EAX, EBX and EDX
! rowspan=2 | Bits
! colspan=2 | EAX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan=10 |
! colspan=2 | EBX
! scope="col" style="width: 0.5em; border-spacing:0; padding:0px" rowspan=10 |
! colspan=2 | EDX
! rowspan=2 | Bits
|-
! Short 
! Feature
! Short
! Feature
! Short
! Feature
|-
! 0
| rowspan=4 | MinRmp&shy;SegSize || rowspan=4 | Minimum supported RMP Segment Size
| rowspan=5 | NumCached&shy;Segments || rowspan=5 | Number of cached RMP segment definitions
| RmpOpt || <code>RMPOPT</code> instruction<ref>AMD, [https://docs.amd.com/api/khub/documents/pVy9DHmRU6S3gKD2150uhg/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.41&download=true&locationValue=viewer AMD64 RMPOPT], pub.no. 69201, rev 1.00, Feb 2026. [https://web.archive.org/web/20260226105644/https://docs.amd.com/api/khub/documents/pVy9DHmRU6S3gKD2150uhg/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.41&download=true&locationValue=viewer Archived] on 26 Feb 2026.</ref>
! 0
|-
! 1
| EnhSmt&shy;Protection || Enhanced SMT Protection<ref>AMD, [https://docs.amd.com/api/khub/documents/NonbFzm036g3YcW2EvrruQ/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.54&download=true&locationValue=viewer AMD64 Enhanced SMT Protection], pub.no. 69204, rev 1.00, Mar 2026. [https://web.archive.org/web/20260329174443/https://docs.amd.com/api/khub/documents/NonbFzm036g3YcW2EvrruQ/content?Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.54&download=true&locationValue=viewer Archived] on 29 Mar 2026.</ref>
! 1
|-
! 2
| RmpDirty || RMP Dirty feature and <code>RMPCHKD</code> instruction<ref>AMD, [https://docs.amd.com/api/khub/documents/dSDYo9rxWwNDSJkmMJCxYQ/content?download=true&Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.41&locationValue=search AMD64 RMP Dirty], pub.no. 69203, rev 1.00, Feb 2026. [https://web.archive.org/web/20260225085001/https://docs.amd.com/api/khub/documents/dSDYo9rxWwNDSJkmMJCxYQ/content?download=true&Ft-Calling-App=ft%2Fturnkey-portal&Ft-Calling-App-Version=5.2.41&locationValue=search Archived] on 25 Feb 2026.</ref>
! 2
|-
! 5:3
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 5:3
|-
! 9:6
| rowspan=3 | MaxRmp&shy;SegSize || rowspan=3 | Maximum supported RMP Segment Size
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 9:6
|-
! 10
| NumSegReduction || Number of RMP segments is reduced
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 10
|-
! 11
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! 11
|-
! <br/>31:12<br/>&nbsp;
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
! <br/>31:12<br/>&nbsp;
|}
{{vpad}}

== EAX=8C86'0000h: Hygon Extended Feature Flags ==
Returns index of highest Hygon feature leaf in EAX (valid if greater than or equal to <code>8C860000h</code>),<ref>OpenEuler kernel 6.6, [https://github.com/chenglongshe/openEuler/blob/OLK-6.6/arch/x86/kernel/cpu/hygon.c#L255 arch/x86/kernel/cpu/hygon.c, line 255]. [https://web.archive.org/web/20260314003003/https://github.com/chenglongshe/openEuler/blob/OLK-6.6/arch/x86/kernel/cpu/hygon.c#L255 Archived] on 14 mar 2026.</ref> and Hygon feature flags in EDX.<ref>OpenEuler kernel 6.6, [https://github.com/chenglongshe/openEuler/blob/OLK-6.6/arch/x86/include/asm/cpufeatures.h#L499 arch/x86/include/asm/cpufeatures.h, line 499]. [https://web.archive.org/web/20260314002844/https://github.com/chenglongshe/openEuler/blob/OLK-6.6/arch/x86/include/asm/cpufeatures.h#L499 Archived] on 14 Mar 2026.</ref>
{| class="wikitable"
|+ CPUID EAX=8C86'0000h: Hygon feature flags in EDX
! rowspan=2 | Bits
! colspan=2 | EDX
|-
! Short 
! Feature
|-
! 0
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
|-
! 1
| sm3 || Hygon SM3 instructions
|-
! 2
| sm4 || Hygon SM4 instructions
|-
! <br/>31:3<br/>&nbsp;
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
|}
{{vpad}}

== EAX=8FFF'FFFEh and EAX=8FFF'FFFFh: AMD Easter Eggs ==
Several AMD CPU models will, for CPUID with <code>EAX=8FFF'FFFFh</code>, return an [[Easter egg (media)|Easter egg]] string in EAX, EBX, ECX and EDX.<ref>{{cite web|last1=Ferrie|first1=Peter|title=Attacks on Virtual Machine Emulators|url=http://www.symantec.com/avcenter/reference/Virtual_Machine_Threats.pdf|website=[[Company:Broadcom#Symantec enterprise security|Symantec]]|publisher=Symantec Advanced Threat Research|access-date=15 March 2017|archive-url=https://web.archive.org/web/20070207103157/http://www.symantec.com/avcenter/reference/Virtual_Machine_Threats.pdf|archive-date=2007-02-07}}</ref><ref>Sandpile, [https://sandpile.org/x86/cpuid.htm#level_C000_0001h x86 architecture CPUID]. Retrieved 22 December 2022.</ref> Known Easter Egg strings include:
{| class="wikitable"
! Processor !! String
|-
| [[Engineering:AMD K6|AMD K6]] || <code>[[Company:NexGen|NexGen]]&zwj;erationAMD</code>
|-
| [[Engineering:AMD K8|AMD K8]] || <code>IT'S HAMMER TIME</code>
|-
| [[Engineering:Jaguar (microarchitecture)|AMD Jaguar]]<ref>instlatx64, [http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0700F01_K16_Kabini_CPUID.txt CPUID dump of AMD A4-5000], lists "HELLO KITTY" string for CPUID leaf <code>8FFFFFFFh</code>. Retrieved 22 December 2022.</ref> || <code>HELLO KITTY! ^-^</code>
|}

Additionally, [[Engineering:AMD K6|AMD K6]] CPUs will, for CPUID with <code>EAX=8FFF'FFFEh</code>, return an [[Easter egg (media)|Easter egg]] reference to "DEI" in EAX.<ref>Sandpile, [https://sandpile.org/x86/cpuid.htm#level_C000_0001h x86 architecture CPUID]. Retrieved 30 July 2025.</ref>
{{vpad}}

== EAX=C000'0000h: Highest [[Company:Centaur Technology|Centaur]] Extended Function ==
Returns index of highest Centaur leaf in EAX. If the returned value in EAX is less than <code>C0000001h</code>, then Centaur extended leaves are not supported.

Present in CPUs from [[Company:VIA Technologies|VIA]] and [[Company:Zhaoxin|Zhaoxin]].

On IDT WinChip CPUs (<code>CentaurHauls</code> Family 5), the extended leaves <code>C0000001h-C0000005h</code> do not encode any Centaur-specific functionality but are instead aliases of leaves <code>80000001h-80000005h</code>.<ref>IDT, [https://www.ardent-tool.com/CPU/docs/IDT_Centaur/WinChip2/w2b_datasheet.pdf WinChip 2B Processor Data Sheet], v0.9, April 1999, chapter 3.3.3, page 31.</ref>

== EAX=C000'0001h: Centaur Feature Information ==
This leaf returns Centaur feature information (mainly [[VIA PadLock|VIA/Zhaoxin PadLock]]) in EDX.<ref>VIA, [https://web.archive.org/web/20100526054140/http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261 PadLock Programming Guide] rev. 1.66, aug 4, 2005, page 5. Archived from the [http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261 original] on May 26, 2010</ref><ref>OpenEuler 1.0 LTS kernel sources, [https://gitee.com/openeuler/kernel/blob/openEuler-1.0-LTS/arch/x86/include/asm/cpufeatures.h#L147 /arch/x86/include/asm/cpufeatures.h] lines 147-178. [https://web.archive.org/web/20230730113626/https://gitee.com/openeuler/kernel/blob/openEuler-1.0-LTS/arch/x86/include/asm/cpufeatures.h Archived] on Jul 30, 2023.</ref><ref>Zhaoxin, [https://web.archive.org/web/20250315101352/https://www.zhaoxin.com/Admin/Others/DownloadsPage.aspx?nid=31&id=3202&tag=0&ref=kfzzc&t=b3f041e6f23d9f48 Padlock instruction set reference], 26 Dec 2024. Archived from the [https://www.zhaoxin.com/Admin/Others/DownloadsPage.aspx?nid=31&id=3202&tag=0&ref=kfzzc&t=b3f041e6f23d9f48 original] on 15 Mar 2025.</ref><ref>Zhaoxin, [https://web.archive.org/web/20250315101213/https://www.zhaoxin.com/Admin/Others/DownloadsPage.aspx?nid=31&id=3152&tag=0&ref=kfzzc&t=32531cd65e657254 GMI reference], 26 Dec 2024. Archived from the [https://www.zhaoxin.com/Admin/Others/DownloadsPage.aspx?nid=31&id=3152&tag=0&ref=kfzzc&t=32531cd65e657254 original] on 15 Mar 2025.</ref> (EAX, EBX and ECX are reserved.)
{| class="wikitable"
|+ CPUID EAX=C000'0001h: Centaur feature bits in EDX
! rowspan=2 | Bit 
! colspan=2 | EDX
|-
! Short 
! Feature
|-
! 0
| sm2{{efn|name=nehemiah_special|text=On VIA [[Engineering:VIA C3#Nehemiah cores|Nehemiah]] and Antaur CPUs (<code>CentaurHauls</code> Family 6 Model 9 only),<ref>VIA, [http://datasheets.chipdb.org/VIA/Nehemiah/VIA%20C3%20Nehemiah%20Datasheet%20R113.pdf C3 Nehemiah Processor Datasheet], rev 1.13, Sep 29, 2004, page 21</ref> bits 0,1,4,5 are used differently:
* Bit 0: Alternate Instruction Set (AIS) present
* Bit 1: AIS enabled
* Bit 4: [[Engineering:LongHaul|LongHaul]] MSR (MSR <code>0x110A</code>) present
* Bit 5: <code>[[Engineering:3DNow!|FEMMS]]</code> instruction (opcode {{nowrap|<code>0F 0E</code>}}) present
}}
 || GMI <code>[[SM9 (cryptography standard)|SM2]]</code> instruction present
|-
! 1
| sm2_en{{efn|name=nehemiah_special}} || SM2 enabled
|-
! 2
| rng || PadLock [[Random number generation|RNG]] present: <code>XSTORE</code> and {{nowrap|<code>REP XSTORE</code>}} instructions
|-
! 3
| rng_en || RNG enabled
|-
! 4
| ccs{{efn|name=nehemiah_special}} || GMI [[SM3 (hash function)|SM3]]/SM4 instructions present: <code>CCS_HASH</code> and <code>CCS_ENCRYPT</code>
|-
! 5
| ccs_en{{efn|name=nehemiah_special}} || SM3/SM4 instructions enabled
|-
! 6
| xcrypt || PadLock Advanced Cryptographic Engine (ACE, using [[Advanced Encryption Standard|AES]] cipher) present: {{nowrap|<code>REP XCRYPT(ECB,CBC,CFB,OFB)</code>}} instructions
|-
! 7
| xcrypt_en || ACE enabled
|-
! 8
| ace2 || ACE v2 present: {{nowrap|<code>REP XCRYPTCTR</code>}} instruction, as well as support for digest mode and misaligned data for ACE's {{nowrap|<code>REP XCRYPT*</code>}} instructions.
|-
! 9
| ace2_en || ACE v2 enabled
|-
! 10
| phe || PadLock Hash Engine (PHE): {{nowrap|<code>REP XSHA1</code>}} and {{nowrap|<code>REP XSHA256</code>}} instructions
|-
! 11
| phe_en || PHE enabled
|-
! 12
| pmm || PadLock [[Montgomery modular multiplication|Montgomery Multiplier]] (PMM): {{nowrap|<code>REP MONTMUL</code>}} instruction
|-
! 13
| pmm_en || PMM enabled
|-
! 14
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''<!-- used for unknown purpose on VIA Esther CPUs -->
|-
! 15
| zx_fma || FMA supported<!-- defined but not observed to have been set on any Zhaoxin CPU, used for unknown purpose on VIA Esther CPUs -->
|-
! 16
| parallax || Adaptive [[ACPI#Performance state|P-state]] control present
|-
! 17
| parallax_en || Adaptive P-state control enabled
|-
! 18
| overstress || Overstress feature for auto overclock present
|-
! 19
| overstress_en || Overstress feature for auto overclock enabled
|-
! 20
| tm3 || Thermal Monitor 3 present<!-- defined but not observed to have been set on any CPU -->
|-
! 21
| tm3_en || Thermal Monitor 3 enabled
|-
! 22
| rng2 || RNG v2 - second generation RNG present: <code>REP XRNG2</code> instruction
|-
! 23
| rng2_en || RNG v2 enabled
|-
! 24
| sme || SME feature present<!-- defined but not observed to have been set on any CPU -->
|-
! 25
| phe2 || PHE v2: SHA384 and SHA512 present
|-
! 26
| phe2_en || PHE v2 enabled
|-
! 27
| xmodx || RSA instructions present: <code>XMODEXP</code> and <code>MONTMUL2</code> instructions
|-
! 28
| xmodx_en || RSA instructions enabled
|-
! 29
| vex || VEX instructions present<!-- defined but not observed to have been set on any CPU -->
|-
! 30
| vex_en || VEX instructions enabled
|-
! 31
| stk || STK is present<!-- defined but not observed to have been set on any CPU -->
|}
{{notelist}}

== EAX=C000'0006h, ECX=0: Zhaoxin Feature Information ==
This sub-leaf returns feature information in EAX. EBX, ECX and EDX are reserved.
{| class="wikitable"
|+ CPUID EAX=C000'0006h, ECX=0: Zhaoxin feature bits in EAX
! rowspan=2 | Bit 
! colspan=2 | EAX
|-
! Short 
! Feature
|-
! 0
| pauseopt || <code>PAUSEOPT</code> instruction<ref>Zhaoxin, [https://www.zhaoxin.com/Admin/Others/DownloadsPage.aspx?nid=31&id=3728&tag=0&ref=kfzzc&pre=1&t=b8302d53a83ad24e PAUSEOPT 指令说明], section 3.1.1 (in Chinese), rev 1.0.0, 13 Aug 2024. [https://web.archive.org/web/20260114020345/https://www.zhaoxin.com/Admin/Others/DownloadsPage.aspx?nid=31&id=3728&tag=0&ref=kfzzc&pre=1&t=b8302d53a83ad24e Archived] on 14 Jan 2026.</ref>
|-
! 31:1
| colspan="2" style="text-align:center; background:lightgrey;"| ''(reserved)''
|}

== CPUID usage from high-level languages ==

=== Inline assembly ===
This information is easy to access from other languages as well. For instance, the C code for gcc below prints the first five values, returned by the cpuid:

<syntaxhighlight lang="c">
#include <stdio.h>
#include <cpuid.h>

int main()
{
    unsigned int i, eax, ebx, ecx, edx;

    for (i = 0; i < 5; i++) {
        __cpuid(i, eax, ebx, ecx, edx);
        printf ("InfoType %x\nEAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", i, eax, ebx, ecx, edx);
    }

    return 0;
}

</syntaxhighlight>

In MSVC and Borland/Embarcadero C compilers (bcc32) flavored inline assembly, the clobbering information is implicit in the instructions:

<syntaxhighlight lang="c">
#include <stdio.h>

int main()
{
    unsigned int a, b, c, d, i = 0;

    __asm {
        /* Do the call. */
        mov EAX, i;
        cpuid;
        /* Save results. */
        mov a, EAX;
        mov b, EBX;
        mov c, ECX;
        mov d, EDX;
    }

    printf ("InfoType %x\nEAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", i, a, b, c, d);
    return 0;
}

</syntaxhighlight>

If either version was written in plain assembly language, the programmer must manually save the results of EAX, EBX, ECX, and EDX elsewhere if they want to keep using the values.

=== Wrapper functions ===

GCC also provides a header called <code>&lt;cpuid.h&gt;</code> on systems that have CPUID. The <code>__cpuid</code> is a macro expanding to inline assembly. Typical usage would be:
<syntaxhighlight lang="c">
#include <stdio.h>
#include <cpuid.h>

int main()
{
    unsigned int eax, ebx, ecx, edx;

    __cpuid(0 /* vendor string */, eax, ebx, ecx, edx);
    printf("EAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", eax, ebx, ecx, edx);

    return 0;
}

</syntaxhighlight>
But if one requested an extended feature not present on this CPU, they would not notice and might get random, unexpected results. Safer version is also provided in <code>&lt;cpuid.h&gt;</code>. It checks for extended features and does some more safety checks. The output values are not passed using reference-like macro parameters, but more conventional pointers.

<syntaxhighlight lang="c">
#include <stdio.h>
#include <cpuid.h>

int main()
{
    unsigned int eax, ebx, ecx, edx;

    /* 0x81234567 is nonexistent, but assume it exists */
    if (!__get_cpuid (0x81234567, &eax, &ebx, &ecx, &edx)) {
        printf("Warning: CPUID request 0x81234567 not valid!\n");
        return 1;
    }

    printf("EAX: %x\nEBX: %x\nECX: %x\nEDX: %x\n", eax, ebx, ecx, edx);

    return 0;
}

</syntaxhighlight>

Notice the ampersands in <code>&amp;a, &amp;b, &amp;c, &amp;d</code> and the conditional statement. If the <code>__get_cpuid</code> call receives a correct request, it will return a non-zero value, if it fails, zero.<ref>{{Cite web|url=https://github.com/gcc-mirror/gcc/blob/master/gcc/config/i386/cpuid.h|title=GCC-mirror/GCC|website=[[GitHub]]|date=13 March 2022}}</ref>

Microsoft Visual C compiler has builtin function <code>__cpuid()</code> so the cpuid instruction may be embedded without using inline assembly, which is handy since the x86-64 version of MSVC does not allow inline assembly at all. The same program for MSVC would be:

<syntaxhighlight lang="cpp">
#include <stdio.h>
#ifdef _MSC_VER
    #include <intrin.h>
#endif

int main()
{
    unsigned int regs[4];
    int i;

    for (i = 0; i < 4; i++) {
        __cpuid(regs, i);
        printf("The code %d gives %d, %d, %d, %d", regs[0], regs[1], regs[2], regs[3]);
    }

    return 0;
}

</syntaxhighlight>

Many interpreted or compiled scripting languages are capable of using CPUID via an [[Foreign function interface|FFI]] library. [https://web.archive.org/web/20150429190703/http://www.cstrahan.com/posts/pure-ruby-cpuid-via-ffi.html One such implementation] shows usage of the Ruby FFI module to execute assembly language that includes the CPUID opcode.

[[.NET|.NET]] 5 and later versions provide the <code>System.Runtime.Intrinsics.X86.X86base.CpuId</code> method. For instance, the C# code below prints the processor brand if it supports CPUID instruction:<syntaxhighlight lang="c#">
using System.Runtime.InteropServices;
using System.Runtime.Intrinsics.X86;
using System.Text;

namespace X86CPUID {
    class CPUBrandString {
        public static void Main(string[] args) {
            if (!X86Base.IsSupported) {
                Console.WriteLine("Your CPU does not support CPUID instruction.");
            } else {
                Span<int> raw = stackalloc int[12];
             (raw[0], raw[1], raw[2], raw[3]) = X86Base.CpuId(unchecked((int)0x80000002), 0);
             (raw[4], raw[5], raw[6], raw[7]) = X86Base.CpuId(unchecked((int)0x80000003), 0);
             (raw[8], raw[9], raw[10], raw[11]) = X86Base.CpuId(unchecked((int)0x80000004), 0);

                Span<byte> bytes = MemoryMarshal.AsBytes(raw);
                string brand = Encoding.UTF8.GetString(bytes).Trim();
                Console.WriteLine(brand);
            }
        }
    }
}

</syntaxhighlight>

== CPU-specific information outside x86 ==
Some of the non-x86 CPU architectures also provide certain forms of structured information about the processor's abilities, commonly as a set of special registers:

* [[ARM architecture]]s have a <code>CPUID</code> coprocessor register which requires [[Protection ring|exception level]] EL1 or above to access.<ref>{{cite web|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0395b/CIHCAGHH.html |title=ARM Information Center |publisher=Infocenter.arm.com |access-date=2013-04-11}}</ref>
* System/370 through z/Architecture IBM mainframe processors have a supervisor-mode-only ''Store CPU ID'' (<code>STIDP</code>) instruction, which provides information that includes the CPU type.<ref>{{cite book |url=https://bitsavers.org/pdf/ibm/370/princOps/GA22-7000-0_370_Principles_Of_Operation_Jun70.pdf |title=IBM System/370 Principles Of Operation |edition=First |page=29 |publisher=IBM |date=June 1970 |id=GA22-7000-0}}</ref><ref name="z/architecture princops">{{cite book |url=https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf |title=z/Architecture Principles of Operation |edition=Fourteenth |date=May 2022 |id=SA22-7832-13}}</ref>{{rp||pages=10{{hyp}}147-10{{hyp}}149}}
* The z/Architecture mainframe processors also have a supervisor-mode-only ''Store Facilities List'' (<code>STFL</code>)<ref name="z/architecture princops" />{{rp|page=10{{hyp}}149}} instruction, and a non-privileged ''Store Facilities List Extended'' (<code>STFLE</code>) instruction,{{rp||pages=7{{hyp}}394–7{{hyp}}395}} which list the installed hardware features.
* The [[MIPS architecture|MIPS32/64]] architecture defines a mandatory ''Processor Identification'' (<code>PrId</code>) and a series of daisy-chained ''Configuration Registers''.<ref>{{cite web|url=https://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol3.pdf | title=MIPS32 Architecture For Programmers, Volume III: The MIPS32 Privileged Resource Architecture|date=2001-03-12|publisher=MIPS Technologies, Inc.}}</ref>
* The [[PowerPC]] processor has the 32-bit read-only ''Processor Version Register'' (<code>PVR</code>) identifying the processor model in use. The instruction requires supervisor access level.<ref>{{cite web|url=http://moss.csc.ncsu.edu/~mueller/cluster/ps3/SDK3.0/docs/arch/PPC_Vers202_Book3_public.pdf | title=PowerPC Operating Environment Architecture, book III}}</ref>
* The [[Engineering:RISC-V|RISC-V]] architecture has an <code>mcpuid</code> "read-only register containing information regarding the capabilities of the CPU implementation"<ref>{{cite web|url=https://people.eecs.berkeley.edu/~krste/papers/riscv-priv-spec-1.7.pdf#page=23|at=section 3.1.1|title=The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.7|date=May 9, 2015}}</ref>


== See also ==
* [https://www.sandpile.org/x86/cpuid.htm sandpile.org], the world's leading source for technical x86 processor information
* [https://x86-cpuid.org/ x86-cpuid.org], a complete x86 architecture CPUID database plus related code generation tools, to be used by both the [[Software:Linux kernel|Linux Kernel]] and the Xen hypervisor.<ref>{{cite web |last1=S. Darwish |first1=Ahmed |title=[ANNOUNCE] x86-cpuid.org: A machine-readable CPUID repository |url=https://lore.kernel.org/lkml/ZpkckA2SHa1r3Bor@lx-t490 |website=Linux Kernel Mailing List archive |access-date=20 July 2024}}</ref>
* [[Software:CPU-Z|CPU-Z]], a Windows utility that uses <code>CPUID</code> to identify various system settings
* [https://thetumultuousunicornofdarkness.github.io/CPU-X/ CPU-X], an alternative of CPU-Z for Linux and FreeBSD
* [[Spectre (security vulnerability)]]
* [[Speculative Store Bypass]] (SSB)
* [[Cpuinfo|{{mono|/proc/cpuinfo}}]], a text file generated by certain systems containing some of the CPUID information

== References ==
{{Reflist}}

== Further reading ==
* {{cite web |title=AMD64 Technology Indirect Branch Control Extension |version=Revision 4.10.18 |date=2018 |type=White paper |publisher=Advanced Micro Devices, Inc. (AMD) |url=https://developer.amd.com/wp-content/resources/Architecture_Guidelines_Update_Indirect_Branch_Control.pdf |access-date=2018-05-09 |url-status=live |archive-url=https://web.archive.org/web/20180509093400/https://developer.amd.com/wp-content/resources/Architecture_Guidelines_Update_Indirect_Branch_Control.pdf |archive-date=2018-05-09}}

== External links ==
* Intel [https://web.archive.org/web/20120625025623/http://www.intel.com/Assets/PDF/appnote/241618.pdf  Processor Identification and the CPUID Instruction] (Application Note 485), last published version. Said to be incorporated into the [http://www.intel.com/Assets/PDF/appnote/241618.pdf Intel 64 and IA-32 Architectures Software Developer's Manual] [https://web.archive.org/web/20130626034554/http://www.intel.com/content/dam/www/public/us/en/documents/application-notes/processor-identification-cpuid-instruction-note.pdf in 2013], but {{As of|July 2014|lc=1}} the manual still directs the reader to note 485.
** Contains some information that can be ''and was'' easily misinterpreted though, particularly with respect to processor topology identification.
** The big Intel manuals tend to lag behind the Intel ISA document, available at the top of [https://software.intel.com/en-us/intel-isa-extensions this page], which is updated even for processors not yet publicly available, and thus usually contains more CPUID bits. For example, as of this writing, the ISA book (at revision 19, dated May 2014) documents the CLFLUSHOPT bit in leaf 7, but the big manuals although apparently more up-to-date (at revision 51, dated June 2014) don't mention it.
* [https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24594.pdf AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions]
* [https://www.etallen.com/cpuid.html cpuid] command-line program for Linux
* [https://skanthak.homepage.t-online.de/cpuid.html cpuprint.com, cpuprint.exe, cpuprint.raw] command-line programs for Windows
* [http://users.atw.hu/instlatx64/ instlatx64] - collection of x86/x64 Instruction Latency, Memory Latency and CPUID dumps

{{Multimedia extensions}}

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[[Category:X86 architecture]]
[[Category:Machine code]]
[[Category:X86 instructions]]

{{Sourceattribution|CPUID}}