View source for Engineering:3DNow!

{{short description|Extension to the x86 instruction set by AMD}}{{Infobox computer hardware
| name         = 3DNow!
| logo         = 3dnow-logo.svg
| image        = 
| caption      = 
| designfirm   = [[Company:Advanced Micro Devices|Advanced Micro Devices]]
| introduced   = 1998
| discontinued = 
| type         = [[Instruction set architecture|instruction set architecture]]
}}
'''3DNow!''' is a deprecated extension to the [[X86|x86]] instruction set developed by [[Company:Advanced Micro Devices|Advanced Micro Devices]] (AMD). It adds [[SIMD|single instruction multiple data]] <!-- astounding that the expansion redirects to the initialism page...meh --> (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of floating-point vector operations using vector registers. This improvement enhances the performance of many graphics-intensive applications. The first microprocessor to implement 3DNow! was the [[Engineering:AMD K6-2|AMD K6-2]], introduced in 1998. In appropriate applications, this enhancement raised the speed by about 2–4 times.<ref>{{cite web |url=http://www.linuxjournal.com/article/3685 |title=Effectively Utilizing 3DNow in Linux |publisher=Linux Journal |date=December 1, 1999 |access-date=2010-10-03 |archive-date=2011-06-07 |archive-url=https://web.archive.org/web/20110607184325/http://www.linuxjournal.com/article/3685 |url-status=live }}</ref>

However, the instruction set never gained much popularity, and AMD announced in August 2010 that support for 3DNow! would be dropped in future AMD processors, except for two instructions (the <code>PREFETCH</code> and <code>PREFETCHW</code> instructions).<ref>{{cite web |url=http://developer.amd.com/2010/08/18/3dnow-deprecated/ |title=3DNow Instructions are Being Deprecated &#124; AMD Developer Central |publisher=Blogs.amd.com |date=2010-08-18 |access-date=2010-10-03 |archive-url=https://web.archive.org/web/20101024174505/http://developer.amd.com/2010/08/18/3dnow-deprecated/ |archive-date=2010-10-24 |url-status=dead }}</ref> These two instructions are also available in Bay-Trail Intel processors.<ref>{{cite web|url=http://wiki.minnowboard.org/IntelE38xx|title=IntelE38xx - MinnowBoard Wiki|access-date=13 February 2017|archive-url=https://web.archive.org/web/20170211075815/http://wiki.minnowboard.org/IntelE38xx|archive-date=11 February 2017|url-status=dead}}</ref>

==History==
3DNow! was developed at a time when 3D graphics were becoming mainstream in PC multimedia and games.  Realtime display of 3D graphics depended heavily on the host CPU's floating-point unit (FPU) to perform floating-point calculations, a task in which AMD's [[Engineering:AMD K6|K6 processor]] was easily outperformed by its competitor, the Intel Pentium II.

As an enhancement to the [[MMX (instruction set)|MMX]] instruction set, the 3DNow! instruction-set augmented the MMX SIMD registers to support common arithmetic operations (add/subtract/multiply) on single-precision (32-bit) floating-point data.  Software written to use AMD's 3DNow! instead of the slower [[X87|x87 FPU]] could execute up to four times faster, depending on the instruction mix.

==Versions==

===3DNow!===
The first implementation of 3DNow! technology contains 21 new instructions that support [[SIMD]] floating-point operations. The 3DNow! data format is packed, single-precision, floating-point. The 3DNow! instruction set also includes operations for SIMD integer operations, data prefetch, and faster MMX-to-floating-point switching. Later, [[Company:Intel|Intel]] would add similar (but incompatible) instructions to the [[Engineering:Pentium III|Pentium III]], known as [[Streaming SIMD Extensions|SSE]] (Streaming SIMD Extensions).

3DNow! floating-point instructions are the following:
{{Div col|colwidth=30em}}
* <code>PI2FD</code>{{snd}} Packed 32-bit integer to floating-point conversion
* <code>PF2ID</code>{{snd}} Packed floating-point to 32-bit integer conversion
* <code>PFCMPGE</code>{{snd}} Packed floating-point comparison, greater or equal
* <code>PFCMPGT</code>{{snd}} Packed floating-point comparison, greater
* <code>PFCMPEQ</code>{{snd}} Packed floating-point comparison, equal
* <code>PFACC</code>{{snd}} Packed floating-point accumulate
* <code>PFADD</code>{{snd}} Packed floating-point addition
* <code>PFSUB</code>{{snd}} Packed floating-point subtraction
* <code>PFSUBR</code>{{snd}} Packed floating-point reverse subtraction
* <code>PFMIN</code>{{snd}} Packed floating-point minimum
* <code>PFMAX</code>{{snd}} Packed floating-point maximum
* <code>PFMUL</code>{{snd}} Packed floating-point multiplication
* <code>PFRCP</code>{{snd}} Packed floating-point reciprocal approximation
* <code>PFRSQRT</code>{{snd}} Packed floating-point reciprocal square root approximation
* <code>PFRCPIT1</code>{{snd}} Packed floating-point reciprocal, first iteration step
* <code>PFRSQIT1</code>{{snd}} Packed floating-point reciprocal square root, first iteration step
* <code>PFRCPIT2</code>{{snd}} Packed floating-point reciprocal/reciprocal square root, second iteration step
{{div col end}}

3DNow! integer instructions are the following:
* <code>PAVGUSB</code>{{snd}} Packed 8-bit unsigned integer averaging
* <code>PMULHRW</code>{{snd}} Packed 16-bit integer multiply with rounding

3DNow! performance-enhancement instructions are the following:
* <code>FEMMS</code>{{snd}} Faster entry/exit of the MMX or floating-point state
* <code>PREFETCH/PREFETCHW</code>{{snd}} Prefetch at least a 32-byte line into L1 data cache (this is the non-deprecated instruction)

===3DNow! extensions===
There is little or no evidence that the second version of 3DNow! was ever officially given its own trade name. This has led to some confusion in documentation that refers to this new instruction set. The most common terms are ''Extended 3DNow!'', ''Enhanced 3DNow!'' and ''3DNow!+''. The phrase "Enhanced 3DNow!" can be found in a few locations on the AMD website but the capitalization of "Enhanced" appears to be either purely grammatical or used for emphasis on processors that may or may not have these extensions (the most notable of which references a benchmark page for the K6-III-P that does not have these extensions).<ref name="extman">{{cite web
|url=https://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf
|title=AMD Extensions to the 3DNow and MMX Instruction Sets Manual
|publisher=Advanced Micro Devices, Inc.
|date=March 2000
|access-date=2008-06-07
|archive-date=2008-05-17
|archive-url=https://web.archive.org/web/20080517014932/http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf
|url-status=live
}}</ref><ref>{{cite web
|url=https://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_1260_1300%5E960,00.html
|title=Mobile AMD-K6-III-P Processor-Based Notebook: Ziff-Davis CPUmark 99
|quote=Incorrect title on page: Mobile AMD-K6-III+ and Mobile AMD-K6-2+ Processors with Enchanced {{sic}} 3DNow! Technology
|access-date=2008-06-07
|archive-date=2008-07-24
|archive-url=https://web.archive.org/web/20080724223037/http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_1260_1300%5E960,00.html
|url-status=live
}}</ref>

This extension to the 3DNow! instruction set was introduced with the first-generation [[Engineering:Athlon|Athlon]] processors. The Athlon added five new 3DNow! instructions and 19 new MMX instructions. Later, the [[Engineering:AMD K6-2|K6-2+]] and [[Engineering:AMD K6-III|K6-III+]] (both targeted at the mobile market) included the five new 3DNow! instructions, leaving out the 19 new MMX instructions. The new 3DNow! instructions were added to boost [[Digital signal processing|DSP]]. The new MMX instructions were added to boost [[Engineering:Streaming media|streaming media]].

The 19 new MMX instructions are a subset of Intel's SSE instruction set. In AMD technical manuals, AMD segregates these instructions apart from the 3DNow! extensions.<ref name="extman"/> In AMD customer product literature, however, this segregation is less clear where the benefits of all 24 new instructions are credited to enhanced 3DNow! technology.<ref>{{cite web
|url=https://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_1260_759%5E1151,00.html
|title=AMD Athlon Processor Product Brief
|publisher=Advanced Micro Devices, Inc.
|access-date=2008-06-08
|archive-date=2008-02-25
|archive-url=https://web.archive.org/web/20080225111905/http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_1260_759%5E1151,00.html
|url-status=live
}}</ref> This has led programmers to come up with their own name for the 19 new MMX instructions. The most common appears to be ''Integer SSE'' (''ISSE'').<ref>{{cite web
|url=http://avisynth.nl/index.php/ISSE
|title=ISSE
|website=[[Software:AviSynth|AviSynth]]
|access-date=2017-07-19
|archive-date=2017-07-02
|archive-url=https://web.archive.org/web/20170702204448/http://avisynth.nl/index.php/ISSE
|url-status=live
}}</ref> ''SSEMMX'' and ''MMX2'' are also found in video filter documentation from the public domain sector. ISSE could also refer to Internet SSE, an early name for SSE.

3DNow! extension DSP instructions are the following:
* <code>PF2IW</code>{{snd}} Packed floating-point to integer word conversion with sign extend
* <code>PI2FW</code>{{snd}} Packed integer word to floating-point conversion
* <code>PFNACC</code>{{snd}} Packed floating-point negative accumulate
* <code>PFPNACC</code>{{snd}} Packed floating-point mixed positive-negative accumulate
* <code>PSWAPD</code>{{snd}} Packed swap doubleword

MMX extension instructions (Integer SSE) are the following:
{{Div col|colwidth=30em}}
* <code>MASKMOVQ</code>{{snd}} Streaming (cache bypass) store using byte mask
* <code>MOVNTQ</code>{{snd}} Streaming (cache bypass) store
* <code>PAVGB</code>{{snd}} Packed average of unsigned byte
* <code>PAVGW</code>{{snd}} Packed average of unsigned word
* <code>PMAXSW</code>{{snd}} Packed maximum signed word
* <code>PMAXUB</code>{{snd}} Packed maximum unsigned byte
* <code>PMINSW</code>{{snd}} Packed minimum signed word
* <code>PMINUB</code>{{snd}} Packed minimum unsigned byte
* <code>PMULHUW</code>{{snd}} Packed multiply high unsigned word
* <code>PSADBW</code>{{snd}} Packed sum of absolute byte differences
* <code>PSHUFW</code>{{snd}} Packed shuffle word
* <code>PEXTRW</code>{{snd}} Extract word into integer register
* <code>PINSRW</code>{{snd}} Insert word from integer register
* <code>PMOVMSKB</code>{{snd}} Move byte mask to integer register
* <code>PREFETCHNTA</code>{{snd}} Prefetch using the NTA reference
* <code>PREFETCHT0</code>{{snd}} Prefetch using the T0 reference
* <code>PREFETCHT1</code>{{snd}} Prefetch using the T1 reference
* <code>PREFETCHT2</code>{{snd}} Prefetch using the T2 reference
* <code>SFENCE</code>{{snd}} Store fence
{{div col end}}

===3DNow! Professional===
''3DNow! Professional'' is a trade name used to indicate processors that combine 3DNow! technology with a complete SSE instructions set (such as SSE, SSE2 or SSE3).<ref>{{cite web
 |url=https://www.amd.com/us-en/Processors/SellAMDProducts/0,,30_177_4458_4513%5E1413%5E2137,00.html 
 |title=Explaining the new 3DNow! Professional Technology 
 |publisher=Advanced Micro Devices, Inc. 
 |access-date=2008-06-08 
 |url-status=dead 
 |archive-url=https://web.archive.org/web/20090121005440/http://www.amd.com/us-en/Processors/SellAMDProducts/0%2C%2C30_177_4458_4513%5E1413%5E2137%2C00.html 
 |archive-date=2009-01-21 
}}</ref> The Athlon XP was the first processor to carry the 3DNow! Professional trade name, and was the first product in the Athlon family to support the complete SSE instruction set (for the total of: 21 original 3DNow! instructions; five 3DNow! extension DSP instructions; 19 MMX extension instructions; and 52 additional SSE instructions for complete SSE compatibility).<ref>{{cite web
|url=https://www.amd.com/us-en/Processors/SellAMDProducts/0,,30_177_4458_3505%5E3785%5E3738,00.html
|title=AMD Athlon XP Architectural Features
|publisher=Advanced Micro Devices, Inc.
|access-date=2008-06-08
|archive-date=2008-02-25
|archive-url=https://web.archive.org/web/20080225112033/http://www.amd.com/us-en/Processors/SellAMDProducts/0,,30_177_4458_3505%5E3785%5E3738,00.html
|url-status=live
}}</ref>

===3DNow! and the Geode GX/LX===
The [[Engineering:Geode (processor)|Geode GX and Geode LX]] added two new 3DNow! instructions which are currently absent in all the other processors.

3DNow! "professional" instructions unique to the Geode GX/LX are the following:
* <code>PFRSQRTV</code>{{snd}} Reciprocal square root approximation for a pair of 32-bit floats
* <code>PFRCPV</code>{{snd}} Reciprocal approximation for a pair of 32-bit floats

==Advantages and disadvantages==
One advantage of 3DNow! is that it is possible to add or multiply the two numbers that are stored in the same [[Processor register|register]]. With SSE, each number can only be combined with a number in the same position in another register. This capability, known as ''horizontal'' in Intel terminology, was the major addition to the [[SSE3]] instruction set.

A disadvantage with 3DNow! is that 3DNow! instructions and MMX instructions share the same register-file, whereas SSE adds 8 new independent registers (<code>XMM0</code>&ndash;<code>XMM7</code>).

Because MMX/3DNow! registers are shared by the standard [[X87|x87]] FPU, 3DNow! instructions and x87 instructions cannot be executed simultaneously. However, because it is aliased to the x87 FPU, the 3DNow! and MMX register states can be saved and restored by the traditional x87 <code>F(N)SAVE</code> and <code>F(N)RSTOR</code> instructions. This arrangement allowed [[Operating system|operating system]]s to support 3DNow! with no explicit modifications, whereas SSE registers required explicit operating system support to properly save and restore the new XMM registers (via the added <code>FXSAVE</code> and <code>FXRSTOR</code> instructions.)

The FX* instructions from SSE provide a functional superset of the older x87 save and restore instructions. They can save not only SSE register states but also the x87 register states (hence are applicable also for MMX and 3DNow! operations where supported).

On AMD Athlon XP and K8-based cores (i.e. [[Engineering:Athlon 64|Athlon 64]]), assembly programmers have noted that it is possible to combine 3DNow! and SSE instructions to reduce register pressure, but in practice it is difficult to improve performance due to the instructions executing on shared functional units.<ref>{{cite newsgroup
 | title =3DNow+ vs SSE on Athlon XP
 | author =Larry Lewis
 | date =9 July 2003
 | newsgroup =comp.sys.ibm.pc.hardware.chips
 | message-id =ad82cd69.0307090931.25391323@posting.google.com
 | url =https://groups.google.com/group/comp.sys.ibm.pc.hardware.chips/browse_thread/thread/9da2d940c5b69745
 | url-access=subscription
 | access-date = 4 January 2023
 | archive-url=https://web.archive.org/web/20121003002542/https://groups.google.com/group/comp.sys.ibm.pc.hardware.chips/browse_thread/thread/9da2d940c5b69745
 | archive-date=2012-10-03
 | via=Google Groups}}</ref>

==Processors supporting 3DNow!==
* All [[Engineering:AMD|AMD]] processors after K6-2 (based on K6), Athlon, Athlon 64 and Phenom architecture families. Not supported in Bulldozer, Bobcat and Zen architecture processors and their derivates.
** The last [[Engineering:AMD|AMD]] [[Engineering:AMD APU|APU]] processor supporting 3DNow! is the A8-3870K, which is based on the [[Engineering:AMD APU#K10 architecture (2011): Llano|Llano]] architecture. It is also the only APU with 3DNow! instructions, as the Bobcat and up exclude support for it.
* National Semiconductor [[Engineering:Geode (processor)|Geode]], later AMD Geode.
* [[Engineering:VIA C3|VIA C3]] (also known as Cyrix III) "Samuel", "Samuel 2" "Ezra", and "Eden ESP" cores.
* IDT Winchip 2

==References==
{{Reflist|30em}}

==Further reading==
* Case, Brian (1 June 1998). "3DNow Boosts Non-Intel 3D Performance". ''Microprocessor Report''.
* Oberman, S.; Favor, G.; Weber, F. (March 1999). [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=755466 "AMD 3DNow technology: architecture and implementations"]. ''[[IEEE Micro]]''.

== External links ==
* [https://web.archive.org/web/20010124090100/http://www1.amd.com/products/cpg/3dnow/optimized/ 3DNow Technology Partners], archived from the [http://www1.amd.com/products/cpg/3dnow/optimized/ original] (removed from AMD's website in early 2001)
* [https://web.archive.org/web/20120121112218/http://support.amd.com/us/Processor_TechDocs/22621.pdf AMD 3DNow Instruction Porting Guide (PDF)], archived from the [http://support.amd.com/us/Processor_TechDocs/22621.pdf original] (removed from AMD's website in 2014)
* [http://support.amd.com/TechDocs/21928.pdf 3DNow Technology Manual]
* [https://support.amd.com/TechDocs/22466.pdf AMD Extensions to the 3DNow and MMX Instruction Sets Manual]
* [https://support.amd.com/TechDocs/33234H_LX_databook.pdf AMD Geode LX Processors Data Book]

{{AMD technology}}
{{Multimedia extensions}}

[[Category:X86 architecture]]

{{Sourceattribution|3DNow!|1}}