View source for Engineering:ARM Cortex-M

{{Short description|Group of 32-bit RISC processor cores}}
[[File:ARM Cortex-M0 and M3 ICs in SMD Packages.jpg|thumb|360px|right|ARM Cortex-M0 and Cortex-M3 microcontroller ICs from NXP and Silicon Labs (Energy Micro)]]
[[Image:STM32F100C4T6B-HD.jpg|thumb|right|[[Engineering:Die (integrated circuit)|Die]] from a STM32F100C4T6B IC.<br/>24&nbsp;[[Hertz|MHz]] ARM Cortex-M3 microcontroller with 16&nbsp;[[Kilobyte|KB]] [[Flash memory|flash memory]], 4&nbsp;KB RAM. Manufactured by STMicroelectronics.]]

The '''ARM Cortex-M''' is a group of [[32-bit|32-bit]] [[Reduced instruction set computer|RISC]] [[ARM architecture|ARM]] processor cores licensed by [[Company:Arm Holdings|Arm Holdings]].  These cores are optimized for low-cost and energy-efficient integrated circuits, which have been embedded in tens of billions of consumer devices.<ref>[http://www.arm.com/products/processors/cortex-m ARM Cortex-M website; arm.com]</ref>  Though they are most often the main component of [[Engineering:Microcontroller|microcontroller]] chips, sometimes they are embedded inside other types of chips too.  The Cortex-M family consists of Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M35P, Cortex-M55.<ref name="M0-TRM"/><ref name="M0+-TRM"/><ref name="M1-TRM"/><ref name="M3-TRM"/><ref name="M4-TRM"/><ref name="M7-TRM"/><ref name="M23-TRM"/>  The Cortex-M4 / M7 / M33 / M35P / M55 cores have an [[Floating-point unit|FPU]] silicon option, and when included in the silicon these cores are sometimes known as "Cortex-Mx with FPU" or "Cortex-MxF", where 'x' is the core variant.

==Overview==
{| class="wikitable" style="float:right; margin-left:9px;"
|-
! colspan=2 | 32-bit
|-
! Year !! Core
|-
| 2004 || Cortex-M3
|-
| 2007 || Cortex-M1
|-
| 2009 || Cortex-M0
|-
| 2010 || Cortex-M4
|-
| 2012 || Cortex-M0+
|-
| 2014 || Cortex-M7
|-
| 2016 || Cortex-M23
|-
| 2016 || Cortex-M33
|-
| 2018 || Cortex-M35P
|-
| 2020 || Cortex-M55
|-
| 2022 || Cortex-M85
|}

The ARM Cortex-M family are ARM microprocessor cores which are designed for use in [[Engineering:Microcontroller|microcontroller]]s, ASICs, [[Engineering:Application-specific integrated circuit#Application-specific standard product|ASSP]]s, FPGAs, and [[System on a chip|SoC]]s.  Cortex-M cores are commonly used as dedicated microcontroller chips, but also are "hidden" inside of SoC chips as power management controllers, I/O controllers, system controllers, touch screen controllers, smart battery controllers, and sensors controllers.

The main difference from the [[Engineering:ARM Cortex-A|Cortex-A]] core is that there is no [[Memory management unit|memory management unit]] (MMU). A full-fledged [[Operating system|operating system]] does not normally run on this class of processor.

Though 8-bit microcontrollers were very popular in the past, Cortex-M has slowly been chipping away at the 8-bit market as the prices of low-end Cortex-M chips have moved downward.  Cortex-M have become a popular replacements for 8-bit chips in applications that benefit from 32-bit math operations, and replacing older legacy ARM cores such as [[Engineering:ARM7|ARM7]] and [[Engineering:ARM9|ARM9]].

===License===
[[Company:Arm Holdings|Arm Holdings]] neither manufactures nor sells CPU devices based on its own designs, but rather licenses the processor architecture to interested parties. Arm offers a variety of licensing terms, varying in cost and deliverables. To all licensees, Arm provides an integratable hardware description of the ARM core, as well as complete software development toolset and the right to sell manufactured [[Chemistry:Silicon|silicon]] containing the ARM CPU.

===Silicon customization===
Integrated Device Manufacturers (IDM) receive the ARM Processor [[Social:Intellectual property|IP]] as [[Logic synthesis|synthesizable]] RTL (written in [[Verilog]]). In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions (including floating point), optimizations for size, debug support, etc.  To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation.

Some of the silicon options for the Cortex-M cores are:
* SysTick timer: A 24-bit system timer that extends the functionality of both the processor and the Nested Vectored Interrupt Controller (NVIC). When present, it also provides an additional configurable priority SysTick interrupt.<ref name="ARMv6-M-Manual"/><ref name="ARMv7-M-Manual"/><ref name="AppNote179"/> Though the SysTick timer is optional, it is very rare to find a Cortex-M microcontroller without it.  If a Cortex-M33 microcontroller has the Security Extension option, then it has two SysTicks, one Secure and one Non-secure.
* Bit-Band: Maps a complete word of memory onto a single bit in the bit-band region. For example, writing to an alias word will set or clear the corresponding bit in the bit-band region. This allows every individual bit in the bit-band region to be directly accessible from a word-aligned address. In particular, individual bits can be set, cleared, or toggled from C/C++ without performing a read-modify-write sequence of instructions.<ref name="ARMv6-M-Manual"/><ref name="ARMv7-M-Manual"/><ref name="AppNote179"/>  Though the bit-band is optional, it is less common to find a Cortex-M3 and Cortex-M4 microcontroller without it.  Some Cortex-M0 and Cortex-M0+ microcontrollers have bit-band. 
* Memory Protection Unit (MPU): Provides support for protecting regions of memory through enforcing privilege and access rules. It supports up to eight different regions, each of which can be split into a further eight equal-size sub-regions.<ref name="ARMv6-M-Manual"/><ref name="ARMv7-M-Manual"/><ref name="AppNote179"/>
* Tightly-Coupled Memory (TCM): Low-latency RAM that is used to hold critical routines, data, stacks.  Other than cache, it is typically the fastest RAM in the microcontroller.

{| class="wikitable"
|+ <big>ARM Cortex-M optional components</big>
|-
! ARM Core !! Cortex<br/>M0<ref name="M0-TRM"/> !! Cortex<br/>M0+<ref name="M0+-TRM"/> !! Cortex<br/>M1<ref name="M1-TRM"/> !! Cortex<br/>M3<ref name="M3-TRM"/> !! Cortex<br/>M4<ref name="M4-TRM"/> !! Cortex<br/>M7<ref name="M7-TRM"/> !! Cortex<br/>M23<ref name="M23-TRM"/> !! Cortex<br/>M33<ref name="M33-TRM"/> !! Cortex<br/>M35P<!--M35P TRM not available at this time-->
|-
| SysTick 24-bit [[Engineering:Programmable interval timer|Timer]] || style="background: yellow; text-align: center;" | Optional<br/>(0,1) || style="background: yellow; text-align: center;" | Optional<br/>(0,1) || style="background: yellow; text-align: center;" | Optional<br/>(0,1) || {{Yes|Yes<br/>(1)}} || {{Yes|Yes<br/>(1)}} || {{Yes|Yes<br/>(1)}} || style="background: yellow; text-align: center;" | Optional<br/>(0,1,2) || {{Yes|Yes<br/>(1,2)}} || {{Yes|Yes<br/>(1,2)}}
|-
| Single-cycle I/O port || {{No}} || style="background: yellow; text-align: center;" | Optional || {{No}} || {{No}} || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || {{No}} || {{No}}
|-
| Bit-Band memory || {{No}}<ref name="Cortex-M-SDK"/> || {{No}}<ref name="Cortex-M-SDK"/> || {{No}}* || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional || {{No}} || {{No}} || {{No}}
|-
| Memory Protection<br/>Unit (MPU) || {{No}} || style="background: yellow; text-align: center;" | Optional<br/>(0,8) || {{No}} || style="background: yellow; text-align: center;" | Optional<br/>(0,8) || style="background: yellow; text-align: center;" | Optional<br/>(0,8) || style="background: yellow; text-align: center;" | Optional<br/>(0,8,16) || style="background: yellow; text-align: center;" | Optional<br/>(0,4,8,12,16) || style="background: yellow; text-align: center;" | Optional<br/>(0,4,8,12,16) || style="background: grey; text-align: center;" | Optional<br/>*
|-
| [[ARM architecture#Security extensions|Security]] Attribution<br/>Unit (SAU) and<br/>Stack Limits || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional<br/>(0,4,8) || style="background: yellow; text-align: center;" | Optional<br/>(0,4,8) || style="background: grey; text-align: center;" | Optional<br/>*
|-
| Instruction TCM || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || {{No}} || {{No}} || {{No}}
|-
| Data TCM || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || {{No}} || {{No}} || {{No}} 
|-
| Instruction Cache || {{No}}<ref name="AppNote321">[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHEADII.html ARM Cortex-M Programming Guide to Memory Barrier Instructions; Section 3.6 System implementation requirements; AppNote 321; arm.com]</ref> || {{No}}<ref name="AppNote321"/> || {{No}}<ref name="AppNote321"/> || {{No}}<ref name="AppNote321"/> || {{No}}<ref name="AppNote321"/> || style="background: yellow; text-align: center;" | Optional || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional
|-
| Data Cache || {{No}}<ref name="AppNote321"/> || {{No}}<ref name="AppNote321"/> || {{No}}<ref name="AppNote321"/> || {{No}}<ref name="AppNote321"/> || {{No}}<ref name="AppNote321"/> || style="background: yellow; text-align: center;" | Optional || {{No}} || {{No}} || {{No}} 
|-
| [[Interrupt vector table|Vector Table]] Offset<br/>Register (VTOR) || {{No}} || style="background: yellow; text-align: center;" | Optional<br/>(0,1) || style="background: yellow; text-align: center;" | Optional<br/>(0,1) || style="background: yellow; text-align: center;" | Optional<br/>(0,1) || style="background: yellow; text-align: center;" | Optional<br/>(0,1) || style="background: yellow; text-align: center;" | Optional<br/>(0,1) || style="background: yellow; text-align: center;" | Optional<br/>(0,1,2) || {{Yes|Yes<br/>(1,2)}} || {{Yes|Yes<br/>(1,2)}}
|}
* Note: Most Cortex-M3 and M4 chips have bit-band and MPU.  The bit-band option can be added to the M0/M0+ using the Cortex-M System Design Kit.<ref name="Cortex-M-SDK">[http://www.arm.com/products/processors/cortex-m/cortex-m-system-design-kit.php Cortex-M System Design Kit; Arm Holdings.]</ref>
* Note: Software should validate the existence of a feature before attempting to use it.<ref name="AppNote179">[http://infocenter.arm.com/help/topic/com.arm.doc.dai0179b/AppsNote179.pdf Cortex-M3 Embedded Software Development; App Note 179; Arm Holdings.]</ref>
* Note: Limited public information is available for the Cortex-M35P until its ''Technical Reference Manual'' is released.

'''Additional silicon options:'''<ref name="ARMv6-M-Manual"/><ref name="ARMv7-M-Manual"/>
* Data endianness: Little-endian or big-endian.  Unlike legacy ARM cores, the Cortex-M is permanently fixed in silicon as one of these choices.
* Interrupts: 1 to 32 (M0/M0+/M1), 1 to 240 (M3/M4/M7/M23), 1 to 480 (M33/M35P).
* Wake-up interrupt controller: Optional.
* Vector Table Offset Register: Optional. (not available for M0).
* Instruction fetch width: 16-bit only, or mostly 32-bit.
* User/privilege support: Optional.
* Reset all registers: Optional.
* Single-cycle I/O port: Optional. (M0+/M23).
* Debug Access Port (DAP): None, SWD, JTAG and SWD. (optional for all Cortex-M cores)
* Halting debug support: Optional.
* Number of watchpoint comparators: 0 to 2 (M0/M0+/M1), 0 to 4 (M3/M4/M7/M23/M33/M35P).
* Number of breakpoint comparators: 0 to 4 (M0/M0+/M1/M23), 0 to 8 (M3/M4/M7/M33/M35P).

==={{anchor|ARMv6-M|ARMv7-M|ARMv7E-M}}Instruction sets===
The Cortex-M0 / M0+ / M1 implement the '''ARMv6-M''' architecture,<ref name="ARMv6-M-Manual"/> the Cortex-M3 implements the '''ARMv7-M''' architecture,<ref name="ARMv7-M-Manual"/> the Cortex-M4 / Cortex-M7 implements the '''ARMv7E-M''' architecture,<ref name="ARMv7-M-Manual"/> the Cortex-M23 / M33 / M35P implement the '''ARMv8-M''' architecture,<ref name="ARMv8-M-Manual"/> and the Cortex-M55 implements the '''ARMv8.1-M''' architecture.<ref name="ARMv8-M-Manual"/> The architectures are binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available for the Cortex-M0 / Cortex-M0+ / Cortex-M1 can execute without modification on the Cortex-M3 / Cortex-M4 / Cortex-M7. Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4 / Cortex-M7 / Cortex-M33 / Cortex-M35P.<ref name="ARMv6-M-Manual"/><ref name="ARMv7-M-Manual"/>  Only Thumb-1 and Thumb-2 instruction sets are supported in Cortex-M architectures; the legacy 32-bit ARM instruction set isn't supported.

All Cortex-M cores implement a common subset of instructions that consists of most Thumb-1, some Thumb-2, including a 32-bit result multiply.  The Cortex-M0 / Cortex-M0+ / Cortex-M1 / Cortex-M23 were designed to create the smallest silicon die, thus having the fewest instructions of the Cortex-M family.

The Cortex-M0 / M0+ / M1 include Thumb-1 instructions, except new instructions (CBZ, CBNZ, IT) which were added in ARMv7-M architecture.  The Cortex-M0 / M0+ / M1 include a minor subset of Thumb-2 instructions (BL, DMB, DSB, ISB, MRS, MSR).<ref name="ARMv6-M-Manual"/>  The Cortex-M3 / M4 / M7 / M33 / M35P have all base Thumb-1 and Thumb-2 instructions.  The Cortex-M3 adds three Thumb-1 instructions, all Thumb-2 instructions, hardware integer divide, and [[Saturation arithmetic|saturation arithmetic]] instructions.  The Cortex-M4 adds [[Engineering:Digital signal processor|DSP]] instructions and an optional single-precision [[Floating-point unit|floating-point unit]] (VFPv4-SP).  The Cortex-M7 adds an optional double-precision FPU (VFPv5).<ref name="M7-TRM"/><ref name="ARMv7-M-Manual"/>  The Cortex-M23 / M33 add TrustZone instructions.

{| class="wikitable"
|+ <big>ARM Cortex-M instruction variations</big>
|-
! Arm Core !! Cortex<br/>M0<ref name="M0-TRM"/> !! Cortex<br/>M0+<ref name="M0+-TRM"/> !! Cortex<br/>M1<ref name="M1-TRM"/> !! Cortex<br/>M3<ref name="M3-TRM"/> !! Cortex<br/>M4<ref name="M4-TRM"/> !! Cortex<br/>M7<ref name="M7-TRM"/> !! Cortex<br/>M23<ref name="M23-TRM"/> !! Cortex<br/>M33<ref name="M33-TRM"/> !! Cortex<br/>M35P !! Cortex<br/>M55
|-
| [[ARM architecture]] || style="text-align: center;" | ARMv6-M<ref name="ARMv6-M-Manual">{{cite web | url=https://documentation-service.arm.com/static/5f8ff05ef86e16515cdbf826?token= | title=ARMv6-M Architecture Reference Manual | publisher=Arm Holdings | date=29 June 2018 | url-status=live | archive-url=https://web.archive.org/web/20210122091059/https://documentation-service.arm.com/static/5f8ff05ef86e16515cdbf826?token= | archive-date=22 January 2021}}</ref> || style="text-align: center;" | ARMv6-M<ref name="ARMv6-M-Manual"/> || style="text-align: center;" | ARMv6-M<ref name="ARMv6-M-Manual"/> || style="text-align: center;" | ARMv7-M<ref name="ARMv7-M-Manual">{{cite web | url=https://documentation-service.arm.com/static/606dc36485368c4c2b1bf62f?token= | title=ARMv7-M Architecture Reference Manual | publisher=Arm Holdings | date=15 February 2021}}</ref> || style="text-align: center;" | ARMv7E-M<ref name="ARMv7-M-Manual"/> || style="text-align: center;" | ARMv7E-M<ref name="ARMv7-M-Manual"/> || style="text-align: center;" | ARMv8-M<br/>Baseline<ref name="ARMv8-M-Manual">[https://developer.arm.com/documentation/ddi0553/latest/ ARMv8-M Architecture Reference Manual; Arm Holdings.]</ref> || style="text-align: center;" | ARMv8-M<br/>Mainline<ref name="ARMv8-M-Manual"/> || style="text-align: center;" | ARMv8-M<br/>Mainline<ref name="ARMv8-M-Manual"/> || style="text-align: center;" | Armv8.1-M
|-
| [[Computer architecture]] || style="text-align: center;" | [[Von Neumann architecture|Von Neumann]] || style="text-align: center;" | Von Neumann || style="text-align: center;" | Von Neumann || style="text-align: center;" | [[Harvard architecture|Harvard]] || style="text-align: center;" | Harvard || style="text-align: center;" | Harvard || style="text-align: center;" | Von Neumann || style="text-align: center;" | Harvard || style="text-align: center;" | Harvard || style="text-align: center;" | Harvard
|-
| [[Instruction pipelining|Instruction pipeline]] || style="text-align: center;" | 3 stages || style="text-align: center;" | 2 stages || style="text-align: center;" | 3 stages || style="text-align: center;" | 3 stages || style="text-align: center;" | 3 stages || style="text-align: center;" | 6 stages || style="text-align: center;" | 2 stages || style="text-align: center;" | 3 stages || style="text-align: center;" | 3 stages || style="text-align: center;" | 4 to 5 stages
|-
| [[ARM architecture#Thumb|Thumb-1]] instructions || style="background: cyan; text-align: center;" | Most || style="background: cyan; text-align: center;" | Most || style="background: cyan; text-align: center;" | Most || {{Yes|Entire}} || {{Yes|Entire}} || {{Yes|Entire}} || style="background: cyan; text-align: center;" | Most || {{Yes|Entire}} || {{Yes|Entire}} || {{Yes|Entire}} 
|-
| [[ARM architecture#Thumb-2|Thumb-2]] instructions || style="background: cyan; text-align: center;" | Some || style="background: cyan; text-align: center;" | Some || style="background: cyan; text-align: center;" | Some || {{Yes|Entire}} || {{Yes|Entire}} || {{Yes|Entire}} || style="background: cyan; text-align: center;" | Some || {{Yes|Entire}} || {{Yes|Entire}} || {{Yes|Entire}} 
|-
| [[Multiplication algorithm|Multiply]] instructions<br/>32x32 = 32-bit result || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} 
|-
| Multiply instructions<br/>32x32 = 64-bit result || {{No}} || {{No}} || {{No}} || {{Yes}} || {{Yes}} || {{Yes}} || {{No}} || {{Yes}} || {{Yes}} || {{Yes}} 
|-
| [[Division algorithm|Divide]] instructions<br/>32/32 = 32-bit quotient || {{No}} || {{No}} || {{No}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} 
|-
| [[Saturation arithmetic|Saturated]] instructions || {{No}} || {{No}} || {{No}} || style="background: cyan; text-align: center;" | Some || {{Yes}} || {{Yes}} || {{No}} || {{Yes}} || {{Yes}} || {{Yes}} 
|-
| [[Engineering:Digital signal processor|DSP]] instructions || {{No}} || {{No}} || {{No}} || {{No}} || {{Yes}} || {{Yes}} || {{No}} || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional
|-
| [[Single-precision floating-point format|Single-Precision]] (SP)<br/>[[Floating-point unit|Floating-point]] instructions || {{No}} || {{No}} || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional || {{No}} || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional
|-
| [[Double-precision floating-point format|Double-Precision]] (DP)<br/>Floating-point instructions || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || {{No}} || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional
|-
|Half-Precisions (HP)|| {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional
|-
|TrustZone instructions || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional
|-
|[[Coprocessor|Co-processor]] instructions || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional
|-
|Helium technology|| {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional
|-
|[[Interrupt latency]]<br/>(if zero-wait state RAM) || style="text-align: center;" | 16 cycles || style="text-align: center;" | 15 cycles || style="text-align: center;" | 23 for NMI<br/>26 for IRQ || style="text-align: center;" | 12 cycles || style="text-align: center;" | 12 cycles || style="text-align: center;" | 12 cycles<br/>14 worst case || style="text-align: center;" | 15 no security ext<br/>27 security ext || style="text-align: center;" | 12 no security ext<br/>?? security ext || style="background: grey; text-align: center;" | TBD || style="background: grey; text-align: center;" | TBD
|}
* Note: The Cortex-M0 / M0+ / M1 doesn't include these 16-bit '''Thumb-1''' instructions: CBZ, CBNZ, IT.<ref name="ARMv6-M-Manual"/><ref name="ARMv7-M-Manual"/>
* Note: The Cortex-M0 / M0+ / M1 only include these 32-bit '''Thumb-2''' instructions: BL, DMB, DSB, ISB, MRS, MSR.<ref name="ARMv6-M-Manual"/><ref name="ARMv7-M-Manual"/>
* Note: The Cortex-M0 / M0+ / M1 / M23 only has 32-bit '''multiply''' instructions with a lower-32-bit result (32bit × 32bit = lower 32bit), where as the Cortex-M3 / M4 / M7 / M33 / M35P includes additional 32-bit multiply instructions with 64-bit results (32bit × 32bit = 64bit). The Cortex-M4 / M7 (optionally M33 / M35P) include DSP instructions for (16bit × 16bit = 32bit), (32bit × 16bit = upper 32bit), (32bit × 32bit = upper 32bit) multiplications.<ref name="ARMv6-M-Manual"/><ref name="ARMv7-M-Manual"/> 
* Note: The number of cycles to complete multiply and divide instructions vary across ARM Cortex-M core designs.  Some cores have a silicon option for the choice of fast speed or small size (slow speed), so cores have the option of using less silicon with the downside of higher cycle count. An interrupt occurring during the execution of a divide instruction or slow-iterative multiply instruction will cause the processor to abandon the instruction, then restart it after the interrupt returns.
** Multiply instructions "32-bit result"{{snd}} Cortex-M0/M0+/M23 is 1 or 32 cycle silicon option, Cortex-M1 is 3 or 33 cycle silicon option, Cortex-M3/M4/M7/M33/M35P is 1 cycle.
** Multiply instructions "64-bit result"{{snd}} Cortex-M3 is 3–5 cycles (depending on values), Cortex-M4/M7/M33/M35P is 1 cycle.
** Divide instructions{{snd}} Cortex-M3/M4 is 2–12 cycles (depending on values), Cortex-M7 is 3–20 cycles (depending on values), Cortex-M23 is 17 or 34 cycle option, Cortex-M33 is 2–11 cycles (depending on values), Cortex-M35P is TBD.
* Note: The Cortex-M4 / M7 / M33 / M35P has a silicon option choice of no '''FPU''' or [[Single-precision floating-point format|single-precision]] ('''SP''') FPU, and the Cortex-M7 adds a third silicon option of supporting both single-precision (SP) and [[Double-precision floating-point format|double-precision]] ('''DP''').  If the Cortex-M4 / M7 / M33 / M35P has a FPU, then it is known as the Cortex-M4'''F''' / Cortex-M7'''F''' / Cortex-M33'''F''' / Cortex-M35P'''F'''.<ref name="ARMv6-M-Manual"/><ref name="ARMv7-M-Manual"/>
* Note: The Cortex-M series includes three new 16-bit '''Thumb-1''' instructions for sleep mode: SEV, WFE, WFI.
* Note: Interrupt latency cycle count assumes: 1) stack located in zero-wait state RAM, 2) another interrupt function not currently executing, 3) Security Extension option doesn't exist, because it adds additional cycles. The Cortex-M cores with a Harvard computer architecture have a shorter interrupt latency than Cortex-M cores with a Von Neumann computer architecture.

{| class="wikitable"
|+ <big>ARM Cortex-M instruction groups</big>
|-
! Group !! Instr<br/>bits !! Instructions !! Cortex<br/>M0,M0+,M1 !! Cortex<br/>M3 !! Cortex<br/>M4 !! Cortex<br/>M7 !! Cortex<br/>M23 !! Cortex<br/>M33,M35P !! Cortex<br/>M55
|-
| style="text-align: center;" | {{nowrap|Thumb-1}} || style="text-align: center;" | 16 || ADC, ADD, ADR, AND, ASR, B, BIC, BKPT, BLX, BX, CMN, CMP, CPS, EOR, LDM, LDR, LDRB, LDRH, LDRSB, LDRSH, LSL, LSR, MOV, MUL, MVN, NOP, ORR, POP, PUSH, REV, REV16, REVSH, ROR, RSB, SBC, SEV, STM, STR, STRB, STRH, SUB, SVC, SXTB, SXTH, TST, UXTB, UXTH, WFE, WFI, YIELD || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} 
|-
| style="text-align: center;" | {{nowrap|Thumb-1}} || style="text-align: center;" | 16 ||| CBNZ, CBZ || {{No}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} 
|-
| style="text-align: center;" | {{nowrap|Thumb-1}} || style="text-align: center;" | 16 ||| IT || {{No}} || {{Yes}} || {{Yes}} || {{Yes}} || {{No}} || {{Yes}} || {{Yes}} 
|-
| style="text-align: center;" | {{nowrap|Thumb-2}} || style="text-align: center;" | 32 || BL, DMB, DSB, ISB, MRS, MSR || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} 
|-
| style="text-align: center;" | {{nowrap|Thumb-2}} || style="text-align: center;" | 32 ||| SDIV, UDIV, MOVT, MOVW || {{No}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} || {{Yes}} 
|-
| style="text-align: center;" | {{nowrap|Thumb-2}} || style="text-align: center;" | 32 || ADC, ADD, ADR, AND, ASR, B, BFC, BFI, BIC, CDP, CLREX, [[Find first set#CLZ|CLZ]], CMN, CMP, DBG, EOR, LDC, LDM, LDR, LDRB, LDRBT, LDRD, LDREX, LDREXB, LDREXH, LDRH, LDRHT, LDRSB, LDRSBT, LDRSH, LDRSHT, LDRT, LSL, LSR, MCR, MCRR, MLA, MLS, MRC, MRRC, MUL, MVN, NOP, ORN, ORR, PLD, PLDW, PLI, POP, PUSH, RBIT, REV, REV16, REVSH, ROR, RRX, RSB, SBC, SBFX, SEV, SMLAL, SMULL, SSAT, STC, STM, STR, STRB, STRBT, STRD, STREX, STREXB, STREXH, STRH, STRHT, STRT, SUB, SXTB, SXTH, TBB, TBH, TEQ, TST, UBFX, UMLAL, UMULL, USAT, UXTB, UXTH, WFE, WFI, YIELD || {{No}} || {{Yes}} || {{Yes}} || {{Yes}} || {{No}} || {{Yes}} || {{Yes}} 
|-
| style="text-align: center;" | [[Engineering:Digital signal processor|DSP]] || style="text-align: center;" | 32 || PKH, QADD, QADD16, QADD8, QASX, QDADD, QDSUB, QSAX, QSUB, QSUB16, QSUB8, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSAX, SHSUB16, SHSUB8, SMLABB, SMLABT, SMLATB, SMLATT, SMLAD, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, SMLAWB, SMLAWT, SMLSD, SMLSLD, SMMLA, SMMLS, SMMUL, SMUAD, SMULBB, SMULBT, SMULTT, SMULTB, SMULWT, SMULWB, SMUSD, SSAT16, SSAX, SSUB16, SSUB8, SXTAB, SXTAB16, SXTAH, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSAX, UHSUB16, UHSUB8, UMAAL, UQADD16, UQADD8, UQASX, UQSAX, UQSUB16, UQSUB8, USAD8, USADA8, USAT16, USAX, USUB16, USUB8, UXTAB, UXTAB16, UXTAH, UXTB16 || {{No}} || {{No}} || {{Yes}} || {{Yes}}|| {{No}} || style="background: yellow; text-align: center;" | Optional || {{Yes}} 
|-
| style="text-align: center;" | [[Single-precision floating-point format|SP Float]] || style="text-align: center;" | 32 || VABS, VADD, VCMP, VCMPE, VCVT, VCVTR, VDIV, VLDM, VLDR, VMLA, VMLS, VMOV, VMRS, VMSR, VMUL, VNEG, VNMLA, VNMLS, VNMUL, VPOP, VPUSH, VSQRT, VSTM, VSTR, VSUB || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional || {{No}} || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional
|-
| style="text-align: center;" | [[Double-precision floating-point format|DP Float]] || style="text-align: center;" | 32 || VCVTA, VCVTM, VCVTN, VCVTP, VMAXNM, VMINNM, VRINTA, VRINTM, VRINTN, VRINTP, VRINTR, VRINTX, VRINTZ, VSEL || {{No}} || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional
|-
| style="text-align: center;" | TrustZone || style="text-align: center;" | 16 || BLXNS, BXNS || {{No}} || {{No}} || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional
|-
| style="text-align: center;" | TrustZone || style="text-align: center;" | 32 || SG, TT, TTT, TTA, TTAT || {{No}} || {{No}} || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional
|-
| style="text-align: center;" | [[Coprocessor|Co-processor]] || style="text-align: center;" | 16 || CDP, CDP2, MCR, MCR2, MCRR, MCRR2, MRC, MRC2, MRRC, MRRC2 || {{No}} || {{No}} || {{No}} || {{No}} || {{No}} || style="background: yellow; text-align: center;" | Optional || style="background: yellow; text-align: center;" | Optional
|}
* Note: MOVW is an alias that means 32-bit "wide" MOV instruction.
* Note: For Cortex-M1, WFE / WFI / SEV instructions exist, but execute as a NOP instruction.
* Note: The single-precision (SP) FPU instructions are valid in the Cortex-M4 / M7 / M33 / M35P only when the SP FPU option exists in the silicon.
* Note: The double-precision (DP) FPU instructions are valid in the Cortex-M7 only when the DP FPU option exists in the silicon.

===Deprecations===
The ARM architecture for ARM Cortex-M series removed some features from older legacy cores:<ref name="ARMv6-M-Manual"/><ref name="ARMv7-M-Manual"/>
* The 32-bit ARM instruction set is not included in Cortex-M cores.
* Endianness is chosen at silicon implementation in Cortex-M cores.  Legacy cores allowed "on-the-fly" changing of the data [[Endianness|endian]] mode.
* [[Coprocessor|Co-processor]] were not supported on Cortex-M cores, until the silicon option was reintroduced in "ARMv8-M Mainline" for ARM Cortex-M33/M35P cores.

The capabilities of the 32-bit ARM instruction set is duplicated in many ways by the Thumb-1 and Thumb-2 instruction sets, but some ARM features don't have a similar feature:
* The SWP and SWPB (swap) ARM instructions don't have a similar feature in Cortex-M.

The 16-bit Thumb-1 instruction set has evolved over time since it was first released in the legacy [[Engineering:ARM7|ARM7T]] cores with the ARMv4T architecture.  New Thumb-1 instructions were added as each legacy ARMv5 / ARMv6 / ARMv6T2 architectures were released. Some 16-bit Thumb-1 instructions were removed from the Cortex-M cores:
* The "BLX <immediate>" instruction doesn't exist because it was used to switch from Thumb-1 to ARM instruction set.  The "BLX <register>" instruction is still available in the Cortex-M.
* SETEND doesn't exist because on-the-fly switching of data endian mode is no longer supported.
* Co-processor instructions were not supported on Cortex-M cores, until the silicon option was reintroduced in "ARMv8-M Mainline" for ARM Cortex-M33/M35P cores.
* The SWI instruction was renamed to SVC, though the instruction binary coding is the same. However, the SVC handler code is different from the SWI handler code, because of changes to the exception models.

==Cortex-M0==
{{Infobox CPU
|name = Cortex-M0
|arch = [[ARM architecture#Thumb|Thumb-1]] (most),<br/>[[ARM architecture#Thumb-2|Thumb-2]] (some)
|microarch = ARMv6-M
}}

The Cortex-M0 core is optimized for small silicon die size and use in the lowest price chips.

Key features of the Cortex-M0 core are:<ref name="M0-TRM">[https://developer.arm.com/documentation/ddi0432/latest/ Cortex-M0 Technical Reference Manual Revision r0p0; Arm Holdings.]</ref>
* ARMv6-M architecture<ref name="ARMv6-M-Manual"/>
* 3-stage [[Pipeline (computing)|pipeline]]
* Instruction sets:
** Thumb-1 (most), missing CBZ, CBNZ, IT
** Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR
** 32-bit hardware integer multiply with 32-bit result
* 1 to 32 [[Interrupt|interrupt]]s, plus [[Non-maskable interrupt|NMI]]

'''Silicon options:'''
* Hardware integer multiply speed: 1 or 32 cycles.

===Chips===
[[File:M2 Health Bracelet - controller board - Nordic N51822-0627.jpg|thumb|nRF51822]]
The following microcontrollers are based on the Cortex-M0 core:
* ABOV AC30M1x64
* [[Company:Cypress Semiconductor|Cypress]] PSoC 4000, 4100, 4100M, 4200, 4200DS, 4200L, 4200M 
* [[Company:Infineon Technologies|Infineon]] [[Engineering:Infineon XMC|XMC1100]], XMC1200, XMC1300, XMC1400, TLE984x
* Dialog DA1458x, DA1468x
* [[Company:Nordic Semiconductor|Nordic]] nRF51
* NXP LPC1100, LPC1200
* [[Company:Nuvoton|Nuvoton]] NuMicro
* Sonix SN32F700
* [[Company:STMicroelectronics|ST]] [[Engineering:STM32#STM32 F0|STM32 F0]]
* [[Company:Toshiba|Toshiba]] TX00
* Vorago VA10800 (extreme temperature), VA10820 (radiation hardened)

The following chips have a Cortex-M0 as a secondary core:
* NXP LPC4300 (one Cortex-M4F + one Cortex-M0)
* [[Company:Texas Instruments|Texas Instruments]] SimpleLink Wireless MCUs CC1310 and CC2650 (one programmable Cortex-M3 + one Cortex-M0 network processor + one proprietary Sensor Controller Engine)

==Cortex-M0+==
{{Infobox CPU
|name = Cortex-M0+
|arch = [[ARM architecture#Thumb|Thumb-1 (most)]],<br/>[[ARM architecture#Thumb-2|Thumb-2 (some)]]
|microarch = ARMv6-M
}}
[[File:Freescale FRDM-KL25Z board with KL25Z128VLK (ARM Cortex-M0+ MCU).JPG|thumb|right| NXP (Freescale) FRDM-KL25Z Board with KL25Z128VLK (Kinetis L)]]
The Cortex-M0+ is an optimized superset of the Cortex-M0. The Cortex-M0+ has complete instruction set compatibility with the Cortex-M0 thus allowing the use of the same compiler and debug tools.  The Cortex-M0+ pipeline was reduced from 3 to 2 stages, which lowers the power usage. In addition to debug features in the existing Cortex-M0, a silicon option can be added to the Cortex-M0+ called the Micro Trace Buffer (MTB) which provides a simple instruction trace buffer. The Cortex-M0+ also received Cortex-M3 and Cortex-M4 features, which can be added as silicon options, such as the [[Memory protection|memory protection]] unit (MPU) and the vector table relocation.<ref name="M0+-TRM"/>

Key features of the Cortex-M0+ core are:<ref name="M0+-TRM">[https://developer.arm.com/documentation/ddi0484/latest/ Cortex-M0+ Technical Reference Manual Revision r0p1; Arm Holdings.]</ref>
* ARMv6-M architecture<ref name="ARMv6-M-Manual"/>
* 2-stage [[Pipeline (computing)|pipeline]] (one fewer than Cortex-M0)
* Instruction sets: (same as Cortex-M0)
** Thumb-1 (most), missing CBZ, CBNZ, IT
** Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR
** 32-bit hardware integer multiply with 32-bit result
* 1 to 32 [[Interrupt|interrupt]]s, plus [[Non-maskable interrupt|NMI]]

'''Silicon options:'''
* Hardware integer multiply speed: 1 or 32 cycles
* 8-region memory protection unit (MPU) (same as M3 and M4)
* Vector table relocation (same as M3, M4)
* Single-cycle I/O port (available in M0+/M23)
* Micro Trace Buffer (MTB) (available in M0+/M23/M33/M35P)

===Chips===
The following microcontrollers are based on the Cortex-M0+ core:
* ABOV Semiconductor A31G11x, A31G12x, A31G314
* [[Company:Cypress Semiconductor|Cypress]] PSoC 4000S, 4100S, 4100S+, 4100PS, 4700S, FM0+
* [[Company:Epson|Epson]] S1C31W74, S1C31D01, S1C31D50
* Holtek HT32F52000
* Microchip (Atmel) [[Engineering:Atmel ARM-based processors|SAM]] C2, D0, D1, D2, DA, L2, R2, R3
* NXP LPC800, LPC11E60, LPC11U60
* NXP (Freescale) Kinetis E, EA, L, M, V1, W0
* [[Organization:Raspberry Pi Foundation|Raspberry Pi]] [[Engineering:RP2040|RP2040]] (two M0+ cores)
* Renesas S124, S128, RE, RE01
* [[Company:Silicon Labs|Silicon Labs]] ([[Company:Energy Micro|Energy Micro]]) [[Engineering:EFM32|EFM32]] Zero, Happy
* [[Company:STMicroelectronics|ST]] [[Engineering:STM32#STM32 L0|STM32 L0]], [[Engineering:STM32#STM32 G0|G0]]

The following chips have a Cortex-M0+ as a secondary core:
* [[Company:Cypress Semiconductor|Cypress]] PSoC 6200 (one Cortex-M4F + one Cortex-M0+)
* [[Company:STMicroelectronics|ST]] WB (one Cortex-M4F + one Cortex-M0+)

The smallest ARM microcontrollers are of the Cortex-M0+ type (as of 2014, smallest at 1.6&nbsp;mm by 2&nbsp;mm in a [[Engineering:Chip-scale package|chip-scale package]] is Kinetis KL03).<ref>{{cite news |url=https://www.engadget.com/2014/02/25/freescale-kinetis-kl03/ |title=Freescale makes the world's smallest ARM controller chip even tinier |first=Jon |last=Fingas |date=25 February 2014 |access-date=2 October 2014}}</ref>

On 21 June 2018, the "[[Engineering:Microcontroller#Smallest computer|world's smallest computer']]", or computer device was announced{{snd}} based on the ARM Cortex-M0+ (and including RAM and wireless transmitters and receivers based on [[Chemistry:Photovoltaics|photovoltaics]]){{snd}} by [[Organization:University of Michigan|University of Michigan]] researchers at the 2018 Symposia on VLSI Technology and Circuits with the paper "A 0.04mm<sup>3</sup> 16nW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature Measurement." The device is 1/10th the size of IBM's previously claimed world-record-sized computer from months back in March 2018, which is smaller than a grain of salt.

==Cortex-M1==
{{Infobox CPU
|name = Cortex-M1
|arch = [[ARM architecture#Thumb|Thumb-1 (most)]],<br/>[[ARM architecture#Thumb-2|Thumb-2 (some)]]
|microarch = ARMv6-M
}}

The Cortex-M1 is an optimized core especially designed to be loaded into FPGA chips.

Key features of the Cortex-M1 core are:<ref name="M1-TRM">[http://infocenter.arm.com/help/topic/com.arm.doc.ddi0413d/DDI0413D_cortexm1_r1p0_trm.pdf Cortex-M1 r1p0 Technical Reference Manual; Arm Holdings.]</ref>
* ARMv6-M architecture<ref name="ARMv6-M-Manual"/>
* 3-stage [[Pipeline (computing)|pipeline]].
* Instruction sets:
** Thumb-1 (most), missing CBZ, CBNZ, IT.
** Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.
** 32-bit hardware integer multiply with 32-bit result.
* 1 to 32 [[Interrupt|interrupt]]s, plus [[Non-maskable interrupt|NMI]].

'''Silicon options:'''
* Hardware integer multiply speed: 3 or 33 cycles.
* Optional Tightly-Coupled Memory (TCM): 0 to 1&nbsp;MB instruction-TCM, 0 to 1&nbsp;MB data-TCM, each with optional ECC.
* External interrupts: 0, 1, 8, 16, 32.
* Debug: none, reduced, full.
* Data endianness: little-endian or BE-8 big-endian. 
* OS extension: present or absent.

===Chips===
The following vendors support the Cortex-M1 as soft-cores on their FPGA chips:
* [[Company:Altera|Altera]] Cyclone-II, Cyclone-III, Stratix-II, Stratix-III
* GOWIN M1 <ref>[https://www.gowinsemi.com/en/about/detail/latest_news/37/ GOWIN Semiconductor joins ARM DesignStart offering free ARM Cortex-M1 Processors for its FPGA product families]</ref>
* [[Company:Actel|Actel]]/[[Company:Microsemi|Microsemi]]/[[Company:Microchip Technology|Microchip]] Fusion, IGLOO/e, ProASIC3L, ProASIC3/E
* [[Company:Xilinx|Xilinx]] Spartan-3, Virtex-2, Virtex-3, Virtex-4, Artix-7<ref>[https://silver.arm.com/browse/AT472 Cortex-M1 DesignStart FPGA XilinxEdition]</ref>

==Cortex-M3==
{{Infobox CPU
|name = Cortex-M3
|arch = [[ARM architecture#Thumb|Thumb-1]], [[ARM architecture#Thumb-2|Thumb-2]],<br/> [[Saturation arithmetic|Saturated]] (some), Divide
|microarch = ARMv7-M
}}
[[File:ArduinoDue Front.jpg|thumb|300px|right|[[Software:Arduino|Arduino]] Due board with Atmel ATSAM3X8E (ARM Cortex-M3 core) microcontroller]]
[[File:LPCXpresso DevelopmentBoard with NXP LPC1343 (ARM Cortex-M3) MCU.jpg|thumb|300px|NXP LPCXpresso Development Board with LPC1343]]

Key features of the Cortex-M3 core are:<ref name="M3-TRM">[http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337i/DDI0337I_cortexm3_r2p1_trm.pdf Cortex-M3 r2p1 Technical Reference Manual; Arm Holdings.]</ref><ref>{{cite web|last=Sadasivan |first=Shyam |title=An Introduction to the ARM Cortex-M3 Processor |url=http://www.arm.com/files/pdf/IntroToCortex-M3.pdf |publisher=[[Company:Arm Holdings|Arm Holdings]] |url-status=dead |archive-url=https://web.archive.org/web/20140726212528/http://www.arm.com/files/pdf/IntroToCortex-M3.pdf |archive-date=July 26, 2014 }}</ref> 
* ARMv7-M architecture<ref name="ARMv7-M-Manual"/>
* 3-stage [[Pipeline (computing)|pipeline]] with [[Branch predictor|branch speculation]].
* Instruction sets:
** Thumb-1 (entire).
** Thumb-2 (entire).
** 32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply. 32-bit multiply is 1 cycle, but 64-bit multiply and MAC instructions require extra cycles.
** 32-bit hardware integer divide (2–12 cycles).
** [[Saturation arithmetic|saturation arithmetic]] support.
* 1 to 240 [[Interrupt|interrupt]]s, plus [[Non-maskable interrupt|NMI]].
* 12 cycle interrupt latency.
* Integrated sleep modes.

'''Silicon options:'''
* Optional Memory Protection Unit (MPU): 0 or 8 regions.

===Chips===
The following microcontrollers are based on the Cortex-M3 core:
* ABOV AC33Mx128, AC33Mx064
* [[Company:Actel|Actel]]/[[Company:Microsemi|Microsemi]]/[[Company:Microchip Technology|Microchip]] [[Actel SmartFusion|SmartFusion, SmartFusion 2]] (FPGA)
* Analog Devices ADUCM360, ADUCM361, ADUCM3029
* [[Company:Broadcom Corporation|Broadcom]] Wi-Fi Chip BCM4319XKUBG
* [[Company:Cypress Semiconductor|Cypress]] PSoC 5000, 5000LP, FM3
* Holtek HT32F
* [[Company:Infineon Technologies|Infineon]] TLE9860, TLE987x
* Microchip (Atmel) [[Engineering:Atmel ARM-based processors|SAM]] 3A, 3N, 3S, 3U, 3X
* NXP LPC1300, LPC1700, LPC1800
* ON Semiconductor Q32M210
* [[Company:Realtek|Realtek]] RTL8710
* [[Company:Silicon Labs|Silicon Labs]] Precision32
* [[Company:Silicon Labs|Silicon Labs]] ([[Company:Energy Micro|Energy Micro]]) [[Engineering:EFM32|EFM32 Tiny, Gecko, Leopard, Giant]]
* [[Company:STMicroelectronics|ST]] [[Engineering:STM32|STM32]] F1, F2, L1, W
* TDK-Micronas HVC4223F
* Texas Instruments F28, LM3, TMS470, [[Engineering:OMAP#OMAP 4|OMAP 4]], SimpleLink Wireless MCUs (CC1310 Sub-GHz and CC2650 BLE+ZigBee+[[6LoWPAN|6LoWPAN]])
* [[Company:Toshiba|Toshiba]] TX03

The following chips have a Cortex-M3 as a secondary core:
* [[Engineering:Apple A9|Apple A9]] (Cortex-M3 as integrated [[Engineering:Apple motion coprocessors|M9 motion co-processor]])
* [[Company:CSR plc|CSR]] Quatro 5300 (Cortex-M3 as co-processor)
* [[Company:Samsung|Samsung]] [[Engineering:Exynos|Exynos]] 7420 (Cortex-M3 as a [[Physics:Dynamic voltage scaling|DVS]] microcontroller)<ref>{{cite web | url=https://www.anandtech.com/show/9330/exynos-7420-deep-dive/ | title=The Samsung Exynos 7420 Deep Dive - Inside a Modern 14nm SoC | publisher=AnandTech | access-date=2015-06-15}}</ref>
* [[Company:Texas Instruments|Texas Instruments]] F28, LM3, TMS470, [[Engineering:OMAP#OMAP 4|OMAP 4470]] (one Cortex-A9 + two Cortex-M3)
* [[Company:XMOS|XMOS]] XS1-XA (seven xCORE + one Cortex-M3)

The following FPGAs include a Cortex-M3 core:
* [[Company:Microsemi|Microsemi]] SmartFusion2 SoC

The following vendors support the Cortex-M3 as soft-cores on their FPGA chips:
* [[Company:Altera|Altera]] Cyclone-II, Cyclone-III, Stratix-II, Stratix-III
* [[Company:Xilinx|Xilinx]] Spartan-3, Virtex-2, Virtex-3, Virtex-4, Artix-7<ref>[https://silver.arm.com/browse/AT426 Cortex-M3 DesignStart FPGA XilinxEdition]</ref>

==Cortex-M4==
{{Infobox CPU
|name = Cortex-M4
|arch = [[ARM architecture#Thumb|Thumb-1]], [[ARM architecture#Thumb-2|Thumb-2]],<br/>[[Saturation arithmetic|Saturated]], [[ARM architecture#DSP enhancement instructions|DSP]],<br/>Divide, [[ARM architecture#Floating-point (VFP)|FPU]] (SP)
|microarch = ARMv7E-M
}}
[[File:Energy Micro Woder Gecko STK showing EFM32WG990F256  (ARM Cortex-M4F) MCU.JPG|thumb|right|Silicon Labs (Energy Micro) Wonder Gecko STK Board with EFM32WG990]]
[[File:TI Stellaris Launchpad showing LM4F120H (ARM Cortex-M4F) MCU.JPG|thumb|[[Company:Texas Instruments|TI]] Stellaris Launchpad Board with LM4F120]]
Conceptually the Cortex-M4 is a Cortex-M3 plus [[Engineering:Digital signal processor|DSP]] instructions, and optional floating-point unit (FPU). A core with an FPU is known as Cortex-M4F.

Key features of the Cortex-M4 core are:<ref name="M4-TRM">[https://developer.arm.com/documentation/100166/0001/ric1417175948576 Cortex-M4 Technical Reference Manual Revision r0p1; Arm Holdings.]</ref>
* ARMv7E-M architecture<ref name="ARMv7-M-Manual"/>
* 3-stage [[Pipeline (computing)|pipeline]] with [[Branch predictor|branch speculation]].
* Instruction sets:
** Thumb-1 (entire).
** Thumb-2 (entire).
** 32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply. 32-bit Multiply and MAC are 1 cycle.
** 32-bit hardware integer divide (2–12 cycles).
** [[Saturation arithmetic]] support.
** DSP extension: Single cycle 16/32-bit [[Multiply–accumulate operation|MAC]], single cycle dual 16-bit MAC, 8/16-bit [[SIMD]] arithmetic.
* 1 to 240 [[Interrupt|interrupt]]s, plus [[Non-maskable interrupt|NMI]].
* 12 cycle interrupt latency.
* Integrated sleep modes.

'''Silicon options:'''
* Optional floating-point unit (FPU): single-precision only IEEE-754 compliant. It is called the FPv4-SP extension.
* Optional memory protection unit (MPU): 0 or 8 regions.

===Chips===
[[File:Micro-bit v2 (cropped) nRF52833.JPG|thumb|upright|nRF52833 on a micro bit v2]]
[[File:Embedded World 2016, M32F407 (cropped) STM M32F407IG.jpg|thumb|upright|STM32F407IGH6]]
The following microcontrollers are based on the Cortex-M4 core:
* Analog Devices ADSP-CM40x
* Microchip (Atmel) [[Engineering:Atmel ARM-based processors|SAM]] 4L, 4N, 4S
* NXP (Freescale) Kinetis K, W2
* [[Company:Texas Instruments|Texas Instruments]] SimpleLink [[Wi-Fi]] CC32xx, CC32xxMOD

The following microcontrollers are based on the Cortex-M4F (M4 + [[Floating-point unit|FPU]]) core:
* Analog Devices ADUCM4050
* [[Company:Cypress Semiconductor|Cypress]] 6200 (one Cortex-M4F + one Cortex-M0+), FM4
* Infineon XMC4000
* Maxim Darwin
* Microchip (Atmel) SAM4C (Dual core: one Cortex-M4F + one Cortex-M4), SAM4E, SAMG5, SAMD5/E5x
* [[Company:Nordic Semiconductor|Nordic]] nRF52
* [[Company:Nuvoton|Nuvoton]] NuMicro M480
* NXP LPC4000, LPC4300 (one Cortex-M4F + one Cortex-M0), LPC54000
* NXP (Freescale) Kinetis K, V3, V4
* Renesas S3, S5, S7, RA4, RA6
* [[Company:Silicon Labs|Silicon Labs]] ([[Company:Energy Micro|Energy Micro]]) [[Engineering:EFM32|EFM32 Wonder]]
* [[Company:STMicroelectronics|ST]] [[Engineering:STM32|STM32]] F3, F4, L4, L4+, G4, WB (one Cortex-M4F + one Cortex-M0+)
* [[Company:Texas Instruments|Texas Instruments]] LM4F, TM4C, [[Engineering:TI MSP432|MSP432]], CC13x2R, CC1352P, CC26x2R
* [[Company:Toshiba|Toshiba]] TX04

The following chips have either a Cortex-M4 or M4F as a secondary core:
* NXP (Freescale) Vybrid VF6 (one Cortex-A5 + one Cortex-M4F)
* NXP (Freescale) [[Engineering:I.MX|i.MX 6]] SoloX (one Cortex-A9 + one Cortex-M4F)
* NXP (Freescale) [[Engineering:I.MX|i.MX 7]] Solo/Dual (one or two Cortex-A7 + one Cortex-M4F)
* NXP (Freescale) [[Engineering:I.MX#i.MX 8 series|i.MX 8]] (two Cortex-A72 + four Cortex-A53 + two Cortex-M4F)
* NXP (Freescale) [[Engineering:I.MX#i.MX 8 series|i.MX 8M]] and 8M Mini (four Cortex-A53 + one Cortex-M4F)
* NXP (Freescale) [[Engineering:I.MX#i.MX 8 series|i.MX 8X]] (four Cortex-A35 + one Cortex-M4F)
* [[Company:STMicroelectronics|ST]] STM32MP1 (one or two Cortex-A7 + one Cortex-M4)
* [[Company:Texas Instruments|Texas Instruments]] [[Engineering:OMAP#OMAP 5|OMAP 5]] (two Cortex-A15s + two Cortex-M4)
* [[Company:Texas Instruments|Texas Instruments]] [[Engineering:Sitara ARM Processor|Sitara AM5700]] (one or two Cortex-A15s + two Cortex-M4s as image processing units + two Cortex-M4s as general purpose units)

==Cortex-M7==
{{Infobox CPU
|name = Cortex-M7
|arch = [[ARM architecture#Thumb|Thumb-1]], [[ARM architecture#Thumb-2|Thumb-2]],<br/>[[Saturation arithmetic|Saturated]], [[ARM architecture#DSP enhancement instructions|DSP]],<br/>Divide, [[ARM architecture#Floating-point (VFP)|FPU]] (SP & DP)
|microarch = ARMv7E-M
}}

The Cortex-M7 is a high-performance core with almost double the power efficiency of the older Cortex-M4. It features a 6-stage superscalar pipeline with [[Branch predictor|branch prediction]] and an optional floating-point unit capable of single-precision and optionally [[Double-precision floating-point format|double-precision]] operations.<ref>{{cite web |url=https://arm.com/products/processors/cortex-m/cortex-m7-processor.php |title=Cortex-M7 Processor | publisher=[[Company:Arm Holdings|Arm Holdings]] |access-date=2014-09-24}}</ref><ref name="M7-PressRelease">{{cite press release |url=https://arm.com/about/newsroom/arm-supercharges-mcu-market-with-high-performance-cortex-m7-processor.php |title=ARM Supercharges MCU Market with High Performance Cortex-M7 Processor |website=arm.com |date=September 24, 2014}}</ref>  The instruction and data buses have been enlarged to 64-bit wide over the previous 32-bit buses.  If a core contains an FPU, it is known as a Cortex-M7F, otherwise it is a Cortex-M7.

Key features of the Cortex-M7 core are:<ref name="M7-TRM">[https://developer.arm.com/documentation/ddi0489/latest/ Cortex-M7 Technical Reference Manual; Arm Holdings.]</ref>
* ARMv7E-M architecture.
* 6-stage [[Pipeline (computing)|pipeline]] with [[Branch predictor|branch speculation]]. Longest of all ARM Cortex-M cores.
* Instruction sets:
** Thumb-1 (entire).
** Thumb-2 (entire).
** 32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply. 32-bit Multiply and MAC are 1 cycle.
** 32-bit hardware integer divide (2–12 cycles).
** [[Saturation arithmetic]] support.
** DSP extension: Single cycle 16/32-bit [[Multiply–accumulate operation|MAC]], single cycle dual 16-bit MAC, 8/16-bit [[SIMD]] arithmetic.
* 1 to 240 [[Interrupt|interrupt]]s, plus [[Non-maskable interrupt|NMI]].
* 12 cycle interrupt latency.
* Integrated sleep modes.

'''Silicon options:'''
* Optional floating-point unit (FPU): (single precision) or (single and double-precision), both IEEE-754-2008 compliant. It is called the FPv5 extension.
* Optional [[CPU cache]]: 0 to 64&nbsp;KB instruction-cache, 0 to 64&nbsp;KB data-cache, each with optional [[ECC memory|ECC]].
* Optional Tightly-Coupled Memory (TCM): 0 to 16&nbsp;MB instruction-TCM, 0 to 16&nbsp;MB data-TCM, each with optional ECC.
* Optional Memory Protection Unit (MPU): 8 or 16 regions.
* Optional Embedded Trace Macrocell (ETM): instruction-only, or instruction and data.
* Optional Retention Mode (with Arm Power Management Kit) for Sleep Modes.

===Chips===
The following microcontrollers are based on the Cortex-M7 core:
* Microchip (Atmel) [[Engineering:Atmel ARM-based processors|SAM]] E7, S7, V7
* NXP ([[Company:Freescale Semiconductor|Freescale]]) Kinetis KV5x, i.MX RT
* [[Company:STMicroelectronics|ST]] [[Engineering:STM32|STM32]] F7, H7

==Cortex-M23==
{{Infobox CPU
|name = Cortex-M23
|arch = [[ARM architecture#Thumb|Thumb-1 (most)]],<br/>[[ARM architecture#Thumb-2|Thumb-2 (some)]],<br/>Divide, TrustZone
|microarch = ARMv8-M Baseline
}}

The Cortex-M23 core was announced in October 2016<ref name="Cortex-M23-M33-PR">[https://www.arm.com/files/pdf/cortex_m23_and_cortex_m33.pdf New ARM Cortex-M processors offer the next industry standard for secure IoT; Arm Holdings; October 25, 2016.]</ref> and based on the newer [[ARM architecture#ARMv8-R and ARMv8-M|ARMv8-M architecture]] that was previously announced in November 2015.<ref name="ARMv8-M-PR">[https://www.arm.com/about/newsroom/armv8-m-architecture-simplifies-security-for-smart-embedded-devices.php ARMv8-M Architecture Simplifies Security for Smart Embedded Devices; Arm Holdings; November 10, 2015.]</ref>  Conceptually the Cortex-M23 is similar to a Cortex-M0+ plus integer divide instructions and TrustZone security features, and also has a 2-stage instruction pipeline.

Key features of the Cortex-M23 core are:<ref name="M23-TRM">[http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf Cortex-M23 r1p0 Technical Reference Manual; Arm Holdings.]</ref><ref name="Cortex-M23-M33-PR"/>
* ARMv8-M Baseline architecture.<ref name="ARMv8-M-Manual"/>
* 2-stage pipeline. (similar to Cortex-M0+)
* TrustZone security instructions. (available only in M23/M33/M35P)
* 32-bit hardware integer divide (17 or 34 cycles). (not available in M0/M0+/M1) (slower than divide in all other cores)
* Stack limit boundaries. (available only with SAU option) (available in M23/M33/M35P)

'''Silicon options:'''
* Hardware integer multiply speed: 1 or 32 cycles.
* Hardware integer divide speed: 17 or 34 cycles maximum. Depending on divisor, instruction may complete in fewer cycles.
* Optional Memory Protection Unit (MPU): 0, 4, 8, 12, 16 regions.
* Optional Security Attribution Unit (SAU): 0, 4, 8 regions.
* Single-cycle I/O port (available in M0+/M23).
* Micro Trace Buffer (MTB) (available in M0+/M23/M33/M35P).

===Chips===
The following microcontrollers are based on the Cortex-M23 core:
* GigaDevice GD32E230
* [[Company:Microchip Technology|Microchip]] SAM L10, L11
* [[Company:Nuvoton|Nuvoton]] M2351
* Renesas S1JA, RA2A1, RA2L1, RA2E1, RA2E2

==Cortex-M33==
{{Infobox CPU
|name = Cortex-M33
|arch = [[ARM architecture#Thumb|Thumb-1]], [[ARM architecture#Thumb-2|Thumb-2]],<br/>[[Saturation arithmetic|Saturated]], [[ARM architecture#DSP enhancement instructions|DSP]],<br/>Divide, [[ARM architecture#Floating-point (VFP)|FPU]] (SP),<br/>TrustZone, Co-processor
|microarch = ARMv8-M Mainline
}}

The Cortex-M33 core was announced in October 2016<ref name="Cortex-M23-M33-PR"/> and based on the newer [[ARM architecture|ARMv8-M architecture]] that was previously announced in November 2015.<ref name="ARMv8-M-PR"/>  Conceptually the Cortex-M33 is similar to a cross of Cortex-M4 and Cortex-M23, and also has a 3-stage instruction pipeline.

Key features of the Cortex-M33 core are:<ref name="M33-TRM">[http://infocenter.arm.com/help/topic/com.arm.doc.100230_0003_00_en/cortex_m33_trm_100230_0003_00_en.pdf Cortex-M33 r0p3 Technical Reference Manual; Arm Holdings.]</ref><ref name="Cortex-M23-M33-PR"/>
* ARMv8-M Mainline architecture.<ref name="ARMv8-M-Manual"/>
* 3-stage pipeline.
* TrustZone security instructions. (available only in M23/M33/M35P)
* 32-bit hardware integer divide (11 cycles maximum). (not available in M0/M0+/M1)
* Stack limit boundaries. (available only with SAU option) (available in M23/M33/M35P)

'''Silicon options:'''
* Optional Floating-Point Unit (FPU): single-precision only IEEE-754 compliant. It is called the FPv5 extension.
* Optional Memory Protection Unit (MPU): 0, 4, 8, 12, 16 regions.
* Optional Security Attribution Unit (SAU): 0, 4, 8 regions.
* Micro Trace Buffer (MTB) (available in M0+/M23/M33/M35P).

===Chips===
The following microcontrollers are based on the Cortex-M33 core:
* Analog Devices ADUCM410, ADUCM420
* Dialog DA1469x
* GigaDevice GD32E50x, GD32W515
* [[Company:Nordic Semiconductor|Nordic]] nRF91, nRF5340
* NXP LPC5500, i.MX RT600
* Renesas RA4, RA6
* [[Company:STMicroelectronics|ST]] [[Engineering:STM32|STM32]] L5, U5
* [[Company:Silicon Labs|Silicon Labs]] Wireless Gecko Series 2

==Cortex-M35P==
{{Infobox CPU
|name = Cortex-M35P
|arch = [[ARM architecture#Thumb|Thumb-1]], [[ARM architecture#Thumb-2|Thumb-2]],<br/>[[Saturation arithmetic|Saturated]], [[ARM architecture#DSP enhancement instructions|DSP]],<br/>Divide, [[ARM architecture#Floating-point (VFP)|FPU]] (SP),<br/>TrustZone, Co-processor
|microarch = ARMv8-M Mainline
}}

The Cortex-M35P core was announced in May 2018. It is conceptually a Cortex-M33 core with a new instruction cache, plus new tamper-resistant hardware concepts borrowed from the ARM SecurCore family, and configurable parity and ECC features.<ref>{{cite web |url=https://developer.arm.com/products/processors/cortex-m/cortex-m35p |title=Cortex-M35P Processor | publisher=[[Company:Arm Holdings|Arm Holdings]] |access-date=2018-06-04}}</ref>

Limited public information is currently available for the Cortex-M35P until its ''Technical Reference Manual'' is released.

===Chips===
The following microcontrollers are based on the Cortex-M35P core:
* As of July 2021, no chips have been announced.

{{clear}}

==Cortex-M55==
{{Infobox CPU
|name = Cortex-M55
|arch = [[ARM architecture#Thumb|Thumb-1]], [[ARM architecture#Thumb-2|Thumb-2]],<br/>[[Saturation arithmetic|Saturated]], [[ARM architecture#DSP enhancement instructions|DSP]],<br/>Divide, [[ARM architecture#Floating-point (VFP)|FPU]] (VFPv5),<br/>TrustZone, Coprocessor, MVE
|microarch = ARMv8.1-M Mainline Helium
}}

The Cortex-M55 core was announced in February 2020 and is based on the [[ARM architecture|Armv8.1-M architecture]] that was previously announced in February 2019. It also has a 4-stage instruction pipeline. 

Key features of the Cortex-M55 core include:
* ARMv8.1-M Mainline/Helium architecture.<ref name="ARMv8-M-Manual"/>
* 4-stage pipeline.
* Stack limit boundaries (available only with SAU option).

'''Silicon options:'''
* Helium (M-Profile Vector Extension, MVE)
* Single-Precision and Double-Precision floating-point
* Digital Signal Processing (DSP) extension support
* TrustZone security extension support
* Safety and reliability (RAS) support
* Coprocessor support
* Secure and Non-secure MPU with 0, 4, 8, 12, or 16 regions
* SAU with 0, 4, or 8 regions
* Instruction cache with size of 4KB, 8KB, 16KB, 32KB, 64KB
* Data cache with size of 4KB, 8KB, 16KB, 32KB, 64KB
* ECC on caches and TCMs
* 1–480 interrupts
* 3–8 exception priority bits
* Internal and external WIC options, optional CTI, ITM, and DWT
* ARM Custom Instructions (available in a future release)

===Chips===
* [https://alifsemi.com/products/ Alif Semiconductor] Ensemble and Crescendo MCU families offer single or dual Cortex-M55 cores, each paired with Ethos-U55 NPUs

==Development tools==
[[File:Segger J-Link PRO.jpg|thumb|right|Segger J-Link PRO. Debug probe with SWD or [[JTAG|JTAG]] interface to target ARM chip, and USB or [[Ethernet|Ethernet]] interfaces to host computer.]]
{{Main article|Engineering:List of ARM Cortex-M development tools}}

==Documentation==
The documentation for ARM chips is extensive.  In the past, 8-bit microcontroller documentation would typically fit in a single document, but as microcontrollers have evolved, so has everything required to support them.  A documentation package for ARM chips typically consists of a collection of documents from the IC manufacturer as well as the CPU core vendor ([[Company:Arm Holdings|Arm Holdings]]).

A typical top-down documentation tree is:

;Documentation tree (top to bottom)
# IC manufacturer website.
# IC manufacturer marketing slides.
# IC manufacturer datasheet for the exact physical chip.
# IC manufacturer reference manual that describes common peripherals and aspects of a physical chip family.
# ARM core website.
# ARM core generic user guide.
# ARM core technical reference manual.
# ARM architecture reference manual.

IC manufacturers have additional documents, such as: evaluation board user manuals, application notes, getting started guides, software library documents, errata, and more. See External links section for links to official Arm documents.

==See also==
* [[ARM architecture]]
* [[Engineering:List of ARM microarchitectures|List of ARM architectures and cores]]
* JTAG, SWD
* [[Interrupt]], [[Interrupt handler]]
* [[Real-time operating system]], [[Software:Comparison of real-time operating systems|Comparison of real-time operating systems]]

==References==
{{Reflist|30em}}

==Further reading==<!-- Note: this section name is linked from [[Engineering:List of ARM Cortex-M development tools|List of ARM Cortex-M development tools]] -->
* ''Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C''; 3rd Ed; Yifeng Zhu; 738 pages; 2017; {{ISBN|978-0982692660}}.
* ''Designer's Guide to the Cortex-M Processor Family''; 2nd Ed; Trevor Martin; 490 pages; 2016; {{ISBN|978-0081006290}}.
* ''ARM Assembly for Embedded Applications''; 3rd Ed; Daniel Lewis; 318 pages; 2017; {{ISBN|978-1543908046}}.
* ''Definitive Guide to the ARM Cortex-M0 and Cortex-M0+ Processors''; 2nd Ed; Joseph Yiu; 784 pages; 2015; {{ISBN|978-0128032770}}.
* ''Definitive Guide to the ARM Cortex-M3 and Cortex-M4 Processors''; 3rd Ed; Joseph Yiu; 600 pages; 2013; {{ISBN|978-0124080829}}.
* ''Digital Signal Processing and Applications Using the ARM Cortex-M4''; 1st Ed; Donald Reay; 250 pages; 2014; {{ISBN|978-1118859049}}.
* ''Embedded Systems: Introduction to ARM Cortex-M Microcontrollers''; 5th Ed; Jonathan Valvano; 506 pages; 2012; {{ISBN|978-1477508992}}.
* ''Assembly Language Programming: ARM Cortex-M3''; 1st Ed; Vincent Mahout; 256 pages; 2012; {{ISBN|978-1848213296}}.

==External links==
;ARM Cortex-M official documents
* [https://community.arm.com/cfs-file/__key/telligent-evolution-components-attachments/01-2142-00-00-00-00-52-96/White-Paper-_2D00_-Cortex_2D00_M-for-Beginners-_2D00_-2016-_2800_final-v3_2900_.pdf Cortex-M for Beginners]{{snd}} arm.com
* [http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf ARMv8-M Security Extensions]{{snd}} arm.com
* [https://arm-software.github.io/CMSIS_5/Core/html/index.html Cortex Microcontroller Software Interface Standard (CMSIS)]{{snd}} arm.com

:{| class="wikitable"
|-
! ARM<br/>core !! Bit<br/>width !! ARM<br/>website !! ARM generic<br/>user guide !! ARM technical<br/>reference manual !! ARM architecture<br/>reference manual
|-
| style="background: LightCyan; text-align: center;" | Cortex-M0 || style="text-align: center;" | 32 || style="text-align: center;" | [https://developer.arm.com/ip-products/processors/cortex-m/cortex-m0 Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf Link] || style="text-align: center;" | [https://developer.arm.com/documentation/ddi0419/latest/ ARMv6-M]
|-
| style="background: LightCyan; text-align: center;" | Cortex-M0+ || style="text-align: center;" | 32 || style="text-align: center;" | [https://developer.arm.com/ip-products/processors/cortex-m/cortex-m0-plus Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0484c/DDI0484C_cortex_m0p_r0p1_trm.pdf Link] || style="text-align: center;" | ARMv6-M
|-
| style="background: LightCyan; text-align: center;" | Cortex-M1 || style="text-align: center;" | 32 || style="text-align: center;" | [https://developer.arm.com/ip-products/processors/cortex-m/cortex-m1 Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.dui0395b/DUI0395B_cortex_m1_fpga_dk_user_guide_altera.pdf Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0413d/DDI0413D_cortexm1_r1p0_trm.pdf Link] || style="text-align: center;" | ARMv6-M
|-
| style="background: LightCyan; text-align: center;" | Cortex-M3 || style="text-align: center;" | 32 || style="text-align: center;" | [https://developer.arm.com/ip-products/processors/cortex-m/cortex-m3 Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.100165_0201_00_en/arm_cortexm3_processor_trm_100165_0201_00_en.pdf Link] || style="text-align: center;" |[https://documentation-service.arm.com/static/606dc36485368c4c2b1bf62f?token= ARMv7-M]
|-
| style="background: LightCyan; text-align: center;" | Cortex-M4 || style="text-align: center;" | 32 || style="text-align: center;" | [https://developer.arm.com/ip-products/processors/cortex-m/cortex-m4 Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.dui0553b/DUI0553.pdf Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.100166_0001_00_en/arm_cortexm4_processor_trm_100166_0001_00_en.pdf Link] || style="text-align: center;" | ARMv7E-M
|-
| style="background: LightCyan; text-align: center;" | Cortex-M7 || style="text-align: center;" | 32 || style="text-align: center;" | [https://developer.arm.com/ip-products/processors/cortex-m/cortex-m7 Link] || style="text-align: center;" | [https://developer.arm.com/documentation/dui0646/latest/ Link] || style="text-align: center;" | [https://developer.arm.com/documentation/ddi0489/latest/ Link] || style="text-align: center;" | ARMv7E-M
|-
| style="background: LightCyan; text-align: center;" | Cortex-M23 || style="text-align: center;" | 32 || style="text-align: center;" | [https://developer.arm.com/ip-products/processors/cortex-m/cortex-m23 Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.dui1095a/DUI1095A_cortex_m23_dgug.pdf Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf Link] || style="text-align: center;" | [https://developer.arm.com/documentation/ddi0553/latest/ ARMv8-M]
|-
| style="background: LightCyan; text-align: center;" | Cortex-M33 || style="text-align: center;" | 32 || style="text-align: center;" | [https://developer.arm.com/ip-products/processors/cortex-m/cortex-m33 Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.100235_0004_00_en/arm_cortex_m33_dgug_100235_0004_00_en.pdf Link] || style="text-align: center;" | [http://infocenter.arm.com/help/topic/com.arm.doc.100230_0004_00_en/cortex_m33_trm_100230_0004_00_en.pdf Link] || style="text-align: center;" | ARMv8-M
|-
| style="background: LightCyan; text-align: center;" | Cortex-M35P || style="text-align: center;" | 32 || style="text-align: center;" | [https://developer.arm.com/ip-products/processors/cortex-m/cortex-m35p Link] || {{n/a|TBD}} || {{n/a|TBD}} || style="text-align: center;" | ARMv8-M
|-
| style="background: LightCyan; text-align: center;" | Cortex-M55 || style="text-align: center;" | 32 || style="text-align: center;" | [https://developer.arm.com/ip-products/processors/cortex-m/cortex-m55 Link] || {{n/a|TBD}} || {{n/a|TBD}} || style="text-align: center;" | ARMv8.1-M
|}

;Quick reference cards
* Instructions: Thumb-1 ([http://infocenter.arm.com/help/topic/com.arm.doc.qrc0006e/QRC0006_UAL16.pdf 1]), ARM and Thumb-2 ([http://infocenter.arm.com/help/topic/com.arm.doc.qrc0001m/QRC0001_UAL.pdf 2]), Vector Floating-Point ([http://infocenter.arm.com/help/topic/com.arm.doc.qrc0007e/QRC0007_VFP.pdf 3]){{snd}} arm.com
* Opcodes: Thumb-1 ([https://re-eject.gbadev.org/files/ThumbRefV2-beta.pdf 1], [http://www.mechcore.net/files/docs/ThumbRefV2-beta.pdf 2]), ARM ([https://re-eject.gbadev.org/files/armref.pdf 3], [http://www.mechcore.net/files/docs/armref.pdf 4]), GNU Assembler Directives ([https://re-eject.gbadev.org/files/GasARMRef.pdf 5]).

;Migrating
* [http://infocenter.arm.com/help/topic/com.arm.doc.dai0237a/DAI0237A_migrating_from_8051_to_Cortex_M.pdf Migrating from 8051 to Cortex-M3] – arm.com
* [http://infocenter.arm.com/help/topic/com.arm.doc.dai0234a/DAI0234A_migrating_from_pic_to_m3.pdf Migrating from PIC to Cortex-M3] – arm.com
* [https://www.arm.com/zh/files/pdf/Cortex-M3_programming_for_ARM7_developers.pdf Migrating from ARM7TDMI to Cortex-M3] – arm.com
* [https://www.keil.com/appnotes/files/apnt_270.pdf Migrating from Cortex-M4 to Cortex-M7] – keil.com

;Other
* [https://micromouseonline.com/2010/07/14/bit-banding-in-the-stm32/ Bit Banding on STM32 Cortex-M microcontrollers]

{{Clear}}
{{Classic ARM-based chips}}
{{Microcontrollers}}
{{Programmable Logic}}
{{Clear}}

[[Category:ARM architecture|Cortex-M]]
[[Category:ARM cores]]

{{Sourceattribution|ARM Cortex-M|1}}