View source for Engineering:Blackfin

{{Infobox CPU architecture
| name           = Blackfin
| designer       = Analog Devices
| bits           = 32-bit
| introduced     = {{Start date and age|2000}}
| version        = 
| design         = RISC
| type           = Register-Register
| encoding       = [[Very long instruction word|Variable]] <small>(16- or 32-bit general purpose, or 64-bit parallel issue of 1 × 32-bit instruction + 2 × 16-bit instructions)</small>
| branching      = Condition code
| endianness     = Little
| extensions     =
| open           =
| registers      = 
| gpr            = 8 × 32-bit data registers (addressable as 16 × 16-bit half-registers), 2 × 40-bit accumulators, 6 × 32-bit address registers, stack pointer, frame pointer
| fpr            = 
}}
{{Infobox CPU
| name           = Blackfin
| image          = blackfin-processor-logo.png
| image_size     = 180px
| caption        = ADI Blackfin Logo
| produced-start = 2008
| produced-end   = Present
| slowest        = 
| fastest        = 
| slow-unit      = 
| fast-unit      = 
| fsb-slowest    =
| fsb-fastest    =
| fsb-slow-unit  =
| fsb-fast-unit  =
| size-from      =
| size-to        =
| soldby         = Analog Devices
| designfirm     = Analog Devices
| manuf1         = Analog Devices
| core1          =
| sock1          =
| pack1          =
| arch           =
| microarch      =
| numcores       =
}}

The '''Blackfin''' is a family of 16-/32-bit [[Engineering:Microprocessor|microprocessor]]s developed, manufactured and marketed by Analog Devices. The processors have built-in, fixed-point [[Engineering:Digital signal processor|digital signal processor]] (DSP) functionality supplied by 16-bit multiply–accumulates (MACs), accompanied on-chip by a [[Engineering:Microcontroller|microcontroller]].<ref>{{cite web|url=http://www.analog.com/en/processors-dsp/Blackfin/processors/Blackfin_architecture/fca.html |title=Blackfin Processor Architecture Overview &#124; Blackfin Processors &#124; Processors and DSP &#124; Analog Devices |access-date=April 9, 2011 |url-status=dead |archive-url=https://web.archive.org/web/20110417200815/http://www.analog.com/en/processors-dsp/Blackfin/processors/Blackfin_architecture/fca.html |archive-date=April 17, 2011 }}</ref> It was designed for a unified low-power processor architecture that can run [[Operating system|operating system]]s while simultaneously handling complex numeric tasks such as [[Real-time computer graphics|real-time]] H.264 video encoding.<ref>{{cite web|url=http://www.analog.com/en/dsp-software/bf_h264_bp_encoder/sw.html |title=H.264 BP/MP Encoder |publisher=Analog Devices |access-date=2014-09-03}}</ref><ref>{{cite web|url=http://www.analog.com/en/dsp-software/bf_h264_bp_decoder/sw.html |title=H.264 BP/MP Decoder Library |publisher=Analog Devices |access-date=2014-09-03}}</ref>

==Architecture details==
Blackfin processors use a [[32-bit|32-bit]] [[Reduced instruction set computer|RISC]] [[Engineering:Microcontroller|microcontroller]] programming model on a [[SIMD]] architecture, which was co-developed by [[Company:Intel|Intel]] and Analog Devices, as MSA (Micro Signal Architecture).

The architecture was announced in December 2000, and first demonstrated at the Embedded Systems Conference in June, 2001.

It incorporates aspects of ADI's older [[Engineering:Super Harvard Architecture Single-Chip Computer|SHARC]] architecture and Intel's [[Engineering:XScale|XScale]] architecture into a single core, combining digital signal processing (DSP) and microcontroller functionality. There are many differences in the core architecture between Blackfin/MSA and XScale/ARM or SHARC, but the combination was designed to improve performance, programmability and power consumption over traditional DSP or RISC architecture designs.

The Blackfin architecture encompasses various CPU models, each targeting particular applications.<ref>{{cite web|url=http://www.analog.com/en/processors-dsp/blackfin/products/index.html#blackfin |title=Blackfin Processors &#124; Analog Devices |website=Analog.com |access-date=2016-06-24}}</ref> The BF-7xx series, introduced in 2014, comprise the Blackfin+ architecture, which expands on the Blackfin architecture with some new processor features and instructions.

==Architecture features==

===Core features===
[[File:Siglent 1000X Series Oscilloscope Teardown (21642956565) (cropped) ADSP-BF526 BBCZ-4A.jpg|thumb|mounted Blackfin BF526 in an Agilent oscilloscope]]

What is regarded as the Blackfin "core" is contextually dependent. For some applications, the [[Engineering:Digital signal processor|DSP]] features are central. Blackfin has two 16-bit hardware MACs, two 40-bit [[Arithmetic logic unit|ALU]]s and [[Accumulator (computing)|accumulator]]s, a 40-bit [[Barrel shifter|barrel shifter]], and four 8-bit video ALUs; Blackfin+ processors add a 32-bit MAC and 72-bit accumulator. This allows the processor to execute up to three instructions per clock cycle, depending on the level of optimization performed by the [[Compiler|compiler]] or [[Programmer|programmer]]. Two nested [[Zero-overhead looping|zero-overhead loops]] and four circular buffer DAGs (data address generators) are designed to assist in writing efficient code requiring fewer instructions. Other applications use the RISC features, which include memory protection, different operating modes (user, kernel), single-cycle [[Opcode|opcode]]s, data and instruction caches, and instructions for bit test, byte, word, or integer accesses and a variety of on-chip peripherals.

The ISA is designed for a high level of [[Expressive power (computer science)|expressiveness]], allowing the assembly programmer (or [[Compiler|compiler]]) to optimize an algorithm for the hardware features present. The standard Blackfin assembly language is written using an algebraic syntax: instead of prefix commands used in many other assembly languages.
{{aligned table|cols=2|class=wikitable|row1header=y|Other assembly languages|Blackfin assembly language
|3={{code|ld R0, 8[P0]|asm}}|5={{code|add R0, R1, R2|asm}}|7={{code|push R7|asm}}|4=<code>R0 = [P0 + 8]</code>|6=<code>R0 = R1 + R2</code>|8=<code>[SP--] = R7</code>}}

===Memory and DMA===
The Blackfin uses a byte-addressable, flat [[Memory map|memory map]].  Internal L1 memory, internal L2 memory, external memory and all memory-mapped [[Control register|control register]]s reside in this 32-bit address space, so that from a programming point of view, the Blackfin has a [[Von Neumann architecture]].

The L1 internal SRAM memory, which runs at the core-clock speed of the device, is based on a [[Harvard architecture]].  Instruction memory and data memory are independent and connect to the core via dedicated memory buses, designed for higher sustained [[Throughput|data rate]]s between the core and L1 memory.

Portions of instruction and data L1 SRAM can be optionally configured as cache independently.

Certain Blackfin processors also have between 64KB and 256KB of L2 memory.  This memory runs slower than the core clock speed.  Code and data can be mixed in L2.

Blackfin processors support a variety of external memories including SDRAM, DDR-SDRAM, NOR flash, NAND flash and [[Static random-access memory|SRAM]].  Some Blackfin processors also include mass-storage interfaces such as [[ATAPI]] and SD/SDIO.  They can support hundreds of megabytes of memory in the external memory space.

Coupled with the core and memory system is a [[Direct memory access|DMA]] engine that can operate between any of its [[Engineering:Peripheral|peripheral]]s and main (or external) memory. The processors typically have a dedicated DMA channel for each peripheral, which is designed for higher [[Throughput|throughput]] for applications that can use it, such as real-time standard-definition (D1) video encoding and decoding.

===Microcontroller features===
The architecture of Blackfin contains the usual CPU, memory, and I/O that is found on [[Engineering:Microprocessor|microprocessor]]s or [[Engineering:Microcontroller|microcontroller]]s.  These features enable operating systems.

All Blackfin processors contain a [[Memory protection|Memory Protection Unit]] (MPU). The MPU provides protection and caching strategies across the entire memory space. The MPU allows Blackfin to support operating systems, RTOSs and kernels like [[Software:ThreadX|ThreadX]], μC/OS-II, or NOMMU Linux. Although the MPU is referred to as a [[Memory management unit|Memory Management Unit]] (MMU) in the Blackfin documentation, the Blackfin MPU does not provide address translation like a traditional MMU, so it does not support [[Virtual memory|virtual memory]] or separate memory addresses per process. This is why Blackfin currently can not support operating systems requiring virtual memory such as WinCE or [[QNX]].

Blackfin supports three [[Protection ring|run-time modes]]: supervisor, user and emulation. In supervisor mode, all processor resources are accessible from the running process. However, when in user mode, system resources and regions of memory can be protected (with the help of the MPU). In a modern operating system or RTOS, the kernel typically runs in supervisor mode and threads/processes will run in user mode. If a thread crashes or attempts to access a protected resource (memory, peripheral, etc.) an [[Exception handling|exception]] will be thrown and the kernel will then be able to shut down the offending thread/process. The official guidance from ADI on how to use the Blackfin in non-OS environments is to reserve the lowest-priority interrupt for general-purpose code so that all software is run in supervisor space.

Blackfin uses a variable-length RISC-like instruction set consisting of 16-, 32- and 64-bit instructions. Commonly used control instructions are encoded as 16-bit opcodes while complex DSP and mathematically intensive functions are encoded as 32- and 64-bit opcodes. This variable length opcode encoding is designed for code density equivalence to modern microprocessor architectures.

===Media-processing features===
The Blackfin instruction set contains media-processing extensions to help accelerate pixel-processing operations commonly used in video compression and [[Image compression|image compression]] and decompression algorithms.

==Peripherals==
Blackfin processors contain an array of connectivity peripherals, depending on the specific processor:

* [[ATAPI]]
* CAN: A wide-area, low-speed serial bus used in some automotive and industrial electronics
* [[Direct memory access|DMA]] with support for memory-to-memory DMA and peripheral DMA
* EMAC ([[Ethernet]] Media Access Controller) with [[Media-independent interface|MII]] and [[Media-independent interface#Reduced media-independent interface|RMII]]
* External memory: the EBIU (External Bus Interface Unit) can include a controller for SDRAM, Mobile SDRAM, DDR1, DDR2, or LPDDR, and an asynchronous memory controller for SRAM, ROM, flash EPROM, and memory-mapped I/O devices
* GPIO including level-triggered and edge-triggered interrupts
* [[I²C]], also known as TWI (Two-Wire Interface): a lower speed, shared serial bus
* MXVR: a MOST Network Interface Controller
* NAND flash
* [[Engineering:Parallel Peripheral Interface|PPI]]: A parallel input/output port that can be used to connect to LCDs, video encoders (video DACs), video decoders (video ADCs), CMOS sensors, CCDs and generic, parallel, high-speed devices.  The PPI can run up to 75&nbsp;MHz and can be configured from 8 to 16-bits wide.
* [[Pulse-width modulation|PWM]] and timers/counters
* Real time clock
* SD/SDIO
* [[Serial Peripheral Interface|SPI]]: a fast serial bus used in some high-speed embedded electronics applications
* SPORT: A synchronous, high speed serial port that can support [[Time-division multiplexing|TDM]], I²S and a number of other configurable framing modes for connection to [[Analog-to-digital converter|ADCs]], [[Digital-to-analog converter|DACs]], other processors, FPGAs, etc.
* UART: allows for bi-directional communication with RS232 devices (PCs, modems, PC peripherals, etc.), [[MIDI]] devices, [[Organization:Infrared Data Association|IRDA]] devices
* USB 2.0 OTG (On-The-Go)
* [[Watchdog timer]]

All of the peripheral control registers are memory-mapped in the normal address space.

==Development tools==
[[Image:Blackfin 537 EZ-Kit-Lite61.jpg|thumb|none|Blackfin BF537 EZ-Kit-Lite evaluation platform]]

ADI provides its own software development toolchains. The original VisualDSP++ [[Integrated development environment|IDE]] is still supported (its last release was 5.1.2 in {{Start date and age|2014|10}}), but is approaching end of life and has not had support added for the new BF6xx and BF7xx processors. The newer toolchain is CrossCore Embedded Studio, which uses supports all Blackfin and Blackfin+ processors using upgraded versions of the same compiler and tools internally, but with a UI based on [[Software:Eclipse|Eclipse CDT]]. No free version of either tool is available; a single-user license for VisualDSP++ costs $3500 USD, and CrossCore Embedded Studio $995 USD.

Other options include [[Company:Green Hills Software|Green Hills Software]]'s MULTI IDE and the GNU [[Software:GNU Compiler Collection|GCC]] Toolchain for the Blackfin processor family. However, like VisualDSP++, these have not been updated to support the newer BF6xx and BF7xx processors. Moreover, neither support all BF5xx processors. Green Hills MULTI lacks support for BF50x, BF51x, some BF52x, BF547, and BF59x. GCC lacks support for BF50x, BF566, and BF59x, and has incomplete support for BF561.

Blackfin is also supported by National Instruments' [[Software:LabVIEW|LabVIEW]] Embedded Module, which requires VisualDSP++.

==Supported operating systems, RTOSs and kernels==
Several commercial and open-source operating systems support running on Blackfin.

{| class="wikitable"
|+OS/RTOS/Kernels on Blackfin
!Title || License !! Comments
|-
| [[Software:ThreadX|ThreadX]]<ref>{{cite web |url=http://rtos.com/products/threadx/BlackFin |title=Real-Time Operating Systems for Embedded Development, Real Time System By Express Logic |website=Rtos.com |access-date=2016-06-24 |url-status=dead |archive-url=https://web.archive.org/web/20160523203201/http://rtos.com/products/threadx/BlackFin |archive-date=2016-05-23 }}</ref> || {{proprietary}} ||
|-
| [[Software:Nucleus RTOS|Nucleus]] ||  {{proprietary}}  ||
|-
| μC/OS-II<ref>{{cite web|url=http://micrium.com/rtos/ucosii/ports/ |title=Real-Time Kernels |website=Micrium.com |access-date=2016-06-24}}</ref> || {{proprietary}} ||
|-
| [[Software:Integrity (operating system)|INTEGRITY]]<ref>{{cite web|url=http://www.ghs.com/products/rtos/integrity.html#reliability |title=INTEGRITY Real-time Operating System |website=Ghs.com |access-date=2016-06-24}}</ref> || {{proprietary}} ||
|-
| [[Software:RTEMS|RTEMS]] || {{free|[[Software:BSD licenses#2-clause license ("Simplified BSD License" or "FreeBSD License")|BSD-2 Clause and Permissive]]}}  ||
|-
| [[RTXC Quadros]] || {{proprietary}} ||
|-
| VDK || {{proprietary}} ||  ADI's real-time kernel.  Ships with VisualDSP++.
|-
| .NET Micro Framework|| {{free|[[Software:Apache License 2.0|Apache License 2.0]]}} || Stand-alone version from Microsoft. Integrated version from AxiomFount.
|}

Blackfin was previously supported by [[Software:ΜClinux|μClinux]] and later by [[Software:Linux|Linux]] with the NOMMU feature, but as it was not ever widely used and no longer had a maintainer,<ref>[http://lkml.iu.edu/hypermail/linux/kernel/1712.3/00268.html] MAINTAINERS: mark arch/blackfin/ and its gubbins as orphaned</ref><ref>[http://lkml.iu.edu/hypermail/linux/kernel/1801.1/04345.html] RE: MAINTAINERS: mark arch/blackfin/ and its gubbins as orphaned</ref> support was removed from Linux on April 1, 2018; 4.16 was the last release to include Blackfin support.<ref>[http://lkml.iu.edu/hypermail/linux/kernel/1804.0/00306.html] arch: remove obsolete architecture ports</ref><ref>{{cite web|url=https://www.theregister.co.uk/2018/04/03/linux_4_16_released/ |title=Linux 4.16 arrives, erases eight CPUs |author=Simon Sharwood |website=theregister.co.uk |date=2018-04-03 |access-date=2018-04-03}}</ref><ref>{{cite web|url=https://lkml.org/lkml/2018/4/2/72|title=[GIT PULL] arch: remove obsolete architecture ports|author=Arnd Bergmann|website=LKML|date=2018-04-03|access-date=2018-04-04}}</ref>

==See also==
*[[Engineering:Super Harvard Architecture Single-Chip Computer|SHARC]]
*[[Engineering:TigerSHARC|TigerSHARC]]

==References==
{{Reflist}}

==External links==
*[http://www.analog.com/en/processors-dsp/blackfin/products/index.html Blackfin processor website]
*[http://www.analog.com/media/en/dsp-documentation/processor-manuals/Blackfin_pgr_rev2.2.pdf Blackfin Processor Programming Reference]
*[http://blackfin.uclinux.org/ blackfin.uclinux.org] Open source tools and Linux kernel for Blackfin
*[http://www.t2-project.org/architectures/blackfin.html T2 SDE] A build-system supporting the cross compilation to Blackfin

{{RISC-based processor architectures}}

[[Category:Instruction set architectures]]
[[Category:Microcontrollers]]
[[Category:Digital signal processors]]

{{Sourceattribution|Blackfin}}