View source for Engineering:List of AMD processors with 3D graphics

{{Short description|None}}
This is a list of microprocessors designed by [[Engineering:AMD|AMD]] containing a 3D integrated graphics processing unit (iGPU), including those under the [[Engineering:AMD APU|AMD APU]] (Accelerated Processing Unit) product series.

== Features overview ==
{{AMD APU features}}

== Graphics API overview ==
{{AMD graphics API support}}

==Desktop processors with 3D graphics==
=== APU or Radeon Graphics branded ===
==== Lynx: "Llano" (2011) ====
* Socket [[Engineering:Socket FM1|FM1]]
* CPU: [[Engineering:AMD 10h|K10]] (also ''Husky'' or ''K10.5'') cores with an upgraded ''Stars'' architecture, no L3 cache
** L1 cache: 64 KB Data per core and 64 KB Instruction cache per core
** L2 cache: 512 KB on dual-core, 1 MB on tri- and quad-core models
** ''[[MMX (instruction set)|MMX]], [[Engineering:3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], SSE4a, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], AMD64, [[Engineering:Cool'n'Quiet|Cool'n'Quiet]]'', ''AMD-V''
* GPU: TeraScale 2 (Evergreen); all A and E series models feature ''Redwood''-class integrated graphics on die (''BeaverCreek'' for the dual-core variants and ''WinterPark'' for the quad-core variants). Sempron and Athlon models exclude integrated graphics.<ref name="athlon">{{cite web |url=http://www.cpu-world.com/news_2011/2011081701_AMD_launches_A-Series_and_the_first_32nm_Athlon_II_X4_CPUs.html |title=AMD launches A-Series and the first 32nm Athlon II X4 CPUs |access-date=November 10, 2013}}</ref>
* [[Engineering:List of AMD graphics processing units#IGP (HD 6000)|List of embedded GPU's]]
* Support for up to four DIMMs of up to DDR3-1866 memory
* [[Engineering:Semiconductor device fabrication|Fabrication]] 32&nbsp;nm on [[Company:GlobalFoundries|GlobalFoundries]] [[Physics:Silicon on insulator|SOI]] process; [[Engineering:Die (integrated circuit)|Die]] size: {{val|228|u=mm2}}, with 1.178 billion transistors<ref>{{cite web |url= http://www.brightsideofnews.com/news/2012/5/28/amd-comes-clean-on-transistor-numbers-with-fx2c-fusion-processors.aspx |title= AMD Comes Clean on Transistor Numbers With FX, Fusion Processors |author= Theo Valich |date= May 28, 2012 |access-date= August 23, 2013}}</ref><ref name="AnandTech_TrinityReview">{{cite web |url=http://www.anandtech.com/show/6332/amd-trinity-a10-5800k-a8-5600k-review-part-1 |title=AMD A10-5800K & A8-5600K Review: Trinity on the Desktop, Part 1 |author= Anand Lal Shimpi |date= September 27, 2012 |access-date= August 23, 2013}}</ref>
* 5&nbsp;GT/s UMI
* Integrated PCIe 2.0 controller
* Select models support Turbo Core technology for faster CPU operation when the thermal specification permits
* Select models support Hybrid Graphics technology to assist a discrete Radeon HD 6450, 6570, or 6670 discrete graphics card. This is similar to the Hybrid CrossFireX technology available in the AMD 700 and 800 chipset series
{| class="wikitable" style="text-align:center;"
|-
! rowspan="3" | Model{{NoteTag|name=fn_4|Models with "K" suffixes feature an unlocked multiplier and overclockable GPU.}}
! rowspan="3" | Released
! rowspan="3" | [[Engineering:Semiconductor device fabrication|Fab]]
! rowspan="3" | [[Engineering:Stepping level|Step.]]
! colspan="5" | [[Central processing unit|CPU]]
! colspan="4" | [[Graphics processing unit|GPU]]
! rowspan="3" | DDR3<br />memory<br />support
! rowspan="3" | [[Thermal design power|TDP]]<br />(W)
! rowspan="3" | Box number
! rowspan="3" | Part number
|-
! rowspan="2" | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]
! colspan="2" | [[Clock rate]] ([[Hertz|GHz]])
! colspan="2" | [[Cache (computing)|Cache]]{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945">{{cite web |url=http://developer.amd.com/wordpress/media/2017/11/54945_PPR_Family_17h_Models_00h-0Fh.pdf |title=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors |work=AMD Technical Documentation |location=AMD Developer Central |publisher=Advanced Micro Devices, Inc. |date=April 15, 2017 |page=25 |access-date=November 1, 2019 }}</ref>}}
! rowspan="2" | Model
! rowspan="2" | Config
! rowspan="2" | Clock<br />(MHz)
! rowspan="2" | Processing<br />power<br />([[FLOPS|GFLOPS]]){{efn|name="SFLOPS"}}
|-
! Base
! Boost
! L1
! L2
|-
! {{rh}} | {{nowrap|Sempron X2 198}}
| 2012
| rowspan=21 |32&nbsp;nm SOI
| rowspan=21 | LN-B0
| rowspan=2 | 2 (2)
| 2.5
| rowspan=12 {{N/a}}
| rowspan=21 | 64&nbsp;KB inst.<br />64&nbsp;KB data<br /><br />per core
| rowspan=2 | 2×512&nbsp;KB
| rowspan=8 colspan=4 {{N/a}}
| rowspan=2 | 1600
| rowspan=3 | 65
| SD198XOJGXBOX
| SD198XOJZ22GX
|-
! {{rh}} | {{nowrap|Athlon II X2 221}}
| 2012
| 2.8
| AD221XOJGXBOX
| AD221XOJZ22GX
|-
! {{rh}} rowspan="2" | {{nowrap|Athlon II X4 631}}
| 2012
| rowspan=6 | 4 (4)
| rowspan=2 | 2.6
| rowspan=6 | 4×1&nbsp;MB
| rowspan=6 | 1866
| AD631XOJGXBOX
| AD631XOJZ43GX
|-
| {{nowrap|Aug 15, 2011}}
| 100
| AD631XOJGXBOX
| AD631XWNZ43GX
|-
! {{rh}} | {{nowrap|Athlon II X4 638}}
| {{nowrap|Feb 8, 2012}}
| 2.7 
| 65
| AD638XOJGXBOX
| AD638XOJZ43GX
|-
! {{rh}} | {{nowrap|Athlon II X4 641}}
| {{nowrap|Feb 8, 2012}}
| 2.8
| rowspan=3 | 100
| AD641XWNGXBOX
| AD641XWNZ43GX
|-
! {{rh}} | {{nowrap|Athlon II X4 651}}
| {{nowrap|Nov 14, 2011}}
| rowspan=2 | 3.0
| AD651XWNGXBOX
| AD651XWNZ43GX
|-
! {{rh}} | {{nowrap|Athlon II X4 651K}}
| 2012
| AD651KWNGXBOX
| AD651KWNZ43GX
|-
! {{rh}} | {{visible anchor|E2-3200|text=[https://web.archive.org/web/20140907124402/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=13 E2-3200]}}
| 2011
| rowspan=4 | 2 (2)
| 2.4
| rowspan=4 | 2×512&nbsp;KB
| HD&nbsp;6370D
| rowspan=4 | 160:8:4
| rowspan=2 | 443
| rowspan=2 | 141.7
| rowspan=4 | 1600
| rowspan=7 | 65
| ED3200OJGXBOX
| ED3200OJZ22GX<br />ED3200OJZ22HX
|-
! {{rh}} | {{visible anchor|A4-3300|text=[https://web.archive.org/web/20140907122452/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=20 A4-3300]}}
| {{nowrap|Sep 7, 2011}}
| 2.5
| rowspan=3 | HD&nbsp;6410D
| AD3300OJGXBOX<br />AD3300OJHXBOX
| AD3300OJZ22GX<br />AD3300OJZ22HX
|-
! {{rh}} | {{visible anchor|A4-3400|text=[https://web.archive.org/web/20140907122409/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=14 A4-3400]}}
| {{nowrap|Sep 7, 2011}}
| 2.7
| rowspan=2 | 600
| rowspan=2 | 192
| AD3400OJGXBOX<br />AD3400OJHXBOX
| AD3400OJZ22GX<br />AD3400OJZ22HX
|-
! {{rh}} | A4-3420
| {{nowrap|Dec 20, 2011}}
| 2.8
| {{N/a}}
| AD3420OJZ22HX
|-
! {{rh}} | {{visible anchor|A6-3500|text=[https://web.archive.org/web/20140907124555/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=19 A6-3500]}}
| {{nowrap|Aug 17, 2011}}
| 3 (3)
| rowspan=2 | 2.1
| rowspan=2 | 2.4
| 3×1&nbsp;MB
| rowspan=5 | HD&nbsp;6530D
| rowspan=5 | 320:16:8
| rowspan=5 | 443
| rowspan=5 | 283.5
| rowspan=9 | 1866
| AD3500OJGXBOX
| AD3500OJZ33GX
|-
! {{rh}} | {{visible anchor|A6-3600|text=[https://web.archive.org/web/20140907142851/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=15 A6-3600]}}
| {{nowrap|Aug 17, 2011}}
| rowspan=8 | 4 (4)
| rowspan=8 | 4×1&nbsp;MB
| AD3600OJGXBOX
| AD3600OJZ43GX
|-
! {{rh}} | {{visible anchor|A6-3620|text=[https://web.archive.org/web/20140907125445/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=33 A6-3620]}}
| {{nowrap|Dec 20, 2011}}
| 2.2
| 2.5
| AD3620OJGXBOX
| AD3620OJZ43GX
|-
! {{rh}} | {{visible anchor|A6-3650|text=[https://web.archive.org/web/20140907124308/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=16 A6-3650]}}
| {{nowrap|Jun 30, 2011}}
| 2.6
| rowspan=2 {{N/a}}
| rowspan=2 | 100
| AD3650WNGXBOX
| AD3650WNZ43GX
|-
! {{rh}} | {{visible anchor|A6-3670K|text=[https://web.archive.org/web/20121230193335/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=31 {{nowrap|A6-3670K}}]}}
| {{nowrap|Dec 20, 2011}}
| 2.7
| AD3670WNGXBOX
| AD3670WNZ43GX
|-
! {{rh}} | {{visible anchor|A8-3800|text=[https://web.archive.org/web/20140907124946/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=17 A8-3800]}}
| {{nowrap|Aug 17, 2011}}
| 2.4
| 2.7
| rowspan=4 | HD&nbsp;6550D
| rowspan=4 | 400:20:8
| rowspan=4 | 600
| rowspan=4 | 480
| rowspan=2 | 65
| AD3800OJGXBOX
| AD3800OJZ43GX
|-
! {{rh}} | {{visible anchor|A8-3820|text=[https://web.archive.org/web/20140907122837/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=32 A8-3820]}}
| {{nowrap|Dec 20, 2011}}
| 2.5
| 2.8
| AD3820OJGXBOX
| AD3820OJZ43GX
|-
! {{rh}} | {{visible anchor|A8-3850|text=[https://web.archive.org/web/20140907124843/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=18 A8-3850]}}
| {{nowrap|Jun 30, 2011}}
| 2.9
| rowspan=2 {{N/a}}
| rowspan=2 | 100
| AD3850WNGXBOX
| AD3850WNZ43GX
|-
! {{rh}} | {{visible anchor|A8-3870K|text=[https://web.archive.org/web/20121230194834/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=30 {{nowrap|A8-3870K}}]}}
| {{nowrap|Dec 20, 2011}}
| 3.0
| AD3870WNGXBOX
| AD3870WNZ43GX
|}
{{Notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}
{{NoteFoot}}

==== Virgo: "Trinity" (2012) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 32&nbsp;nm on GlobalFoundries SOI process
* Socket [[Engineering:Socket FM2|FM2]]
* CPU: [[Engineering:Piledriver (microarchitecture)|Piledriver]]
** L1 Cache: 16 KB Data per core and 64 KB Instructions per module
* GPU TeraScale 3 (VLIW4)
* Die Size: {{val|246|u=mm2}}, 1.303 Billion transistors<ref>{{cite web |url=http://www.pcper.com/news/Processors/Trinity-Improvements-Include-Updated-Piledriver-Cores-and-VLIW4-GPUs-0 |title=Trinity Improvements Include Updated Piledriver Cores and VLIW4 GPUs |date=May 4, 2012 |access-date=November 10, 2013}}</ref>
* Support for up to four DIMMs of up to DDR3-1866 memory
* 5 GT/s UMI
* GPU (based on VLIW4 architecture) instruction support: ''[[Software:DirectX|DirectX]] 11, Opengl 4.2, DirectCompute, Pixel Shader 5.0, Blu-ray 3D, [[OpenCL]] 1.2, AMD Stream, UVD3''
* Integrated PCIe 2.0 controller, and Turbo Core technology for faster CPU/GPU operation when the thermal specification permits
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]],<ref name="auto">{{cite web |url=https://www.extremetech.com/computing/129363-amd-detonates-trinity-behold-bulldozers-second-coming |title=AMD detonates Trinity: Behold Bulldozer's second coming - ExtremeTech |access-date=October 7, 2017}}</ref> [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]]
* Sempron and Athlon models exclude integrated graphics
* Select models support Hybrid Graphics technology to assist a Radeon HD 7350, 7450, 7470, 7550, 7570, 7670 discrete graphics card.<ref>{{cite web |url=http://www.tomshardware.co.uk/a10-5800k-a8-5600k-a6-5400k,review-32463.html |title=AMD Trinity On The Desktop: A10, A8, And A6 Get Benchmarked!—Trinity: Coming Soon To A Desktop Near You |access-date=November 10, 2013}}</ref><ref>{{cite web|url=http://www.xbitlabs.com/articles/graphics/display/amd-trinity-graphics.html |title=AMD Trinity for Desktops. Part 1: Graphics Core |publisher=X-bit labs |date=September 27, 2012 |url-status=dead |archive-url=https://web.archive.org/web/20121011155319/http://www.xbitlabs.com/articles/graphics/display/amd-trinity-graphics.html |archive-date=October 11, 2012 }}</ref> However, it has been found that this does not always improve 3D accelerated graphics performance.<ref>{{cite web |url=http://hexus.net/tech/reviews/cpu/46157-amd-a10-5800k-dual-graphics-evaluation/ |title=Review: AMD A10-5800K Dual Graphics evaluation—CPU |date=October 4, 2012 |access-date=November 10, 2013}}</ref><ref>{{cite web |url=http://www.anandtech.com/show/4476/amd-a83850-review/6 |title=The AMD A8-3850 Review: Llano on the Desktop |access-date=November 10, 2013}}</ref>
{| class="wikitable" style="text-align:center;"
|-
! rowspan="3" | Model
! rowspan="3" | Released
! rowspan="3" | Fab
! rowspan="3" | Step.
! colspan="5" | CPU
! colspan="4" | GPU
! rowspan="3" | DDR3<br />memory<br />support
! rowspan="3" | TDP<br />(W)
! rowspan="3" | Box number
! rowspan="3" | Part number<ref>{{cite web |url=http://www.shopblt.com/cgi-bin/s.cgi?s_max=100&order_id=239797834&s_mfg=AMD |title=Product Search Results—Bottom Line Telecommunications |publisher=Bottom Line Telecommunications Corporation |access-date=November 10, 2013}}</ref>
|-
! rowspan="2" | [Modules/[[Floating-point unit|FPUs]]]<br />[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! colspan="2" | [[Clock rate]] ([[Hertz|GHz]])
! colspan="2" | [[Cache (computing)|Cache]]{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan="2" | Model
! rowspan="2" | Config
! rowspan="2" | Clock<br />(MHz)
! rowspan="2" | Processing<br />power<br />([[FLOPS|GFLOPS]]){{efn|name="SFLOPS"}}
|-
! Base
! Boost
! L1
! L2
|-
! {{rh}} | Sempron&nbsp;X2&nbsp;240<ref name="amdsemproncpulist">{{cite web |url=https://www.amd.com/en-us/products/processors/desktop/sempron-cpu |title=AMD Sempron CPU |access-date=March 2, 2015}}</ref>
|
| rowspan=17 | 32&nbsp;nm
| rowspan=17 | TN-A1
| rowspan=2 | [1]2
| 2.9
| 3.3
| rowspan=17 | 64&nbsp;KB inst.<br />per module<br /><br />16&nbsp;KB data<br />per core
| rowspan=2 | 1&nbsp;MB
| rowspan=5 colspan=4 {{N/a}}
| rowspan=2 | 1600
| rowspan=4 | 65
|
| SD240XOKA23HJ
|-
! {{rh}} | Athlon&nbsp;X2&nbsp;340<ref name=AX2_340>{{cite web |url=http://ru.gecid.com/cpu/amd_athlon_x2_340/?s=all |title=Обзор и тестирование процессора AMD Athlon X2 340 |access-date=September 12, 2016 |author=Альберт Шаповалов |website=Ru.gecid.com/ |date=September 10, 2014 |language=ru}}</ref>
| Oct 2012
| 3.2
| 3.6
| 
| AD340XOKA23HJ
|-
! {{rh}} | Athlon&nbsp;X4&nbsp;730
| Oct 1, 2012
| rowspan=5 | [2]4
| 2.8
| 3.2
| rowspan=5 |2×2&nbsp;MB
| rowspan=5 |1866
| 
|AD730XOKA44HJ
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/740/80 Athlon&nbsp;X4&nbsp;740]
| rowspan=2 | Oct 2012
| 3.2
| 3.7 
| AD740XOKHJBOX
| AD740XOKA44HJ
|-
! {{rh}} | {{visible anchor|Athlon&nbsp;X4 750K|text=[http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/750K/81 Athlon&nbsp;X4&nbsp;750K]}}
| 3.4
| 4.0
| 100 
| AD750KWOHJBOX
| AD750KWOA44HJ
|-
! {{rh}} | {{visible anchor|FirePro A300|text=[https://web.archive.org/web/20130728035554/http://products.amd.com/en-us/WorkstationAPUDetail.aspx?id=54&f1=&f2=&f3=&f4=4&f5=&f6=& FirePro&nbsp;A300]}}
| rowspan=2 |Aug 7, 2012
| 3.4
| 4.0
| rowspan=2 | FirePro
| rowspan=2 | 384:24:8<br />6 CU
| 760
| 583.6
| 65
|
| AWA300OKA44HJ
|-
! {{rh}} | {{visible anchor|FirePro A320|text=[https://web.archive.org/web/20130728035549/http://products.amd.com/pages/workstationapudetail.aspx?id=53&f1=&f2=&f3=&f4=4&f5=&f6=&&AspxAutoDetectCookieSupport=1 FirePro&nbsp;A320]}}
| 3.8
| 4.2
| 800
| 614.4
| 100 
|
| AWA320WOA44HJ
|-
! {{rh}} | {{visible anchor|A4-5300|text=[https://web.archive.org/web/20150619200306/http://products.amd.com/en-us/DesktopAPUDetail.aspx?detailId=49 A4-5300]}}
| Oct 1, 2012
| rowspan=4 | [1]2
| rowspan=2 | 3.4
| rowspan=2 | 3.6
| rowspan=4 | 1&nbsp;MB
| rowspan=2 | HD&nbsp;7480D
| rowspan=2 | 128:8:4<br />2 CU
| rowspan=2 | 723
| rowspan=2 | 185
| rowspan=2 | 1600
| rowspan=6 | 65 
| AD5300OKHJBOX
| AD5300OKA23HJ
|-
! {{rh}} | {{visible anchor|A4-5300B|text=[https://web.archive.org/web/20150619201302/http://products.amd.com/en-us/DesktopAPUDetail.aspx?detailId=60 A4-5300B]}}
| Oct 2012
|
| AD530BOKA23HJ
|-
! {{rh}} | {{visible anchor|A6-5400K|text=[https://web.archive.org/web/20150619215923/http://products.amd.com/en-us/DesktopAPUDetail.aspx?detailId=48 A6-5400K]}}
| Oct 1, 2012
| rowspan=2 | 3.6
| rowspan=2 | 3.8
| rowspan=2 | HD&nbsp;7540D
| rowspan=2 | 192:12:4<br />3 CU
| rowspan=2 | 760
| rowspan=2 | 291.8
| rowspan=8 | 1866 
| AD540KOKHJBOX
| AD540KOKA23HJ
|-
! {{rh}} | {{visible anchor|A6-5400B|text=[https://web.archive.org/web/20150619201551/http://products.amd.com/en-us/DesktopAPUDetail.aspx?detailId=59 A6-5400B]}}
| Oct 2012
|
| AD540BOKA23HJ
|-
! {{rh}} | {{visible anchor|A8-5500|text=[https://web.archive.org/web/20150619200311/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=47 A8-5500]}}
| Oct 1, 2012
| rowspan=6 | [2]4
| rowspan=2 | 3.2
| rowspan=2 | 3.7
| rowspan=6 | 2×2&nbsp;MB
| rowspan=3 | HD&nbsp;7560D
| rowspan=3 | 256:16:8<br />4 CU
| rowspan=3 | 760
| rowspan=3 | 389.1
| AD5500OKHJBOX
| AD5500OKA44HJ
|-
! {{rh}} | {{visible anchor|A8-5500B|text=[https://web.archive.org/web/20150619201548/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=58 A8-5500B]}}
| Oct 2012
|
| AD550BOKA44HJ
|-
! {{rh}} | {{visible anchor|A8-5600K|text=[https://web.archive.org/web/20150619215737/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=46 A8-5600K]}}
| rowspan=3 | Oct 1, 2012
| 3.6
| 3.9
| 100 
| AD560KWOHJBOX
| AD560KWOA44HJ
|-
! {{rh}} | {{visible anchor|A10-5700|text=[https://web.archive.org/web/20150619202309/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=45 A10-5700]}}
| 3.4
| 4.0
| rowspan=3 | HD&nbsp;7660D
| rowspan=3 | 384:24:8<br />6 CU
| 760
| 583.6
| 65 
| AD5700OKHJBOX
| AD5700OKA44HJ
|-
! {{rh}} | {{visible anchor|A10-5800K|text=[https://web.archive.org/web/20150619202621/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=44 A10-5800K]}}
| rowspan=2 | 3.8
| rowspan=2 | 4.2
| rowspan=2 | 800
| rowspan=2 | 614.4
| rowspan=2 | 100 
| AD580KWOHJBOX
| AD580KWOA44HJ
|-
! {{rh}} | {{visible anchor|A10-5800B|text=[https://web.archive.org/web/20150619201449/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=57 A10-5800B]}}
| Oct 2012
|
| AD580BWOA44HJ
|}
{{Notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== "Richland" (2013) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 32&nbsp;nm on GlobalFoundries SOI process
* Socket [[Engineering:Socket FM2|FM2]]
* Two or four CPU cores based on the [[Engineering:Piledriver (microarchitecture)|Piledriver]] microarchitecture
** Die Size: {{val|246|u=mm2}}, 1.303 Billion transistors<ref>{{cite web |author1=Hassan Mujtaba |title=AMD A10-6800K and A10-6700 "Richland" APU Review |url=https://wccftech.com/review/amd-a10-6800k-a10-6700-richland-apu-review/ |website=Wccftech |access-date=March 20, 2020}}</ref>
** L1 Cache: 16 KB Data per core and 64 KB Instructions per module
** MMX, SSE, [[SSE2]], [[SSE3]], SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, [[AES instruction set|AES]], [[Advanced Vector Extensions|AVX]], AVX1.1, [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], Turbo Core 3.0, [[NX bit]], [[Engineering:PowerNow!|PowerNow!]]
* GPU
** TeraScale 3 architecture
** HD Media Accelerator, [[AMD Hybrid Graphics]]

{| class="wikitable" style="text-align:center;"
|-
! rowspan="3" | Model
! rowspan="3" | Released
! rowspan="3" | Fab
! rowspan="3" | Step. 
! colspan="5" | CPU 
! colspan="4" | GPU 
! rowspan="3" | DDR3<br />memory<br />support
! rowspan="3" | TDP<br />(W)
! rowspan="3" | Box number
! rowspan="3" | Part number
|-
! rowspan="2" | [Modules/[[Floating-point unit|FPUs]]]<br />[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! colspan="2" | [[Clock rate]] ([[Hertz|GHz]])
! colspan="2" | [[Cache (computing)|Cache]]{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan="2" | Model
! rowspan="2" | Config
! rowspan="2" | Clock<br />(MHz)
! rowspan="2" | Processing<br />power<br />([[FLOPS|GFLOPS]]){{efn|name="SFLOPS"}}
|-
! Base
! Boost
! L1
! L2
|-
! {{rh}} class="table-rh" | Sempron&nbsp;X2&nbsp;250<ref name="amdsemproncpulist" />
|
| rowspan="28" | 32&nbsp;nm
| rowspan="28" | RL-A1
| rowspan="3" | [1]2
| 3.2
| 3.6
| rowspan="28" | 64&nbsp;KB inst.<br />per module<br /><br />16&nbsp;KB data<br />per core
| rowspan="3" | 1&nbsp;MB
| rowspan=6 colspan=4 {{N/a}}
|
| rowspan=4 | 65
|
| SD250XOKA23HL
|-
! {{rh}} class="table-rh" | Athlon&nbsp;X2&nbsp;350<ref name="amdcpulist">{{cite web |url=https://www.amd.com/en-us/products/processors/desktop/athlon-cpu |title=AMD Athlon Processors |access-date=March 2, 2015}}</ref>
|
| 3.5
| 3.9
| rowspan=5 | 1866
| 
| AD350XOKA23HL
|-
! {{rh}} class="table-rh" | Athlon&nbsp;X2&nbsp;370K
| Jun 2013
| 4.0
| 4.2 
| AD370KOKHLBOX
| AD370KOKA23HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/750/143 Athlon&nbsp;X4&nbsp;750]
| Oct 2013
| rowspan=3 | [2]4
| 3.4
| 4.0
| rowspan=3 | 2×2&nbsp;MB
|
| AD750XOKA44HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/760K/83 Athlon&nbsp;X4&nbsp;760K]
| Jun 2013
| 3.8
| 4.1
| 100 
| AD760KWOHLBOX
| AD760KWOA44HL
|-
! {{rh}} class="table-rh" | FX-670K<ref>{{cite web |title=AMD FX-670K CPU Shows Up in the Wild |url=http://www.techpowerup.com/199179/amd-fx-670k-cpu-shows-up-in-the-wild.html |author=btarunr |website=TechPowerUp |date=March 23, 2014}}</ref>
| Mar 2014 (OEM)
| 3.7
| 4.3
| rowspan=13 | 65
|
| FD670KOKA44HL
|-
! {{rh}} class="table-rh" | [https://web.archive.org/web/20130619180848/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=84 A4-4000]
| May 2013
| rowspan=12 | [1]2
| 3.0
| 3.2
| rowspan=12 | 1&nbsp;MB
| rowspan=2 | HD&nbsp;7480D
| rowspan=6 | 128:8:4<br />2 CU
| rowspan=2 | 720
| rowspan=2 | 184.3
| rowspan=2 | 1333
| AD4000OKHLBOX
| AD4000OKA23HL
|-
! {{rh}} class="table-rh" | [https://web.archive.org/web/20150619203039/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=104 A4-4020]
| Jan 2014
| 3.2
| 3.4 
| AD4020OKHLBOX
| AD4020OKA23HL
|-
! {{rh}} class="table-rh" | A4-6300
| rowspan=2 | Jul 2013
| rowspan=2 | 3.7
| rowspan=2 | 3.9
| rowspan=4 | HD&nbsp;8370D
| rowspan=4 | 760 
| rowspan=4 | 194.5
| rowspan=6 | 1600 
| AD6300OKHLBOX
| AD6300OKA23HL
|-
! {{rh}} class="table-rh" | [https://web.archive.org/web/20150619215735/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=95 A4-6300B]
|
| AD630BOKA23HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Desktops/A4-6320-with-Radeon%E2%84%A2-HD-8370D/28 A4-6320]
| Dec 2013
| rowspan=4 | 3.8
| rowspan=4 | 4.0 
| AD6320OKHLBOX
| AD6320OKA23HL
|-
! {{rh}} class="table-rh" | [https://web.archive.org/web/20141129185732/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=138 A4-6320B]
| Mar 2014
|
| AD632BOKA23HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Desktops/A4-7300-with-Radeon%E2%84%A2-HD-8470D/30 A4-7300]
| rowspan=2 | Aug 2014
| rowspan=6 | HD&nbsp;8470D
| rowspan=6 | 192:12:4<br />3 CU
| rowspan=6 | 800
| rowspan=6 | 307.2 
|
| AD7300OKA23HL
|-
| {{rh}} class="table-rh" | [https://web.archive.org/web/20141129185558/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=136 A4&nbsp;Pro-7300B]
|
| AD730BOKA23HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-Business-Class---Dual-Core-A6-Series-APU-for-Desktops/A6-6400B-with-Radeon%E2%84%A2-HD-8470D/72 A6-6400B]
| rowspan=2 | Jun 4, 2013
| rowspan=2 | 3.9
| rowspan=2 | 4.1
| rowspan=12 | 1866 
|
| AD640BOKA23HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Desktops/A6-6400K-with-Radeon%E2%84%A2-HD-8470D/44 A6-6400K]
| AD640KOKHLBOX
| AD640KOKA23HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-Business-Class---Dual-Core-A6-Series-APU-for-Desktops/A6-6420B-with-Radeon%E2%84%A2-HD-8470D/73 A6-6420B]
| rowspan=2 | Jan 2014
| rowspan=2 | 4.0
| rowspan=2 | 4.2 
|
| AD642BOKA23HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Desktops/A6-6420K-with-Radeon%E2%84%A2-HD-8470D/45 A6-6420K]
| AD642KOKHLBOX
| AD642KOKA23HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Desktops/A8-6500T-with-Radeon%E2%84%A2-HD-8550D/60 A8-6500T]
| Sep 18, 2013
| rowspan=10 | [2]4
| 2.1
| 3.1
| rowspan=10 | 2×2&nbsp;MB
| HD&nbsp;8550D
| rowspan=4 | 256:16:8<br />4 CU
| 720
| 368.6
| 45 
| AD650TYHHLBOX
| AD650TYHA44HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Desktops/A8-6500-with-Radeon%E2%84%A2-HD-8570D/59 A8-6500]
| rowspan=3 | Jun 4, 2013
| rowspan=2 | 3.5
| rowspan=2 | 4.1
| rowspan=3 | HD&nbsp;8570D
| rowspan=2 | 800
| rowspan=2 | 409.6
| rowspan=2 | 65 
| AD6500OKHLBOX
| AD6500OKA44HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-Business-Class---Quad-Core-A8-Series-APU-for-Desktops/A8-6500B-with-Radeon%E2%84%A2-HD-8570D/75 A8-6500B]
|
| AD650BOKA44HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Desktops/A8-6600K-with-Radeon%E2%84%A2-HD-8570D/61 A8-6600K]
| 3.9
| 4.2
| 844
| 432.1
| 100 
| AD660KWOHLBOX
| AD660KWOA44HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-6700T-with-Radeon%E2%84%A2-HD-8650D/5 A10-6700T]
| Sep 18, 2013
| 2.5
| 3.5 
| HD&nbsp;8650D
| rowspan=6 | 384:24:8<br />6 CU
| 720
| 552.9
| 45 
| AD670TYHHLBOX
| AD670TYHA44HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-6700-with-Radeon%E2%84%A2-HD-8670D/4 A10-6700]
| Jun 4, 2013
| 3.7
| rowspan=3 | 4.3
| rowspan=5 | HD&nbsp;8670D
| rowspan=5 | 844
| rowspan=5 | 648.1
| 65 
| AD6700OKHLBOX
| AD6700OKA44HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A-Series-A10-APU-for-Desktops/A10-6790B-with-Radeon%E2%84%A2-HD-8670D/110 A10-6790B]
| Oct 29, 2013
| rowspan=2 | 4.0 
| rowspan=4 | 100
| AD679KWOHLBOX
| AD679KWOA44HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-6790K-with-Radeon%E2%84%A2-HD-8670D/6 A10-6790K]
| Oct 28, 2013
|
| AD679BWOA44HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-6800K-with-Radeon%E2%84%A2-HD-8670D/7 A10-6800K]
| rowspan=2 | Jun 4, 2013
| rowspan=2 | 4.1
| rowspan=2 | 4.4
| rowspan=2 | 2133 
| AD680KWOHLBOX
| AD680KWOA44HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A-Series-A10-APU-for-Desktops/A10-6800B-with-Radeon%E2%84%A2-HD-8670D/109 A10-6800B]
|
|AD680BWOA44HL
|}
{{Notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== "Kabini" (2013, [[System on a chip|SoC]]) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* [[Engineering:Socket AM1|Socket AM1]], aka Socket FS1b (AM1 platform)
* 2 to 4 CPU Cores ([[Engineering:Jaguar (microarchitecture)|Jaguar (microarchitecture)]])
* L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, SSE4.1, SSE4.2, AMD64, [[Advanced Vector Extensions|AVX]], [[F16C]], [[CLMUL instruction set|CLMUL]], [[AES instruction set|AES]], MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], AMD-V support
* SoC with integrated memory, PCIe, 2× USB 3.0, 6× USB 2.0, Gigabit Ethernet, and 2× SATA III (6 [[Gigabit|Gb]]/s) controllers
* GPU based on [[Graphics Core Next]] (GCN)
{| class="wikitable" style="text-align:center;"
|-
! rowspan="3" | Model 
! rowspan="3" | Released
! rowspan="3" | Fab
! rowspan="3" | Step.
! colspan="5" | CPU
! colspan="4" | GPU
! rowspan="3" | DDR3<br />memory<br />support
! rowspan="3" | TDP<br />(W)
! rowspan="3" | Box number
! rowspan="3" | Part number
|-
! rowspan="2" | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]
! colspan="2" | [[Clock rate]] ([[Hertz|GHz]])
! colspan="2" | [[Cache (computing)|Cache]]{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan="2" | Model
! rowspan="2" | Config
! rowspan="2" | Clock<br />(MHz)
! rowspan="2" | Processing<br />power<br />([[FLOPS|GFLOPS]]){{efn|name="SFLOPS"}}
|-
! Base
! Boost
! L1
! L2
|-
! {{rh}} | {{visible anchor|Athlon X4 530|text=[https://www.cpu-world.com/CPUs/Jaguar/AMD-Athlon%20X4%20530%20-%20AD530XJAH44HM.html Athlon&nbsp;X4&nbsp;530]}}
| rowspan="2" | 
| rowspan="7" | 28&nbsp;nm
| rowspan="7" | KB-A1
| rowspan="2" | 4 (4) 
| 2.00
| rowspan="7" {{N/a}}
| rowspan="7" | 32&nbsp;KB inst.<br />32&nbsp;KB data<br /><br />per core
| rowspan="2" | 2&nbsp;MB
| rowspan="2" colspan="4" {{N/a}}
| rowspan="2" | 1600<br /><small>single-channel</small>
| rowspan="7" | 25
| 
| AD530XJAH44HM
|-
! {{rh}} | {{visible anchor|Athlon X4 550|text=[https://www.cpu-world.com/CPUs/Jaguar/AMD-Athlon%20X4%20550%20-%20AD550XJAH44HM.html Athlon&nbsp;X4&nbsp;550]}}
| 2.20
| 
| AD550XJAH44HM 
|-
! {{rh}} | {{visible anchor|Sempron 2650|text=[http://products.amd.com/en-us/search/APU/AMD-Sempron%E2%84%A2-APUs/AMD-Sempron%E2%84%A2-Dual-Core-APU/Sempron%E2%84%A2-2650-APU-with-Radeon%E2%84%A2-R3-Series/119 Sempron&nbsp;2650]}}
| rowspan="4" | Apr 9, 2014
| 2 (2) 
| 1.45
| 1&nbsp;MB
| R3 (HD&nbsp;8240)
| rowspan="5" | 128:8:4<br />2 CU
| 400
| 102.4
| 1333<br /><small>single-channel</small>
| SD2650JAHMBOX
| SD2650JAH23HM
|-
! {{rh}} | {{visible anchor|Sempron 3850|text=[http://products.amd.com/en-us/search/APU/AMD-Sempron%E2%84%A2-APUs/AMD-Sempron%E2%84%A2-Quad-Core-APU/Sempron%E2%84%A2-3850-APU-with-Radeon%E2%84%A2-R3-Series/120 Sempron&nbsp;3850]}}
| rowspan="4" | 4 (4)
| 1.30
| rowspan="4" | 2&nbsp;MB
| R3 (HD&nbsp;8280)
| 450
| 115.2
| rowspan="4" | 1600<br /><small>single-channel</small>
| SD3850JAHMBOX
| SD3850JAH44HM
|-
! {{rh}} | {{visible anchor|Athlon 5150|text=[http://products.amd.com/en-us/search/APU/AMD-Athlon%E2%84%A2-APUs/AMD-Athlon%E2%84%A2-Quad-Core-APU/Athlon%E2%84%A2-5150-APU-with-Radeon%E2%84%A2-R3-Series/76 Athlon&nbsp;5150]}}
| 1.60
| rowspan="3" | R3 (HD&nbsp;8400)
| rowspan="3" | 600
| rowspan="3" | 153.6 
| AD5150JAHMBOX
| AD5150JAH44HM
|-
! {{rh}} | {{visible anchor|Athlon 5350|text=[http://products.amd.com/en-us/search/APU/AMD-Athlon%E2%84%A2-APUs/AMD-Athlon%E2%84%A2-Quad-Core-APU/Athlon%E2%84%A2-5350-APU-with-Radeon%E2%84%A2-R3-Series/77 Athlon&nbsp;5350]}}
| 2.05 
| AD5350JAHMBOX
| AD5350JAH44HM
|-
! {{rh}} | {{visible anchor|Athlon 5370|text=[http://products.amd.com/en-us/search/APU/AMD-Athlon%E2%84%A2-APUs/AMD-Athlon%E2%84%A2-Quad-Core-APU/Athlon%E2%84%A2-5370-APU-with-Radeon%E2%84%A2-R3-Series/182 Athlon&nbsp;5370]}}
| Feb 2016
| 2.20 
|
| AD5370JAH44HM
|}
{{Notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== "Kaveri" (2014) & "Godavari" (2015) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]].
* [[Engineering:Socket FM2+|Socket FM2+]],<ref>{{cite web |url= http://www.xbitlabs.com/news/cpu/display/20130530232155_AMD_s_Next_Gen_Kaveri_APUs_Will_Require_New_Mainboards.html |title= AMD's Next-Gen "Kaveri" APUs Will Require New Mainboards |author= Anton Shilov |access-date= December 17, 2014 |date= May 30, 2013 |archive-date= June 7, 2013 |archive-url= https://web.archive.org/web/20130607163138/http://www.xbitlabs.com/news/cpu/display/20130530232155_AMD_s_Next_Gen_Kaveri_APUs_Will_Require_New_Mainboards.html |url-status= dead }}</ref> support for PCIe 3.0.
* Two or four CPU cores based on the [[Engineering:Steamroller (microarchitecture)|Steamroller]] microarchitecture.
**Kaveri refresh models have codename Godavari.<ref>{{cite web|url=http://www.cpu-world.com/Cores/Godavari.html|title=AMD Godavari core|website=www.cpu-world.com|access-date=September 16, 2018}}</ref>
* Die Size: {{val|245|u=mm2}}, 2.41&nbsp;Billion transistors.<ref>{{cite web |author1=Joel Hruska |title=AMD Kaveri A10-7850K and A8-7600 review: Was it worth the wait for the first true heterogeneous chip? |url=https://www.extremetech.com/computing/174632-amd-kaveri-a10-7850k-and-a8-7600-review-was-it-worth-the-wait-for-the-first-true-heterogeneous-chip |website=ExtremeTech |access-date=March 20, 2020}}</ref>
* L1 Cache: 16 KB Data per core and 96 KB Instructions per module.
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], Turbo Core
* Three to eight Compute Units (CUs) based on GCN 2nd gen microarchitecture;<ref name="wccftech">{{cite web |url=http://wccftech.com/amd-kaveri-apu-architecture-detailed-generation-apu-featuring-steamroller-gcn-cores/ |title=AMD Kaveri APU Architecture Detailed |author=Hassan Mujtaba |date=July 4, 2013 |access-date=March 15, 2015}}</ref> 1 Compute Unit (CU) consists of 64 [[Unified shader model|Unified Shader Processors]] : 4 [[Texture mapping unit|Texture Mapping Units]] (TMUs) : 1 [[Render output unit|Render Output Unit]] (ROPs).
* [[Engineering:Heterogeneous System Architecture|Heterogeneous System Architecture]]-enabled [[Zero-copy|zero-copy]] through [[Pointer (computer programming)|pointer]] passing.
* [[Engineering:Semiconductor intellectual property core|SIP blocks]]: Unified Video Decoder, Video Coding Engine, TrueAudio.<ref name="SemiAccurate">{{cite web |url=http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/ |title=A technical look at AMD's Kaveri architecture |date=January 15, 2014 |work=SemiAccurate}}</ref>
* Dual-channel (2× 64 Bit) DDR3 memory controller.
* Integrated custom ARM Cortex-A5 co-processor<ref name="arstechnica.com">{{cite web | url=https://arstechnica.com/information-technology/2012/06/amd-to-add-arm-processors-to-boost-chip-security/ | title=AMD to add ARM processors to boost chip security | access-date=September 3, 2013 | date=June 14, 2012}}</ref> with TrustZone Security Extensions<ref name="technewspedia.com">{{cite web |url=http://technewspedia.com/amd-and-arm-fusion-redefine-beyond-x86/ |title=AMD and ARM Fusion redefine beyond x86 |access-date=November 10, 2013 |archive-url=https://web.archive.org/web/20131105095352/http://technewspedia.com/amd-and-arm-fusion-redefine-beyond-x86/ |archive-date=November 5, 2013 |url-status=dead }}</ref> in select APU models, except the Performance APU models.<ref name="ps-philgeps.gov.ph carrizo">{{cite web |url=http://www.ps-philgeps.gov.ph/home/images/BAD/PHILIPPINES_PS-DBM%20Event%20July%2015,%202016.pdf|title=Carrizo presentation, page 12 - Carrizo is the 1st ARM Trustzone capable performance APU|access-date=January 13, 2020}}</ref>
* Select models support Hybrid Graphics technology by using a Radeon R7 240 or R7 250 discrete graphics card.<ref>{{cite web |url=http://www.techspot.com/review/781-amd-a10-7850k-graphics-performance/ |title=AMD A10-7850K Graphics Performance |date=February 14, 2014 |access-date=April 2, 2014}}</ref>
* Display controller: AMD Eyefinity 2, 4K Ultra HD support, DisplayPort 1.2 Support.<ref>{{cite web |url=http://www.guru3d.com/articles_pages/amd_a8_7600_apu_review,3.html |title=AMD A8-7600 Kaveri APU review - The Embedded GPU - HSA & hUMA |date=January 14, 2014}}</ref>
{| class="wikitable" style="text-align:center;"
! rowspan="3" | Model 
! rowspan="3" | Released
! rowspan="3" | Fab
! rowspan="3" | Step.
! colspan="5" | CPU
! colspan="4" | GPU
! rowspan="3" | DDR3<br />memory<br />support
! rowspan="3" | TDP<br />(W)
! rowspan="3" | Box number
! rowspan="3" | Part number
|-
! rowspan="2" | [Modules/[[Floating-point unit|FPUs]]]<br />[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! colspan="2" | [[Clock rate]] ([[Hertz|GHz]])
! colspan="2" | [[Cache (computing)|Cache]]{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan="2" | Model
! rowspan="2" | Config
! rowspan="2" | Clock<br />(MHz)
! rowspan="2" | Processing<br />power<br />([[FLOPS|GFLOPS]]){{efn|name="SFLOPS"}}
|-
! Base
! Boost
! L1
! L2
|-
! {{rh}}|{{nowrap|Athlon X2 450}}<ref name="amdcpulist" />
| Jul 31, 2014
| rowspan="30" | 28&nbsp;nm
| rowspan=3 | KV-A1
| [1]2
| 3.5
| 3.9
| rowspan="30" | 96&nbsp;KB inst.<br />per module<br /><br />16&nbsp;KB data<br />per core
| 1&nbsp;MB
| rowspan=8 colspan=4 {{N/a}}
| 1866
| rowspan="4" | 65 
| 
| AD450XYBI23JA
|-
! {{rh}} class="table-rh" |[https://www.cpu-world.com/CPUs/Bulldozer/AMD-Athlon%20X4%20830%20-%20AD830XYBI44JA.html {{nowrap|Athlon X4 830}}]
| 2018
| rowspan="7" | [2]4
| 3.0
| 3.4
| rowspan="7" | 2×2&nbsp;MB
| rowspan="7" | 2133
| 
| AD830XYBI44JA
|-
! {{rh}} class="table-rh" |Athlon&nbsp;X4&nbsp;840<ref name="amdcpulist" />
| Aug 2014
| 3.1
| 3.8
| AD840XYBJABOX
| AD840XYBI44JA
|-
! {{rh}} class="table-rh" |[https://www.cpu-upgrade.com/CPUs/AMD/Athlon_X4/850.html {{nowrap|Athlon X4 850}}]
| 2015
| GV-A1
| 3.2
| 
| 
| AD835XACI43KA
|-
! {{rh}} class="table-rh" |[http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/860K-with-New-Thermal-Solution/133 {{nowrap|Athlon X4 860K}}]
| Aug 2014
| KV-A1
| 3.7
| 4.0 
| rowspan="3" | 95 
| AD860KXBJABOX<br />AD860KWOHLBOX<br />AD860KXBJASBX
| AD860KXBI44JA
|-
! {{rh}} class="table-rh" |[http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/870K-with-New-Thermal-Solution/132 {{nowrap|Athlon X4 870K}}]
| Dec 2015
| rowspan=2 | GV-A1
| 3.9
| 4.1 
| AD870KXBJCSBX
| AD870KXBI44JC
|-
! {{rh}}|[http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/880K-with-Near-Silent-Thermal-Solution/138 {{nowrap|Athlon X4 880K}}]
| Mar 1, 2016
| 4.0
| 4.2
| AD880KXBJCSBX
| 
|-
! {{rh}}|FX-770K<ref>{{cite web|title=HP offers desktop PCs with AMD FX-770K Kaveri processor|url=http://en.ofweek.com/new-products/HP-offers-desktop-PCs-with-AMD-FX-770K-Kaveri-processor-19708|author=Gennadiy Shvets|website=OFweek|date=October 18, 2014|access-date=March 23, 2016|archive-url=https://web.archive.org/web/20180513082437/http://en.ofweek.com/new-products/HP-offers-desktop-PCs-with-AMD-FX-770K-Kaveri-processor-19708|archive-date=May 13, 2018|url-status=dead}}</ref>
| Dec 2014
| rowspan=5 | KV-A1
| 3.5
| 3.9
| rowspan=10 | 65
| 
| FD770KYBI44JA
|-
! {{rh}}|[http://products.amd.com/en-ca/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A4-APU-for-Desktops/A4-PRO-7350B-with-Radeon%E2%84%A2-R5-Graphics/114 {{nowrap|A4 Pro-7350B}}]
| Jul 31, 2014
| rowspan=6 | [1]2
| 3.4
| 3.8 
| rowspan=6 | 1&nbsp;MB
| rowspan=6 | R5
| 192:12:8<br />3 CU
| 514
| 197.3
| rowspan=4 | 1866
| 
| AD735BYBI23JA
|-
! {{rh}}|[https://products.amd.com/en-ca/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A4-APU-for-Desktops/6th-Gen-AMD-PRO-A4-8350B-APU/160 {{nowrap|Pro A4-8350B}}]
| Sep 29, 2015
| 3.5
| 3.9
| rowspan=5 | 256:16:8<br />4 CU
| 757
| 387.5
| 
| AD835BYBI23JC
|-
! {{rh}} class="table-rh" |[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Desktops/A6-7400K-with-Radeon%E2%84%A2-R5-Series/46 A6-7400K]
| rowspan=2 | Jul 31, 2014
| rowspan=2 | 3.5
| rowspan=2 | 3.9
| rowspan=2 | 756
| rowspan=2 | 387 
| AD740KYBJABOX
| AD740KYBI23JA
|-
! {{rh}}|[http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A6-APU-for-Desktops/A6-PRO-7400B-with-Radeon%E2%84%A2-R5-Graphics/115 {{nowrap|A6 Pro-7400B}}]
|
| AD740BYBI23JA
|-
! {{rh}}|[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Desktops/A6-7470K-with-Radeon%E2%84%A2-R5-Series/181 A6-7470K]
| Feb 2, 2016
| rowspan=2 | GV-A1
| rowspan=2 | 3.7
| rowspan=2 | 4.0
| rowspan=2 | 800
| rowspan=2 | 409.6
| rowspan=18 | 2133
| AD747KYBJCBOX
| AD747KYBI23JC
|-
! {{rh}}|[https://products.amd.com/de-de/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A6-APU-for-Desktops/6th-Gen-AMD-PRO-A6-8550B-APU/159 {{nowrap|Pro A6-8550B}}]
| Sep 29, 2015
|
| AD855BYBI23JC
|-
! {{rh}}|A8-7500<ref>{{cite web |title=ASRock - FM2+ CPU Support List|url=https://www.asrock.com/support/cpu.asp?s=FM2%2b|website=asrock.com|access-date=October 18, 2020}}</ref><ref>{{cite web |author1=电脑维修技术网 |title=AMD APU A8-7500 CPU怎么样？|url=http://www.pc811.com/tuijian/26613.html|website=pc811.com|access-date=October 18, 2020}}</ref>
| 2014
| rowspan=4 | KV-A1
| rowspan=16 | [2]4
| 3.0
| 3.7
| rowspan=16 | 2×2&nbsp;MB
| rowspan=16 | R7
| rowspan=7 | 384:24:8<br /> 6 CU
| rowspan=4 | 720
| rowspan=4 | 552.9
| 
| AD7500YBI44JA
|-
! {{rh}}|[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Desktops/A8-7600-with-Radeon%E2%84%A2-R7-Series/62 A8-7600]
| rowspan=2 | Jul 31, 2014
| rowspan=2 | 3.1
| rowspan=3 | 3.8
| AD7600YBJABOX
| AD7600YBI44JA
|-
! {{rh}}|[http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A8-APU-for-Desktops/A8-PRO-7600B-with-Radeon%E2%84%A2-R7-Graphics/117 {{nowrap|A8 Pro-7600B}}]
|
| AD760BYBI44JA
|-
! {{rh}}|[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Desktops/A8-7650K-with-Radeon%E2%84%A2-R7-Series/63 A8-7650K]
| Jan 7, 2015
| 3.3
| rowspan=2 | 95 
| AD765KXBJABOX<br />AD765KXBJASBX
| AD765KXBI44JA
|-
! {{rh}} class="table-rh" |[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Desktops/A8-7670K-with-Radeon%E2%84%A2-R7-Series-and-New-Thermal-Solution/177 A8-7670K]
| Jul 20, 2015
| rowspan=2 | GV-A1
| 3.6
| rowspan="2" | 3.9
| rowspan=2 | 757
| rowspan=2 | 581.3 
| AD767KXBJCSBX<br />AD767KXBJCBOX
| AD767KXBI44JC
|-
! {{rh}}|[https://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A8-APU-for-Desktops/6th-Gen-AMD-PRO-A8-8650B-APU/158 {{nowrap|Pro A8-8650B}}]
| Sep 29, 2015
| 3.2
| 65
| 
| AD865BYBI44JC
|-
! {{rh}} class="table-rh" |[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-7700K-with-Radeon%E2%84%A2-R7-Series/8 A10-7700K]
| Jan 14, 2014
| rowspan=5 | KV-A1
| 3.4
| 3.8
| rowspan="5" | 720
| 552.9
| 95 
| AD770KXBJABOX
| AD770KXBI44JA
|-
! {{rh}} class="table-rh" |[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-7800-with-Radeon%E2%84%A2-R7-Series/9 A10-7800]
| rowspan=2 | Jul 31, 2014
| rowspan=2 | 3.5
| rowspan=2 | 3.9
| rowspan=9 | 512:32:8<br />8 CU
| rowspan=4 | 737.2
| rowspan=2 | 65 
| AD7800YBJABOX
| AD7800YBI44JA
|-
! {{rh}} | {{visible anchor|A10 PRO-7800B|text=[http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Desktops/A10-PRO-7800B-with-Radeon%E2%84%A2-R7-Graphics/111 {{nowrap|A10 Pro-7800B}}]}}
|
| AD780BYBI44JA
|-
! {{rh}}|[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-7850K-with-Radeon%E2%84%A2-R7-Series/10 A10-7850K]
| Jan 14, 2014
| rowspan=2 | 3.7
| rowspan=3 | 4.0
| rowspan=2 | 95 
| AD785KXBJABOX
| AD785KXBI44JA
|-
! {{rh}}|[http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Desktops/A10-PRO-7850B-with-Radeon%E2%84%A2-R7-Graphics/112 {{nowrap|A10 Pro-7850B}}]
| Jul 31, 2014
| 
| AD785BXBI44JA
|-
! {{rh}}|[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-7860K-with-Radeon%E2%84%A2-R7-Series/180 A10-7860K]
| Feb 2, 2016
| rowspan=5 | GV-A1
| 3.6
| 757
| 775.1
| 65 
| AD786KYBJABOX<br />AD786KYBJCSBX
| AD786KYBI44JC
|-
! {{rh}}|[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-7870K-with-Radeon%E2%84%A2-R7-Series/155 A10-7870K]
| May 28, 2015
| 3.9
| 4.1
| rowspan=2 | 866
| rowspan=2 | 886.7
| rowspan=2 | 95 
| AD787KXDJCBOX<br />AD787KXDJCSBX
| AD787KXDI44JC
|-
! {{rh}}|[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-7890K-with-Radeon%E2%84%A2-R7-Graphics-and-Wraith-cooler/186 A10-7890K]
| Mar 1, 2016
| 4.1
| 4.3 
| AD789KXDJCHBX
| AD789KXDI44JC
|-
! {{rh}}|[https://products.amd.com/en-ca/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Desktops/6th-Gen-AMD-PRO-A10-8750B-APU/157 {{nowrap|Pro A10-8750B}}]
| rowspan=2 | Sep 29, 2015
| 3.6
| 4.0
| 757
| 775.1 
| 65
| 
| AD875BYBI44JC
|-
! {{rh}}|[https://products.amd.com/en-gb/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Desktops/6th-Gen-AMD-PRO-A10-8850B-APU/156 {{nowrap|Pro A10-8850B}}]
| 3.9
| 4.1
| 800
| 819.2
| 95
| 
| AD885BXBI44JC
|-
! rowspan=3 | Model 
! rowspan=3 | Released
! rowspan=3 | Fab
! rowspan=3 | Step.
! rowspan=2 | [Modules/FPUs]<br />Cores/threads
! Base
! Boost
! L1
! L2
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock<br />(MHz)
! rowspan=2 | Processing<br />power<br />(GFLOPS){{efn|name="SFLOPS"}}
! rowspan=3 | DDR3<br />memory<br />support
! rowspan=3 | TDP<br />(W)
! rowspan=3 | Box number
! rowspan=3 | Part number
|-
! colspan=2 | Clock rate (GHz)
! colspan=2 | Cache{{efn|name="kib"}}
|-
! colspan=5 | CPU
! colspan=4 | GPU
|}
{{Notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== "Carrizo" (2016) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]]: 28&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* Socket [[Engineering:Socket FM2+|FM2+]] or [[Engineering:Socket AM4|AM4]], support for PCIe 3.0
* Two or four CPU cores based on the [[Engineering:Excavator (microarchitecture)|Excavator]] microarchitecture
* Die size: {{val|250.04|u=mm2}}, 3.1 billion transistors<ref>{{cite web |author1=Hassan Mujtaba |title=AMD Details Carrizo APUs Energy Efficient Design at Hot Chips 2015 – 28nm Bulk High Density Design With 3.1 Billion Transistors, 250mm2 Die |url=https://wccftech.com/amd-carrizo-apu-architecture-hot-chips/ |website=Wccftech |access-date=March 20, 2020 |date=August 26, 2015}}</ref>
* L1 cache: 32&nbsp;KB data per core and 96&nbsp;KB instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], [[RDRAND]], Turbo Core
* Single- or dual-channel DDR3 or DDR4 memory controller
* Third generation [[Graphics Core Next|GCN]]-based GPU ([[Radeon 300 series|Radeon M300]])
* Integrated custom ARM Cortex-A5 coprocessor<ref name="arstechnica.com" /> with TrustZone security extensions<ref name="technewspedia.com" /><ref name="ps-philgeps.gov.ph carrizo" />
{| class="wikitable" style="text-align:center;"
|-
! rowspan="3" | Model
! rowspan="3" | Released
! rowspan="3" | Fab
! rowspan="3" | Step.
! rowspan="3" | Socket
! colspan="5" | CPU
! colspan="4" | GPU
! rowspan="3" | Memory<br />support
! rowspan="3" | TDP<br />(W)
! rowspan="3" | Box number{{efn|name="box"|With cooler if available.}} 
! rowspan="3" | Part number
|-
! rowspan="2" | [Modules/[[Floating-point unit|FPUs]]]<br />[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! colspan="2" | [[Clock rate]] ([[Hertz|GHz]])
! colspan="2" | [[Cache (computing)|Cache]]{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan="2" | Model
! rowspan="2" | Config
! rowspan="2" | Clock<br />(MHz)
! rowspan="2" | Processing<br />power<br />([[FLOPS|GFLOPS]]){{efn|name="SFLOPS"}}
|-
! Base
! Boost
! L1
! L2
|-
! {{rh}} class="table-rh" | [https://www.cpu-upgrade.com/CPUs/AMD/Athlon_X4/835.html {{nowrap|Athlon X4 835}}]
| 
| rowspan="10" | 28&nbsp;nm
| rowspan="10" | CZ-A1
| rowspan="4" | FM2+
| rowspan="2" | [2]4
| 3.1
| 
| rowspan="10" | 96&nbsp;KB inst.<br />per module<br /><br />32&nbsp;KB data<br />per core
| rowspan="2" | 2×1&nbsp;MB
| rowspan="2" colspan="4" {{N/a}}
| rowspan="4" | DDR3-2133
| rowspan="4" | 65
| 
| AD835XACI43KA
|-
! {{rh}} class="table-rh" | [https://www.amd.com/en/products/cpu/845-near-silent-thermal-solution {{nowrap|Athlon X4 845}}]
| Feb 2, 2016
| rowspan="3" | 3.5
| rowspan="3" | 3.8
| AD845XYBJCSBX<br />AD845XACKASBX
| AD845XACI43KA
|-
! {{rh}} class="table-rh" | A6-7480<ref>{{cite web |title=AMD quietly launches new Carrizo APU: A8-7680 processor |url=https://www.reddit.com/r/hardware/comments/9rmj8t/amd_quietly_launches_new_carrizo_apu_a87680/ |access-date=June 29, 2019 |date=October 26, 2018}}</ref>
| rowspan="2" | Oct 2018
| [1]2
| 1&nbsp;MB
| R5
| rowspan="2" | 384:24:8<br />6 CU
| rowspan="2" | 900
| rowspan="2" | 691.2
| AD7480ACABBOX
| AD7480ACI23AB
|-
! {{rh}} class="table-rh" | A8-7680<ref>{{cite web |title=Day of the Dead: AMD Releases new Carrizo FM2+ APU, the A8-7680 |url=https://www.anandtech.com/show/13524/amd-new-carrizo-fm2-apu-a8-7680 |author=Cutress, Ian |access-date=June 29, 2019 |date=October 28, 2018}}</ref>
| [2]4
| 2×1&nbsp;MB
| R7
| AD7680ACABBOX
| AD7680ACI43AB
|-
! {{rh}} class="table-rh" | [https://www.amd.com/en/product/6156 {{nowrap|Pro A6-8570E}}]
| rowspan=6 | Oct 2016
| rowspan=6 | AM4
| rowspan=2 | [1]2
| 3.0
| 3.4
| rowspan=2 | 1&nbsp;MB
| rowspan=2 | R5
| 256:16:4<br />4 CU
| 800
| 409.6
| rowspan=6 | DDR4-2400
| 35
| 
| AD857BAHM23AB
|-
! {{rh}} class="table-rh" | [https://www.amd.com/en/product/6151 {{nowrap|Pro A6-8570}}]
| 3.5
| 3.8
| rowspan=3 | 384:24:6<br />6 CU
| 1029
| 790.2
| 65
| 
| AD857BAGM23AB
|-
! {{rh}} class="table-rh" | [https://www.amd.com/en/product/6241 {{nowrap|Pro A10-8770E}}]
| rowspan=4 | [2]4
| 2.8
| 3.5
| rowspan=4 | 2×1&nbsp;MB
| rowspan=4 | R7
| 847
| 650.4
| 35
| 
| AD877BAHM44AB
|-
! {{rh}} class="table-rh" | [https://www.amd.com/en/product/6236 {{nowrap|Pro A10-8770}}]
| 3.5
| rowspan="2" | 3.8
| 1029
| 790.2
| 65
| 
| AD877BAGM44AB
|-
! {{rh}} class="table-rh" | [https://www.amd.com/en/product/6146 {{nowrap|Pro A12-8870E}}]
| 2.9
| rowspan=2 | 512:32:8<br />8 CU
| 900
| 921.6
| 35
| 
| AD887BAHM44AB
|-
! {{rh}} class="table-rh" | [https://www.amd.com/en/product/6231 {{nowrap|Pro A12-8870}}]
| 3.7
| 4.2
| 1108
| 1134.5
| 65
| 
| AD887BAUM44AB
|}
{{Notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== "Bristol Ridge" (2016) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* [[Engineering:Socket AM4|Socket AM4]], support for PCIe 3.0
* Two or four "[[Engineering:Excavator (microarchitecture)|Excavator+]]" CPU cores
* L1 Cache: 32 KB Data per core and 96 KB Instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], [[RDRAND]], Turbo Core
* Dual-channel DDR4 memory controller
* [[Engineering:PCI Express|PCI Express]] 3.0 x8 (No Bifurcation support, requires a PCI-e switch for any configuration other than x8)
* [[Engineering:PCI Express|PCI Express]] 3.0 x4 as link to optional external chipset
* 4x USB 3.1 Gen 1
* Storage: 2x [[Engineering:SATA|SATA]] and 2x NVMe or 2x PCI Express
* Third Generation [[Graphics Core Next|GCN]] based GPU<ref>{{cite news|last1=Cutress|first1=Ian|title=AMD 7th Gen Bristol Ridge and AM4 Analysis|url=http://www.anandtech.com/show/10705/amd-7th-gen-bristol-ridge-and-am4-analysis-a12-9800-b350-a320-chipset|access-date=September 23, 2016|website=Anandtech.com|date=September 23, 2016}}</ref> with hybrid [[VP9]] decoding
{| class="wikitable" style="text-align:center;"
|-
! rowspan="3" | Model
! rowspan="3" | Released
! rowspan="3" | Fab
! rowspan="3" | Step.
! colspan="5" | CPU
! colspan="4" | GPU
! rowspan="3" | DDR4<br />memory<br />support
! rowspan="3" | TDP<br />(W)
! rowspan="3" | Box number{{efn|name="box"|With cooler if available.}}
! rowspan="3" | Part number
|-
! rowspan="2" | [Modules/[[Floating-point unit|FPUs]]]<br />[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! colspan="2" | [[Clock rate]] ([[Hertz|GHz]])
! colspan="2" | [[Cache (computing)|Cache]]{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan="2" | Model
! rowspan="2" | Config
! rowspan="2" | Clock<br />(MHz)
! rowspan="2" | Processing<br />power<br />([[FLOPS|GFLOPS]]){{efn|name="SFLOPS"}}
|-
! Base
! Boost
! L1
! L2
|-
! {{rh}} | {{nowrap|Athlon X4 940}}<ref>{{cite web |title=7th Gen AMD Athlon™ X4 940 |url=https://www.amd.com/en/product/2081 |website=AMD}}</ref>
| rowspan=3 | Jul 27, 2017
| rowspan=19 | 28&nbsp;nm
| rowspan=19 | BR-A1
| rowspan=3 | [2]4
| 3.2
| 3.6
| rowspan=19 | 96&nbsp;KB inst.<br />per module<br /><br />32&nbsp;KB data<br />per core
| rowspan=3 | 2×1&nbsp;MB
| rowspan=3 colspan=4 {{N/a}}
| rowspan=19 | 2400
| rowspan=4 | 65
| AD940XAGABBOX
| AD940XAGM44AB
|-
! {{rh}} | {{nowrap|Athlon X4 950}}<ref>{{cite web |title=7th Gen AMD Athlon™ X4 940 |url=https://www.amd.com/en/product/2076 |website=AMD}}</ref>
| 3.5
| 3.8
| AD950XAGABBOX
| AD950XAGM44AB
|-
! {{rh}} | {{nowrap|Athlon X4 970}}<ref>{{cite web |title=7th Gen AMD Athlon™ X4 940 |url=https://www.amd.com/en/product/2071 |website=AMD}}</ref>
| 3.8
| 4.0
| AD970XAUABBOX
| AD970XAUM44AB
|-
! {{rh}} | A6-9400<ref>{{cite web |title=AMD A6-Series A6-9400 - AD9400AGM23AB / AD9400AGABBOX |url=https://www.cpu-world.com/CPUs/Bulldozer/AMD-A6-Series%20A6-9400.html |website=CPU-World}}</ref>
| Mar 16, 2019
| rowspan=6 | [1]2
| 3.4
| 3.7
| rowspan=6 | 1&nbsp;MB
| rowspan=6 | R5
| 192:12:4<br />3 CU
| 720
| 276.4
| AD9400AGABBOX
| AD9400AGM23AB
|-
! {{rh}} | A6-9500E<ref>{{cite web |title=7th Gen A6-9500E APU |url=https://www.amd.com/en/product/2091 |website=AMD}}</ref>
| Sep 5, 2016
| rowspan=2 | 3.0
| rowspan=2 | 3.4
| rowspan=2 | 256:16:4<br />4 CU
| rowspan=2 | 800
| rowspan=2 | 409.6
| rowspan=2 | 35
| AD9500AHABBOX
| AD9500AHM23AB
|-
! {{rh}} | {{nowrap|Pro A6-9500E}}<ref>{{cite web |title=7th Gen AMD PRO A6-9500E APU |url=https://www.amd.com/en/product/6186 |website=AMD}}</ref>
| Oct 3, 2016
| 
| AD950BAHM23AB
|-
! {{rh}} | A6-9500<ref>{{cite web |title=7th Gen A6-9500 APU |url=https://www.amd.com/en/product/2096 |website=AMD}}</ref>
| Sep 5, 2016
| rowspan=2 | 3.5
| rowspan=2 | 3.8
| rowspan=2 | 384:24:6<br />6 CU
| rowspan=2 | 1029
| rowspan=2 | 790.2
| rowspan=5 | 65
| AD9500AGABBOX
| AD9500AGM23AB
|-
! {{rh}} | {{nowrap|Pro A6-9500}}<ref>{{cite web |title=7th Gen AMD PRO A6-9500 APU |url=https://www.amd.com/en/product/6181 |website=AMD}}</ref>
| Oct 3, 2016
| 
| AD950BAGM23AB
|-
! {{rh}} | A6-9550<ref>{{cite web |title=7th Gen A6-9550 APU |url=https://www.amd.com/en/product/2086 |website=AMD}}</ref>
| Jul 27, 2017
| 3.8
| 4.0
| 256:16:4<br />4 CU
| 800
| 409.6
| AD9550AGABBOX
| AD9550AGM23AB
|-
! {{rh}} | A8-9600<ref>{{cite web |title=7th Gen A8-9600 APU |url=https://www.amd.com/en/product/2101 |website=AMD}}</ref>
| Sep 5, 2016
| rowspan=10 | [2]4
| rowspan=2 | 3.1
| rowspan=2 | 3.4
| rowspan=10 | 2×1&nbsp;MB
| rowspan=10 | R7
| rowspan=6 | 384:24:6<br />6 CU
| rowspan=2 | 900
| rowspan=2 | 691.2
| AD9600AGABBOX
| AD9600AGM44AB
|-
! {{rh}} | {{nowrap|Pro A8-9600}}<ref>{{cite web |title=7th Gen AMD PRO A8-9600 APU |url=https://www.amd.com/en/product/6191 |website=AMD}}</ref>
| Oct 3, 2016
| 
| AD960BAGM44AB
|-
! {{rh}} | A10-9700E<ref>{{cite web |title=7th Gen A10-9700E APU |url=https://www.amd.com/en/product/2106 |website=AMD}}</ref>
| Sep 5, 2016
| rowspan=2 | 3.0
| rowspan=2 | 3.5
| rowspan=2 | 847
| rowspan=2 | 650.4
| rowspan=2 | 35
| AD9700AHABBOX
| AD9700AHM44AB
|-
! {{rh}} | {{nowrap|Pro A10-9700E}}<ref>{{cite web |title=7th Gen AMD PRO A10-9700E APU |url=https://www.amd.com/en/product/6166 |website=AMD}}</ref>
| Oct 3, 2016
| 
| AD970BAHM44AB
|-
! {{rh}} | A10-9700<ref>{{cite web |title=7th Gen A10-9700 APU |url=https://www.amd.com/en/product/2111 |website=AMD}}</ref>
| Sep 5, 2016
| rowspan=2 | 3.5
| rowspan=2 | 3.8
| rowspan=2 | 1029
| rowspan=2 | 790.2
| rowspan=2 | 65
| AD9700AGABBOX
| AD9700AGM44AB
|-
! {{rh}} | {{nowrap|Pro A10-9700}}<ref>{{cite web |title=7th Gen AMD PRO A10-9700 APU |url=https://www.amd.com/en/product/6161 |website=AMD}}</ref>
| Oct 3, 2016
| 
| AD970BAGM44AB
|-
! {{rh}} | A12-9800E<ref>{{cite web |title=7th Gen A12-9800E APU |url=https://www.amd.com/en/product/2116 |website=AMD}}</ref>
| Sep 5, 2016
| rowspan=2 | 3.1
| rowspan=2 | 3.8
| rowspan=4 | 512:32:8<ref>{{cite news|last1=Sang-ho|first1=Lee|title=AMD Final Heavy Equipment X Carrier ZEN Bristol Ridge A12-9800 platform change|url=https://translate.google.com/translate?sl=auto&tl=en&js=y&prev=_t&hl=en&ie=UTF-8&u=http%3A%2F%2Fwww.bodnara.co.kr%2Fbbs%2Farticle.html%3Fnum%3D134612%26mn%3D4&edit-text=|access-date=November 12, 2016|publisher=BodNara Korea|date=September 19, 2016}}</ref><br />8 CU
| rowspan=2 | 900
| rowspan=2 | 921.6
| rowspan=2 | 35
| AD9800AHABBOX
| AD9800AUM44AB
|-
! {{rh}} | {{nowrap|Pro A12-9800E}}<ref>{{cite web |title=7th Gen AMD PRO A12-9800E APU |url=https://www.amd.com/en/product/6176 |website=AMD}}</ref>
| Oct 3, 2016
| 
| AD980BAHM44AB
|-
! {{rh}} | A12-9800<ref>{{cite web |title=7th Gen A12-9800 APU |url=https://www.amd.com/en/product/2121 |website=AMD}}</ref>
| Sep 5, 2016
| rowspan=2 | 3.8
| rowspan=2 | 4.2
| rowspan=2 | 1108
| rowspan=2 | 1134.5
| rowspan=2 | 65
| AD9800AUABBOX
| AD9800AUM44AB
|-
! {{rh}} | {{nowrap|Pro A12-9800}}<ref>{{cite web |title=7th Gen AMD PRO A12-9800 APU |url=https://www.amd.com/en/product/6171 |website=AMD}}</ref>
| Oct 3, 2016
| 
| AD980BAUM44AB
|}
{{Notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== "Raven Ridge" (2018) ====
{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 14&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* [[Engineering:Transistor|Transistor]]s: 4.94 billion
* [[Engineering:Die (integrated circuit)|Die]] size: 210&nbsp;mm²
* [[Engineering:Socket AM4|Socket AM4]]
* Zen CPU cores
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[FMA instruction set#FMA3 instruction set|FMA3]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[RDRAND]], Turbo Core
* Dual-channel DDR4 memory controller
* Fifth generation [[Graphics Core Next#GCN 5th Generation (Vega)|GCN]] based GPU
* Video Core Next (VCN) 1.0

==== "Picasso" (2019) ====
{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 12&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* [[Engineering:Transistor|Transistor]]s: 4.94 billion
* [[Engineering:Die (integrated circuit)|Die]] size: 210&nbsp;mm²
* [[Engineering:Socket AM4|Socket AM4]]
* [[Engineering:Zen+|Zen+]] CPU cores
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[FMA instruction set#FMA3 instruction set|FMA3]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[RDRAND]], Turbo Core
* Dual-channel DDR4 memory controller
* Fifth generation [[Graphics Core Next#GCN 5th Generation (Vega)|GCN]] based GPU
* Video Core Next (VCN) 1.0

==== "Renoir" (2020) ====
{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 7&nbsp;nm by [[Company:TSMC|TSMC]]
* [[Engineering:Socket AM4|Socket AM4]]
* Up to eight [[Engineering:Zen 2|Zen 2]] CPU cores
* Dual-channel DDR4 memory controller

==== "Cezanne" (2021) ====
{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 7&nbsp;nm by [[Company:TSMC|TSMC]]
* [[Engineering:Socket AM4|Socket AM4]]
* Up to eight [[Engineering:Zen 3|Zen 3]] CPU cores
* Dual-channel DDR4 memory controller

=== Non APU or Radeon Graphics branded ===
==== "Raphael" (2022) ====

{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 5&nbsp;nm (CCD) and 6&nbsp;nm (cIOD) by [[Company:TSMC|TSMC]]
* [[Engineering:Socket AM5|Socket AM5]]
* Up to sixteen [[Engineering:Zen 4|Zen 4]] CPU cores
* Dual-channel DDR5 memory controller

* Basic iGPU

== Server APUs ==
=== Opteron X2100-series "Kyoto" (2013) & "Steppe Eagle" (2016) ===
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm
* Socket FT3 (BGA)
* 4 CPU Cores ([[Engineering:Jaguar (microarchitecture)|Jaguar]] & [[Engineering:Puma (microarchitecture)|Puma]] microarchitecture)
* L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, SSE4.1, SSE4.2, [[Advanced Vector Extensions|AVX]], [[F16C]], CLMUL, [[AES instruction set|AES]], MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], AMD-V support
* Single-channel DDR3 memory controller
* Turbo Dock Technology, C6 and CC6 low power states
* GPU based on 2nd generation [[Graphics Core Next]] (GCN) architecture

{| class="wikitable" style="text-align: center"
|-
! rowspan="3" | Model
! rowspan="3" | Released
! rowspan="3" | Fab
! rowspan="3" | Step.
! colspan="4" | CPU
! colspan="4" | GPU
! rowspan="3" | DDR3<br />memory<br />support
! rowspan="3" | TDP<br />(W)
! rowspan="3" | Part number
! rowspan="3" | Release<br />price<br />({{wipe|United States dollar}})
|-
! rowspan="2" | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]
! rowspan="2" | Clock<br />(GHz)
! colspan="2" | [[Cache (computing)|Cache]]{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan="2" | Model
! rowspan="2" | Config
! rowspan="2" | Clock<br />(MHz)
! rowspan="2" | Processing<br />power<br />([[FLOPS|GFLOPS]]){{efn|name="SFLOPS"}}
|-
! L1
! L2
|-
! style="text-align: left" | [https://www.amd.com/en/product/1566 X1150]<ref>{{cite web |title=AMD Opteron X1150 - OX1150IPJ44HM |url=https://www.cpu-world.com/CPUs/Jaguar/AMD-Opteron%20X%20series%20X1150.html |website=CPUWorld |access-date=November 13, 2023}}</ref>
| rowspan="2" | May 29, 2013<ref>{{cite press release |date=May 29, 2013 |title=AMD Launches the AMD Opteron X-Series Family: the Industry’s Highest Performance Small Core x86 Server Processors |url=https://www.amd.com/en/press-releases/amd-launches-the-2013may29 |website=AMD |access-date=November 13, 2023}}</ref>
| rowspan="3" | 28&nbsp;nm
| rowspan="2" | 
| rowspan="3" | 4 (4)
| 2.0
| rowspan="3" | 32&nbsp;KB inst.<br />32&nbsp;KB data<br /><br />per core
| rowspan="3" | 2&nbsp;MB
| colspan="4" {{N/a}}
| rowspan="2" | 1600
| 9&ndash;17
| OX1150IPJ44HM
| $64
|-
! style="text-align: left" | [https://web.archive.org/web/20150621165854/http://products.amd.com/en-us/WorkstationAPUDetail.aspx?id=78 X2150]
| 1.9
| R3 (HD&nbsp;8400)
| rowspan="2" | 128:8:4<br />2 CU
| 266&ndash;600
| 28.9
| 11&ndash;22
| OX2150IAJ44HM
| $99
|-
! style="text-align: left" | [https://web.archive.org/web/20170103141209/https://www.amd.com/en-us/products/server/opteron-x/x2170 X2170]
| Sep 1, 2016
| 
| 2.4
| R5
| 655&ndash;800
| 153.6
| 1866
| 11&ndash;25
| OX2170IXJ44JB
| 
|}
{{Notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

=== Opteron X3000-series "Toronto" (2017) ===
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm
* Socket FP4 (BGA)
* Two or Four CPU cores based on the [[Engineering:Excavator (microarchitecture)|Excavator]] microarchitecture<ref>{{cite news|last1=Kennedy|first1=Patrick|title=New HPE ProLiant MicroServer Gen10 Powered by AMD Opteron X3000 APUs|url=https://www.servethehome.com/new-hpe-proliant-microserver-gen10-powered-amd-opteron-x3000-apus/|access-date=June 5, 2017|date=June 5, 2017}}</ref><ref name="OpteronX3000">{{cite web |title=Opteron Family |url=https://www.amd.com/en/opteron |website=AMD |access-date=June 5, 2017 |url-status=dead |archive-url=https://web.archive.org/web/20170520180537/https://www.amd.com/en/opteron |archive-date=2017-05-20}}</ref>
* L1 Cache: 32 KB Data per core and 96 KB Instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], [[RDRAND]]
* Dual-channel DDR4 memory controller
* GPU based on 3rd generation [[Graphics Core Next#Graphics Core Next 3|Graphics Core Next]] (GCN) architecture

{| class="wikitable" style="text-align: center"
|-
! rowspan="3" | Model
! rowspan="3" | Released 
! rowspan="3" | Fab
! rowspan="3" | Step.
! colspan="5" | CPU
! colspan="4" | GPU
! rowspan="3" | DDR4<br />memory<br />support
! rowspan="3" | TDP<br />(W)
! rowspan="3" | Part number
! rowspan="3" | Release<br />price<br />({{wipe|United States dollar}})
|-
! rowspan="2" | [Modules/[[Floating-point unit|FPUs]]]<br />[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! colspan="2" | [[Clock rate]] ([[Hertz|GHz]])
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan="2" | Model
! rowspan="2" | Config
! rowspan="2" | Clock<br />(MHz)
! rowspan="2" | Processing<br />power<br />([[FLOPS|GFLOPS]]){{efn|name="SFLOPS"}}
|-
! Base
! [[Engineering:AMD Turbo Core|Boost]]
! L1
! L2
|-
! style="text-align: left" | X3216<ref name="OpteronX3000" /><ref>{{cite web |title=AMD Opteron X3216 - OX3216AAY23KA |url=https://www.cpu-world.com/CPUs/Bulldozer/AMD-Opteron%20X3000%20series%20X3216.html |website=CPUWorld |access-date=November 13, 2023}}</ref>
| June 2017
| rowspan="3" | 28&nbsp;nm
| rowspan="3" | 01h
| [1]2
| 1.6
| 3.0
| rowspan=3 | 96 KB inst.<br />per module<br /><br />32 KB data<br />per core
| 1&nbsp;MB
| R5
| 256:16:4<br />4 CU
| rowspan="3" | 800
| 409.6
| 1600
| 12&ndash;15
| OX3216AAY23KA
| rowspan="3" | OEM for HP
|-
! style="text-align: left" | X3418<ref name="OpteronX3000" /><ref>{{cite web |title=AMD Opteron X3418 - OX3418AAY43KA |url=https://www.cpu-world.com/CPUs/Bulldozer/AMD-Opteron%20X3000%20series%20X3418.html |website=CPUWorld |access-date=November 13, 2023}}</ref>
| 
| rowspan="2" | [2]4
| 1.8
| 3.2
| rowspan="2" | 2&nbsp;MB
| rowspan="2" | R7
| 384:24:6<br />6 CU
| 614.4
| rowspan="2" | 2400
| rowspan="2" | 12&ndash;35
| OX3418AAY43KA
|-
! style="text-align: left" | X3421<ref name="OpteronX3000" /><ref>{{cite web |title=AMD Opteron X3421 - OX3421AAY43KA |url=https://www.cpu-world.com/CPUs/Bulldozer/AMD-Opteron%20X3000%20series%20X3421.html |website=CPUWorld |access-date=November 13, 2023}}</ref>
| June 2017
| 2.1
| 3.4
| 512:32:8<br />8 CU
| 819.2
| OX3421AAY43KA
|}
{{Notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

== Mobile processors with 3D graphics ==
=== APU or Radeon Graphics branded ===
==== Sabine: "Llano" (2011) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 32&nbsp;nm on [[Company:GlobalFoundries|GlobalFoundries]] [[Physics:Silicon on insulator|SOI]] process 
* Socket FS1
* Upgraded ''Stars'' (AMD 10h architecture) codenamed ''Husky'' CPU cores (K10.5) with no L3 cache, and with ''Redwood''-class integrated graphics on die 
* L1 Cache: 64 KB Data per core and 64 KB Instructions per core(''BeaverCreek'' for the dual-core variants and ''WinterPark'' for the quad-core variants)
* Integrated PCIe 2.0 controller
* GPU: TeraScale 2
* Select models support Turbo Core technology for faster CPU operation when the thermal specification permits
* Support for 1.35&nbsp;V DDR3L-1333 memory, in addition to regular 1.5&nbsp;V DDR3 memory specified
* 2.5&nbsp;GT/s UMI
* [[MMX (instruction set)|MMX]], [[Engineering:3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], SSE4a, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], AMD64, AMD-V
* [[Engineering:PowerNow!|PowerNow!]]

{| class="wikitable sortable" style="text-align: center"
|-
! rowspan=3 | Model 
! rowspan=3 | Released
! rowspan=3 | Fab
! rowspan=3 | Step.
! colspan=6 | CPU
! colspan=4 | GPU
! rowspan=3 | DDR3
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]
! rowspan=2 | Clock
(GHz)
! rowspan=2 | Turbo
(GHz)
! colspan=3 | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | GFLOPS{{efn|name="SFLOPS"}}
|-
! L1
! L2
! L3
|-
! {{rh}} | {{visible anchor|E2-3000M|text=[https://web.archive.org/web/20140907121951/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=5 {{nowrap|E2-3000M}}]}}
| 2011
6/14
| rowspan=19 | 32&nbsp;nm
| rowspan=19 | B0
| rowspan=8 | 2 (2)
| 1.8
| 2.4
| rowspan=19 | 64 KB inst.<br />64 KB data<br /><br />per core
| 2× 512KB
| rowspan=19 {{n/a}}
| HD 6380G
| 160:8:4
| 400
| 128
| rowspan=10 | 1333
| 35
| EM3000DDX22GX
|-
! colspan="2" |  || colspan="2" | || || colspan="4" | || colspan="2" |
|-
! {{rh}} | {{visible anchor|A4-3300M|text=[https://web.archive.org/web/20140907095843/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=6 {{nowrap|A4-3300M}}]}}
| 2011
6/14
| rowspan=2 | 1.9
| rowspan=3 | 2.5
| 2× 1MB
| rowspan=6 | HD 6480G
| 240:12:4
| 444
| 213.1
| rowspan=2 | 35
| AM3300DDX23GX
|-
! {{rh}} | {{visible anchor|A4-3305M|text=[https://web.archive.org/web/20140907100032/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=29 {{nowrap|A4-3305M}}]}}
| December 7, 2011
| 2× 512KB
| 160:8:4
| 593
| 189.7
| AM3305DDX22GX
|-
! {{rh}} | {{visible anchor|A4-3310MX|text=[https://web.archive.org/web/20140907122040/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=7 {{nowrap|A4-3310MX}}]}}
| 2011
6/14
| 2.1
| rowspan=3 | 2× 1MB
| rowspan=3 | 240:12:4
| rowspan=3 | 444
| rowspan=3 | 213.1
| 45
| AM3310HLX23GX
|-
! {{rh}} | {{visible anchor|A4-3320M|text=[https://web.archive.org/web/20140907122036/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=28 {{nowrap|A4-3320M}}]}}
| rowspan=2 | December 7, 2011
| 2.0
| rowspan=3 | 2.6
| 35
| AM3320DDX23GX
|-
! {{rh}} | {{visible anchor|A4-3330MX|text=[https://web.archive.org/web/20140907121957/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=27 {{nowrap|A4-3330MX}}]}}
| 2.2
| rowspan=2 | 45
| AM3330HLX23GX
|-
! {{rh}} | {{visible anchor|A4-3330MX|text=[https://web.archive.org/web/20150620113825/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=88 {{nowrap|A4-3330MX}}]}}
|
| 2.3
| 2× 512KB
| 160:8:4
| 593
| 189.7
| AM3330HLX23HX
|-
! colspan="2" |  || colspan="3" | || ||  colspan="4" | || colspan="2" |
|-
! {{rh}} | {{visible anchor|A6-3400M|text=[https://web.archive.org/web/20140907122119/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=8 {{nowrap|A6-3400M}}]}}
| rowspan=2 | 2011
6/14
| rowspan=10 | 4 (4)
| 1.4
| rowspan=2 | 2.3
| rowspan=10 | 4× 1MB
| rowspan=4 | HD 6520G
| rowspan=4 | 320:16:8
| rowspan=4 | 400
| rowspan=4 | 256
| 35
| AM3400DDX43GX
|-
! {{rh}} | {{visible anchor|A6-3410MX|text=[https://web.archive.org/web/20140907095836/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=9 {{nowrap|A6-3410MX}}]}}
| 1.6
| 1600
| 45
| AM3410HLX43GX
|-
! {{rh}} | {{visible anchor|A6-3420M|text=[https://web.archive.org/web/20150620120654/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=26 {{nowrap|A6-3420M}}]}}
| rowspan=2 | December 7, 2011
| 1.5
| rowspan=2 | 2.4
| 1333
| 35
| AM3420DDX43GX
|-
! {{rh}} | {{visible anchor|A6-3430MX|text=[https://web.archive.org/web/20140907122042/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=25 {{nowrap|A6-3430MX}}]}}
| 1.7
| 1600
| 45
| AM3430HLX43GX
|-
! colspan="2" |  || colspan="2" | || colspan="7" |
|-
! {{rh}} | {{visible anchor|A8-3500M|text=[https://web.archive.org/web/20140907095838/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=10 {{nowrap|A8-3500M}}]}}
| rowspan=2 | 2011
6/14
| 1.5
| 2.4
| rowspan=5 | HD 6620G
| rowspan=5 | 400:20:8
| rowspan=5 | 444
| rowspan=5 | 355.2
| 1333
| 35
| AM3500DDX43GX
|-
! {{rh}} | {{visible anchor|A8-3510MX|text=[https://web.archive.org/web/20140907122121/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=11 {{nowrap|A8-3510MX}}]}}
| 1.8
| rowspan=2 | 2.5
| 1600
| 45
| AM3510HLX43GX
|-
! {{rh}} | {{visible anchor|A8-3520M|text=[https://web.archive.org/web/20140907095840/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=24 {{nowrap|A8-3520M}}]}}
| December 7, 2011
| 1.6
| 1333
| 35
| AM3520DDX43GX
|-
! {{rh}} | {{visible anchor|A8-3530MX|text=[https://web.archive.org/web/20140907100034/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=12 {{nowrap|A8-3530MX}}]}}
| 2011
6/14
| 1.9
| 2.6
| rowspan=2 | 1600
| rowspan=2 | 45
| AM3530HLX43GX
|-
! {{rh}} | {{visible anchor|A8-3550MX|text=[https://web.archive.org/web/20140907100109/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=23 {{nowrap|A8-3550MX}}]}}
| December 7, 2011
| 2.0
| 2.7
| AM3550HLX43GX
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== Comal: "Trinity" (2012) ====
[[File:AMD FS1 CPU Socket-top closed - with AMD A10-4600M (AM4600DEC44HJ) APU PNr°0810.jpg|thumb|An AMD A10-4600M APU]]
* [[Engineering:Semiconductor device fabrication|Fabrication]] 32&nbsp;nm on GlobalFoundries SOI process
* Socket FS1r2, FP2
* Based on the [[Engineering:Piledriver (microarchitecture)|Piledriver architecture]]
* L1 Cache: 16 KB Data per core and 64 KB Instructions per module
* GPU: TeraScale 3 (VLIW4)
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], Turbo Core
* Memory support: 1.35&nbsp;V DDR3L-1600 memory, in addition to regular 1.5&nbsp;V DDR3 memory specified (Dual-channel)
* 2.5&nbsp;GT/s UMI
* Transistors: 1.303&nbsp;billion
* Die size: 246&nbsp;mm²
{{clr}}
{| class="wikitable sortable" style="text-align: center"
|-
! rowspan=3 | Model number
! rowspan=3 | Released
! rowspan=3 | Fab
! rowspan=3 | Step.
! rowspan=3 |Socket
! colspan="5" | CPU
! colspan=5 | GPU
! rowspan=3 | DDR3
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [Modules/[[Floating-point unit|FPUs]]]
[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! rowspan=2 | Clock
(GHz)
! rowspan=2 | Turbo
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan=2 | Model
! rowspan=2 | Config{{NoteTag|name=fn_2|[[Unified shader model|Unified shader processors]] (USPs): [[Texture mapping unit]]s (TMUs): [[Render output unit]]s (ROPs). 1 CU (Compute Unit) {{=}} 64 USPs: 4 TMUs : 1 ROPs}}
! rowspan=2 | Clock
(MHz)
! rowspan=2 | Turbo
(MHz)
! rowspan=2 | GFLOPS{{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
|-
! {{rh}} | {{visible anchor|A4-4355M|text=[https://web.archive.org/web/20140907095759/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=51 {{nowrap|A4-4355M}}]}}
| September 27, 2012
| rowspan=11 |32&nbsp;nm
| rowspan=11 | TN-A1
| rowspan=6 |FP2
| rowspan=2 | [1]2
| 1.9
| 2.4
| rowspan=11 | 64 KB inst.<br />per module<br /><br />16 KB data<br />per core
| 1
| HD 7400G
| 192:12:4<br />3 CU
| rowspan=2 | 327
| rowspan=3 | 424
| 125.5
| rowspan=3 | 1333
| rowspan=2 | 17
| AM4355SHE23HJ
|-
! {{rh}} | {{visible anchor|A6-4455M|text=[https://web.archive.org/web/20140907122201/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=38 {{nowrap|A6-4455M}}]}}
| May 15, 2012
| 2.1
| 2.8
| 2
| HD 7500G
| 256:16:8<br /> 4 CU
| 167.4
| AM4455SHE24HJ
|-
! {{rh}} | {{visible anchor|A8-4555M|text=[https://web.archive.org/web/20140907122330/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=50 {{nowrap|A8-4555M}}]}}
| September 27, 2012
| rowspan=4 | [2]4
| 1.6
| 2.4
| rowspan=4 | 2×
2MB
| HD 7600G
| 384:24:8<br />6 CU
| 320
| 245.7
| 19
| AM4555SHE44HJ
|-
! {{rh}} class="table-rh" |{{nowrap|A8-4557M}}<ref name="CPUWorldA8">{{cite web|url=http://www.cpu-world.com/news_2013/2013031901_AMD_lists_A8-4557M_and_A10-4657M_mobile_APUs.html|title=AMD lists A8-4557M and A10-4657M mobile APUs|website=www.cpu-world.com|access-date=September 17, 2018}}</ref>
| Mar
2013
| 1.9
| 2.8
| HD 7000
| 256:16:8<br />4 CU
| 497
| 655
| 254.4
| (L)1600
| 35
| AM4557DFE44HJ
|-
! {{rh}} class="table-rh" |[https://web.archive.org/web/20140907122244/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=37 {{nowrap|A10-4655M}}]
|May 15, 2012
| 2.0
| 2.8
| HD 7620G
| rowspan=2 |384:24:8<br />6 CU
| 360
| 496
| 276.4
| 1333
| 25
| AM4655SIE44HJ
|-
! {{rh}} class="table-rh" |{{nowrap|A10-4657M}}<ref name="CPUWorldA8" />
| Mar
2013
| 2.3
| 3.2
| HD 7000
| 497
| 686
| 381.6
| (L)1600
| rowspan=6 | 35
| AM4657DFE44HJ
|-
! colspan="2" |  || colspan="4" | || || colspan="6" | 
!
|-
! {{rh}} | {{visible anchor|A4-4300M|text=[https://web.archive.org/web/20140907095950/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=43 {{nowrap|A4-4300M}}]}}
| rowspan=4 |May 15, 2012
| rowspan=4 |FS1r2
| rowspan=2 | [1]2
| 2.5
| 3.0
| rowspan=2 | 1
| HD 7420G
| 128:8:4<br />2 CU
| 480
| 655
| 122.8
| rowspan=4 | 1600
| AM4300DEC23HJ
|-
! {{rh}} | {{visible anchor|A6-4400M|text=[https://web.archive.org/web/20140907095638/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=36 {{nowrap|A6-4400M}}]}}
| 2.7
| 3.2
| HD 7520G
| 192:12:4<br />3 CU
| rowspan=3 | 496
| rowspan=3 | 685
| 190.4
| AM4400DEC23HJ
|-
! {{rh}} | {{visible anchor|A8-4500M|text=[https://web.archive.org/web/20140907121821/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=35 {{nowrap|A8-4500M}}]}}
| rowspan=2 | [2]4
| 1.9
| 2.8
| rowspan=2 | 2×
2MB
| HD 7640G
| 256:16:8<br />4 CU
| 253.9
| AM4500DEC44HJ
|-
! {{rh}} | {{visible anchor|A10-4600M|text=[https://web.archive.org/web/20140907121647/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=34 {{nowrap|A10-4600M}}]}}
| 2.3
| 3.2
| HD 7660G
| 384:24:8<br />6 CU
| 380.9
| AM4600DEC44HJ
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}
{{notefoot}}

==== "Richland" (2013) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 32&nbsp;nm on GlobalFoundries SOI process
* Socket FS1r2, FP2
* ''Elite Performance APU''.<ref>{{cite web |url=http://techreport.com/news/24482/amd-intros-35w-richland-mobile-apus |title=AMD intros 35W Richland mobile APUs |date=March 12, 2013 |access-date=November 10, 2013}}</ref><ref>Poeter, Damon. (March 12, 2013) [https://www.pcmag.com/article2/0,2817,2416506,00.asp AMD Bakes New Interface Capabilities Into Richland APUs | News & Opinion]</ref>
* CPU: [[Engineering:Piledriver (microarchitecture)|Piledriver architecture]]
** L1 Cache: 16 KB Data per core and 64 KB Instructions per module
* GPU: TeraScale 3 (VLIW4)
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], Turbo Core

{| class="wikitable sortable" style="text-align: center"
|-
! rowspan=3 | Model number 
! rowspan=3 | Released
! rowspan=3 | Fab
! rowspan=3 | Step.
! rowspan=3 | Socket
! colspan="5" | CPU
! colspan=5 | GPU
! rowspan=3 | DDR3
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [Modules/[[Floating-point unit|FPUs]]]
[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! rowspan=2 | Clock
(GHz)
! rowspan=2 | Turbo
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan=2 | Model
! rowspan=2 | Config{{NoteTag|name=fn_2|[[Unified shader model|Unified shader processors]] (USPs): [[Texture mapping unit]]s (TMUs): [[Render output unit]]s (ROPs). 1 CU (Compute Unit) {{=}} 64 USPs: 4 TMUs : 1 ROPs}}
! rowspan=2 | Clock
(MHz)
! rowspan=2 | Turbo
(MHz)
! rowspan=2 | GFLOPS{{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
|-
! {{rh}} | {{visible anchor|A4-5145M|text=[https://web.archive.org/web/20150620114958/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=77 {{nowrap|A4-5145M}}]}}
| rowspan=4 | 2013/5
| rowspan=12 | 32&nbsp;nm
| rowspan=12 | RL-A1
| rowspan=4 | FP2
| rowspan=2 | [1]2
| 2.0
| 2.6
| rowspan=12 | 64 KB inst.<br />per module<br /><br />16 KB data<br />per core
| rowspan=2 | 1
| HD 8310G
| 128:8:4<br />2 CU
| 424
| 554
| 108.5
| rowspan=4 | (L)1333
| rowspan=2 | 17
| AM5145SIE44HL
|-
! {{rh}} | {{visible anchor|A6-5345M|text=[https://web.archive.org/web/20140907122123/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=76 {{nowrap|A6-5345M}}]}}
| 2.2
| 2.8
| HD 8410G
| 192:12:4<br />3 CU
| rowspan=2 | 450
| 600
| 172.8
| AM5345SIE44HL
|-
! {{rh}} | {{visible anchor|A8-5545M|text=[https://web.archive.org/web/20150620115406/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=75 {{nowrap|A8-5545M}}]}}
| rowspan=2 | [2]4
| 1.7
| 2.7
| rowspan=2 | 4
| HD 8510G
| rowspan=2 | 384:28:8<br />6 CU
| 554
| 345.6
| 19
| AM5545SIE44HL
|-
! {{rh}} | {{visible anchor|A10-5745M|text=[https://web.archive.org/web/20150620124410/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=74 {{nowrap|A10-5745M}}]}}
| 2.1
| 2.9
| HD 8610G
| 533
| 626
| 409.3
| 25
| AM5745SIE44HL
|-
! colspan="2" |
! colspan="4" | || || colspan="8" |
|-
! {{rh}} | {{visible anchor|A4-5150M|text=[https://web.archive.org/web/20150620113911/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=65 {{nowrap|A4-5150M}}]}}
| rowspan=2 | 2013 Q1
| rowspan="2" | FS1r2
| rowspan=3 | [1]2
| 2.7
| 3.3
| rowspan=3 | 1
| HD 8350G
| 128:8:4<br />2 CU
| rowspan=3 | 533
| rowspan=7 | 720
| 136.4
| rowspan=2 | 1600
| rowspan=7 | 35
| AM5150DEC23HL
|-
! {{rh}} | {{visible anchor|A6-5350M|text=[https://web.archive.org/web/20140907122246/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=64 {{nowrap|A6-5350M}}]}}
| rowspan=2 | 2.9
| rowspan=2 | 3.5
| rowspan=2 | HD 8450G
| rowspan=2 | 192:12:4<br />3 CU
| rowspan=2 | 204.6
| AM5350DEC23HL
|-
! {{rh}} | {{visible anchor|A6-5357M|text=[https://web.archive.org/web/20150620125650/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=73 {{nowrap|A6-5357M}}]}}
| 2013/5
|FP2
| (L)1600
| AM5357DFE23HL
|-
! {{rh}} | {{visible anchor|A8-5550M|text=[https://web.archive.org/web/20150620122653/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=63 {{nowrap|A8-5550M}}]}}
| 2013 Q1
|FS1r2
| rowspan="4" | [2]4
| rowspan=2 | 2.1 
| rowspan=2 | 3.1
| rowspan=4 | 4
| rowspan=2 | HD 8550G
| rowspan=2 | 256:16:8<br />4 CU
| 515
| 263.6
| 1600
| AM5550DEC44HL
|-
! {{rh}} | {{visible anchor|A8-5557M|text=[https://web.archive.org/web/20150620114809/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=72 {{nowrap|A8-5557M}}]}}
| 2013/5
|FP2
| 554
| 283.6
| (L)1600
| AM5557DFE44HL
|-
! {{rh}} | {{visible anchor|A10-5750M|text=[https://web.archive.org/web/20150620121303/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=62 {{nowrap|A10-5750M}}]}}
| 2013 Q1
|FS1r2
| rowspan="2" | 2.5
| rowspan=2 | 3.5
| rowspan=2 | HD 8650G
| rowspan=2 | 384:24:8<br />6 CU
| 533
| 409.3
| 1866
| AM5750DEC44HL
|-
! {{rh}} | {{visible anchor|A10-5757M|text=[https://web.archive.org/web/20150620124215/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=71 {{nowrap|A10-5757M}}]}}
| 2013/5
|FP2
| 600
| 460.8
| (L)1600
| AM5757DFE44HL
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}
{{notefoot}}

==== "Kaveri" (2014) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm
* Socket FP3
* Up to 4 [[Engineering:Steamroller (microarchitecture)|Steamroller]] x86 CPU cores with 4&nbsp;MB of L2 cache.<ref>{{cite web |url=http://www.technationnews.com/2013/11/24/amd-kaveri-apu-with-steamrollerb-core-features-20-cpu-and-30-gpu-performance-uplift-over-richland-platform-details-unveiled/ |title=AMD Kaveri APU with SteamrollerB Core Features 20% CPU and 30% GPU Performance Uplift over Richland – Platform Details Unveiled &#124; TechNationNews.com |access-date=November 26, 2013 |url-status=dead |archive-url=https://web.archive.org/web/20131203121409/http://www.technationnews.com/2013/11/24/amd-kaveri-apu-with-steamrollerb-core-features-20-cpu-and-30-gpu-performance-uplift-over-richland-platform-details-unveiled/ |archive-date=December 3, 2013 }}</ref>
* L1 Cache: 16 KB Data per core and 96 KB Instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], Turbo Core
* Three to eight Compute Units (CUs) based on [[Graphics Core Next]] (GCN)<ref name="wccftech" /> microarchitecture; 1 Compute Unit (CU) consists of 64 [[Unified shader model|Unified Shader Processors]] : 4 [[Texture mapping unit|Texture Mapping Units]] (TMUs) : 1 [[Render output unit|Render Output Unit]] (ROPs)
* [[Engineering:AMD Accelerated Processing Unit#HSA|AMD Heterogeneous System Architecture]] (HSA) 2.0
* [[Engineering:Semiconductor intellectual property core|SIP blocks]]: Unified Video Decoder, Video Coding Engine, TrueAudio<ref name="SemiAccurate"/>
* Dual-channel (2x64-bit) DDR3 memory controller
* Integrated custom ARM Cortex-A5 co-processor<ref name="arstechnica.com"/> with TrustZone Security Extensions<ref name="technewspedia.com"/>

{| class="wikitable sortable" style="text-align: center"
|-
! rowspan=3 | Model number
! rowspan=3 | Released 
! rowspan=3 | Fab
! colspan="5" | CPU
! colspan=5 | GPU
! rowspan=3 |DDR3

Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [Modules/[[Floating-point unit|FPUs]]]
[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! rowspan=2 | Clock
(GHz)
! rowspan=2 | Turbo
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | Turbo
(MHz)
! rowspan=2 | GFLOPS{{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
|-
! style="text-align:right; font-size:85%;" | [https://web.archive.org/web/20140907095919/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=124 {{nowrap|A6-7000}}]
| rowspan=12 | June 2014 
| rowspan=12 | 28&nbsp;nm
| rowspan=2 | [1]2
| rowspan=2 | 2.2
| rowspan=2 | 3.0
| rowspan=12 | 96 KB inst.<br />per module<br /><br />16 KB data<br />per core
| rowspan=2 | 1
| rowspan=2 | R4
| rowspan=2 | 192:12:3<br />3 CU
| 494
| 533
| 189.6
| 1333
| rowspan=2 | 17
| AM7000ECH23JA
|-
! style="text-align:right; font-size:85%;" | [https://web.archive.org/web/20140725140917/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=128 {{nowrap|A6 PRO - 7050B}}]
| 533
| {{n/a}} 
| 204.6
| 1600
| AM705BECH23JA
|-
! || colspan="3" | || || colspan="8" | 
|-
! style="text-align:right; font-size:85%;" | [https://web.archive.org/web/20140907100118/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=123 {{nowrap|A8-7100}}]
| rowspan=9 | [2]4
| 1.8
| 3.0
| rowspan=9 | 2× 2 MB
| rowspan=2 | R5
| rowspan=2 | 256:16:4<br />4 CU
| 450
| 514
| 230.4
| rowspan=5 | 1600
| rowspan=5 | 20
| AM7100ECH44JA
|-
! style="text-align:right; font-size:85%;" | [https://web.archive.org/web/20140725140613/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=127 {{nowrap|A8 PRO - 7150B}}]
| rowspan="2" | 1.9
| rowspan="2" | 3.2
| 553
| {{n/a}}
| 283.1
| AM715BECH44JA
|-
! style="text-align:right; font-size:85%;" | [https://web.archive.org/web/20140907121959/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=122 {{nowrap|A10-7300}}]
| rowspan=2 | R6
| rowspan=3 | 384:24:8<br />6 CU
| 464
| 533
| 356.3
| AM7300ECH44JA
|-
! style="text-align:right; font-size:85%;" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Laptops/A10-PRO-7350B-with-Radeon%E2%84%A2-R6-Graphics/113 {{nowrap|A10 PRO - 7350B}}]
| rowspan="2" | 2.1
| rowspan="2" | 3.3
| 533
| {{n/a}}
| 424.7
| AM735BECH44JA
|-
! style="text-align:right; font-size:85%;" | [https://web.archive.org/web/20140907095913/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=121 {{nowrap|FX-7500}}]
| R7
| 498
| 553
| 382.4
| FM7500ECH44JA
|-
! || colspan="2" | ||  colspan="7" | || 
|-
! style="text-align:right; font-size:85%;" | [https://web.archive.org/web/20140907122045/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=120 {{nowrap|A8-7200P}}]
| 2.4
| 3.3
| R5
| 256:16:4<br />4 CU
| 553
| 626
| 283.1
| rowspan=2 | 1866
| rowspan=3 | 35
| AM740PDGH44JA
|-
! style="text-align:right; font-size:85%;" | [https://web.archive.org/web/20140907121954/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=119 {{nowrap|A10-7400P}}]
| 2.5
| 3.4
| R6
| 384:24:8<br />6 CU
| 576
| 654
| 442.3 
| AM740PDGH44JA
|-
! style="text-align:right; font-size:85%;" | [https://web.archive.org/web/20140907100113/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=118 {{nowrap|FX-7600P}}]
| 2.7
| 3.6
| R7
| 512:32:8<br />8 CU
| 600
| 686
| 614.4
| 2133
| FM760PDGH44JA
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== "Carrizo" (2015) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm
* Socket FP4
* Up to 4 [[Engineering:Excavator (microarchitecture)|Excavator]] x86 CPU cores
* L1 Cache: 32 KB Data per core and 96 KB Instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], [[RDRAND]], Turbo Core
* GPU based on [[Graphics Core Next]] 1.2

{| class="wikitable sortable" style="text-align: center"
! style="text-align:left" rowspan="3" | Model number 
! rowspan=3 | Released
! rowspan=3 | Fab
! colspan="5" | CPU
! colspan="4" | GPU
! rowspan=3 | DDR
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [Modules/[[Floating-point unit|FPUs]]]
[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! rowspan=2 | Clock
(GHz)
! rowspan=2 | Turbo
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | GFLOPS{{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
|-
! style="text-align:right; font-size:85%;" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Laptops/A6-8500P-with-Radeon%E2%84%A2-R5-Graphics/126 {{nowrap|A6-8500P}}]
| rowspan=2 | June 2015
| rowspan=13 | 28&nbsp;nm
| rowspan=3 | [1]2
| rowspan=2 | 1.6
| rowspan=2 | 3.0
| rowspan=13 | 96 KB inst.<br />per module<br /><br />32&nbsp;KB data<br />per core
| rowspan=3 | 1
| rowspan=3 | R5
| rowspan=3 | 256:16:4<br />4 CU
| rowspan=3 | 800
| rowspan=3 | 409.6
| rowspan=2 | 3)1600
| rowspan=13 | 12-
35
| AM850PAAY23KA
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A6-APU-for-Laptops/AMD-PRO-A6-8500B-with-Radeon%E2%84%A2-R5-Graphics/161 {{nowrap|PRO A6-8500B}}]
| AM850BAAY23KA
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A6-APU-for-Laptops/6th-Gen-AMD-PRO-A6-8530B-APU/238 {{nowrap|PRO A6-8530B}}]
|Q3 2016
| 2.3
| 3.2
| 4)1866
| AM853BADY23AB
|-
! colspan="2" | 
! colspan="3" | ||  || colspan="3" | || colspan="2" | 
!
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Laptops/A8-8600P-with-Radeon%E2%84%A2-R6-Graphics/125 {{nowrap|A8-8600P}}]
| rowspan=4 | June 2015
| rowspan=9 | [2]4
| rowspan=2 | 1.6
| rowspan=2 | 3.0
| rowspan=9 | 2×
1MB
| rowspan=4 | R6
| rowspan=5 | 384:24:8<br />6 CU
| rowspan=2 | 720
| rowspan=2 | 552.9
| rowspan=4 | 3)2133
| AM860PAAY43KA
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A8-APU-for-Laptops/AMD-PRO-A8-8600B-with-Radeon%E2%84%A2-R6-Graphics/162 {{nowrap|PRO A8-8600B}}]
| AM860BAAY43KA
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Laptops/A10-8700P-with-Radeon%E2%84%A2-R6-Graphics/124 {{nowrap|A10-8700P}}]
| rowspan=2 | 1.8
| rowspan=2 | 3.2
| rowspan=2 | 800
| rowspan=2 | 614.4
| AM870PAAY43KA
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Laptops/AMD-PRO-A10-8700B-with-Radeon%E2%84%A2-R6-Graphics/163 {{nowrap|PRO A10-8700B}}]
| AM870BAAY43KA
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Laptops/6th-Gen-AMD-PRO-A10-8730B-APU/237 {{nowrap|PRO A10-8730B}}]
| Q3 2016
| 2.4
| 3.3
| R5
| 720
| 552.9
| 4)1866
| AM873BADY44AB
|-
! style="text-align:right; font-size:85%" | [http://www.cpu-world.com/CPUs/Bulldozer/AMD-A10-Series%20A10-8780P%20Extreme.html {{nowrap|A10-8780P}}]
| December 2015
| 2.0
| 3.3
| R8
| rowspan=3 | 512:32:8<br />8 CU
|
|
| 3)?
| AM878PAIY43KA
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-FX-Series-Processors/AMD-FX-Series-Processors-for-Laptops/FX-8800P-with-Radeon%E2%84%A2-R7-Graphics/123 {{nowrap|FX-8800P}}]
| rowspan=2 | June 2015
| rowspan=2 | 2.1
| rowspan=2 | 3.4
| rowspan=3 | R7
| rowspan=2 | 800
| rowspan=2 | 819.2
| rowspan=2 | 4)2133
| FM880PAAY43KA
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A12-APU-for-Laptops/AMD-PRO-A12-8800B-with-Radeon%E2%84%A2-R7-Graphics/164 {{nowrap|PRO A12-8800B}}]
| FM880BAAY43KA
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A12-APU-for-Laptops/6th-Gen-AMD-PRO-A12-8830B-APU/236 {{nowrap|PRO A12-8830B}}]
| Q3 2016
| 2.5
| 3.4
| 384:24:8<br />6 CU
| 758
| 582.1
| 4)1866
| AM883BADY44AB
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== "Bristol Ridge" (2016) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm
* Socket FP4<ref name="AMDGen7">{{cite news|last1=Cutress|first1=Ian|title=AMD Announces 7th Generation APU|url=http://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks|access-date=June 1, 2016|website=Anandtech.com|date=June 1, 2016}}</ref>
* Two or four "[[Engineering:Excavator (microarchitecture)|Excavator+]]" x86 CPU cores
* L1 Cache: 32 KB Data per core and 96 KB Instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], [[RDRAND]], Turbo Core
* GPU based on [[Graphics Core Next]] 1.2 with [[VP9]] decoding

{| class="wikitable sortable" style="text-align: center"
! style="text-align:left" rowspan=3 | Model number 
! rowspan=3 | Released
! rowspan=3 | Fab
! colspan="5" | CPU
! colspan="4" | GPU
! rowspan=3 | DDR4
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 |[Modules/[[Floating-point unit|FPUs]]]

[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! rowspan=2 | Clock
(GHz)
! rowspan=2 | Turbo
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | GFLOPS{{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A6-APU-for-Laptops/7th-Gen-AMD-PRO-A6-9500B-APU/227 Pro A6-9500B]
|| October 24, 2016
| rowspan=16 | 28nm
|| [1]2
| 2.3
| 3.2
| rowspan=16 | 96 KB inst.<br />per module<br /><br />32 KB data<br />per core
|| 1
|| R5
|| 256:16:4<br />4 CU
| 800
| 409.6
|| 1866
|| 12-
15
| 
|-
! colspan="2" | 
! colspan="3" | ||  || colspan="3" | || colspan="4" |
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A8-APU-for-Laptops/7th-Gen-AMD-PRO-A8-9600B-APU/226 Pro A8-9600B]
|| October 24, 2016
| rowspan=14 | [2]4
| rowspan=2 | 2.4
| rowspan=2 | 3.3
| rowspan=14 | 2× 1 MB
| rowspan=3 | R5
| rowspan=9 | 384:24:6<br />6 CU
| rowspan=2 | 720
| rowspan=2 | 552.9
| rowspan=5 | 1866
| rowspan=5 | 12–
15
| 
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Laptops/7th-Gen-A10-9600P-APU/197 {{nowrap|A10-9600P}}]
|June 2016
| AM960PADY44AB
|-
! style="text-align:right; font-size:85%" | {{nowrap|A10-9620P}}<ref>{{cite web|url=https://www.notebookcheck.net/AMD-A10-9620P-SoC-Benchmarks-and-Specs.234384.0.html|title=AMD A10-9620P SoC - Benchmarks and Specs|website=Notebookcheck.net|access-date=July 20, 2018}}</ref>
|2017 (OEM)
| rowspan=3 | 2.5
| rowspan=3 | 3.4
| rowspan=3 | 758
| rowspan=3 | 582.1
| 
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Laptops/7th-Gen-AMD-PRO-A10-9700B-APU/224 {{nowrap|Pro A10-9700B}}]
|| October 24, 2016
| rowspan=2 | R7
|
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A12-Series-APU-for-Laptops/7th-Gen-A12-9700P-APU/195 {{nowrap|A12-9700P}}]
| June 2016
| AM970PADY44AB
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A8-APU-for-Laptops/7th-Gen-AMD-PRO-A8-9630B/225 {{nowrap|Pro A8-9630B}}]
|| October 24, 2016
| rowspan=2 | 2.6
| rowspan=2 | 3.3
| rowspan=2 | R5
| rowspan=2 | 800
| rowspan=2 | 614.4
| rowspan=4 | 2400
| rowspan=4 | 25–
45
| 
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Laptops/7th-Gen-A10-9630P-APU/196 {{nowrap|A10-9630P}}]
| June 2016
| AM963PAEY44AB
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Laptops/7th-Gen-AMD-PRO-A10-9730B-APU/223 {{nowrap|Pro A10-9730B}}]
|| October 24, 2016
| rowspan=2 | 2.8
| rowspan=2 | 3.5
| rowspan=2 | R7
| rowspan=2 | 900
| rowspan=2 | 691.2
|
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A12-Series-APU-for-Laptops/7th-Gen-A12-9730P-APU/194 {{nowrap|A12-9730P}}]
| June 2016
| AM973PAEY44AB
|-
! colspan="2" |  || colspan="2" | || colspan="3" | || colspan="4" |
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A12-APU-for-Laptops/7th-Gen-AMD-PRO-A12-9800B-APU/222 {{nowrap|Pro A12-9800B}}]
|| October 24, 2016
| rowspan=2 | 2.7
| rowspan=2 | 3.6
| rowspan=4 | R7
| rowspan=4 | 512:32:8<br />8 CU
| rowspan=2 | 758
| rowspan=2 | 776.1
| rowspan=2 | 1866
| rowspan=2 | 12–
15
| 
|-
! style="text-align:right; font-size:85%" | [http://products.amd.com/en-us/search/APU/AMD-FX-Series-Processors/AMD-FX-Series-Processors-for-Laptops/7th-Gen-FX%E2%84%A2-9800P-APU/193] {{nowrap|FX-9800P}}<br />{{nowrap|A12-9720P}}<ref>{{cite web|url=https://www.notebookcheck.net/AMD-A12-9720P-SoC-Benchmarks-and-Specs.234448.0.html|title=AMD A12-9720P SoC - Benchmarks and Specs|website=Notebookcheck.net|access-date=July 20, 2018}}</ref><ref>{{cite web|url=http://store.hp.com/us/en/pdp/hp-pavilion-laptop---17z-touch-optional-1gz59av-1|title=HP Pavilion 17 - HP® Official Store|website=Store.hp.com|access-date=July 20, 2018}}</ref>
|June 2016<br />2017 (OEM)|| FM980PADY44AB<br />?
|-
! style="text-align:right; font-size:85%"" | [http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A12-APU-for-Laptops/7th-Gen-AMD-PRO-A12-9830B-APU/221 {{nowrap|Pro A12-9830B}}]
|| October 24, 2016
| rowspan=2 | 3.0
| rowspan=2 | 3.7
| rowspan=2 | 900
| rowspan=2 | 921.6
| rowspan=2 | 2400
| rowspan=2 | 25–
45
| 
|-
! style="text-align:right; font-size:85%"" | [http://products.amd.com/en-us/search/APU/AMD-FX-Series-Processors/AMD-FX-Series-Processors-for-Laptops/7th-Gen-FX%E2%84%A2-9830P-APU/191 {{nowrap|FX-9830P}}]
| June 2016
| FM983PAEY44AB
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

===="Raven Ridge" (2017)====
{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 14&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* [[Engineering:Transistor|Transistor]]s: 4.94 billion
* Socket FP5
* [[Engineering:Die (integrated circuit)|Die]] size: 210&nbsp;mm²
* Zen CPU cores
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[FMA instruction set#FMA3 instruction set|FMA3]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[RDRAND]], Turbo Core
* Fifth generation GCN-based GPU

==== "Picasso" (2019) ====
{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 12&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* Socket FP5
* [[Engineering:Die (integrated circuit)|Die]] size: 210&nbsp;mm²
* Up to four [[Engineering:Zen+|Zen+]] CPU cores
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[FMA instruction set#FMA3 instruction set|FMA3]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[RDRAND]], Turbo Core
* Dual-channel DDR4 memory controller
* Fifth generation GCN-based GPU

==== "Renoir" (2020) ====
{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 7&nbsp;nm by TSMC<ref>{{cite web |url=https://www.anandtech.com/show/15324/amd-ryzen-4000-mobile-apus-7nm-8core-on-both-15w-and-45w-coming-q1 |title=AMD Ryzen 4000 Mobile APUs: 7nm, 8-core on both 15W and 45W, Coming Q1 |last=Cutress |first=Ian |date=January 6, 2020 |website=anandtech.com |publisher=[[AnandTech]] |access-date=January 7, 2020}}</ref><ref>{{cite web |url=https://www.tomshardware.com/news/amd-launches-threadripper-3990x-and-ryzen-4000-renoir-apus |title=AMD Launches Threadripper 3990X and Ryzen 4000 'Renoir' APUs |last=Alcorn |first=Paul |date=January 7, 2020 |website=tomshardware.com |publisher=Tom's Hardware |access-date=January 7, 2020}}</ref><ref>{{cite web |url=https://www.theverge.com/2020/1/6/21054007/amd-7nm-ryzen-4000-cpu-ces-2020-intel-competition-laptop-processors-zen-2 |title=AMD's 7nm Ryzen 4000 CPUs are here to take on Intel's 10nm Ice Lake laptop chips |last=Gartenberg |first=Chaim |date=January 6, 2020 |website=theverge.com |publisher=[[The Verge]] |access-date=January 7, 2020}}</ref>
* Socket FP6
* [[Engineering:Die (integrated circuit)|Die]] size: 156&nbsp;mm²
* 9.8 billion transistors on one single 7&nbsp;nm monolithic die<ref name="Renoir">{{cite web|url=https://www.techpowerup.com/264801/amd-renoir-die-shot-pictured|title=AMD "Renoir" die Shot Pictured |date=March 16, 2020 |url-status=live |access-date=June 25, 2021 |archive-url= https://web.archive.org/web/20201209212449/https://www.techpowerup.com/264801/amd-renoir-die-shot-pictured |archive-date= December 9, 2020}}</ref>
* Up to eight [[Engineering:Zen 2|Zen 2]] CPU cores
* L1 [[Cache (computing)|cache]]: 64&nbsp;KB (32&nbsp;KB data + 32&nbsp;KB instruction) per core.
* L2 cache: 512&nbsp;KB per core.
* Fifth generation GCN-based GPU
* Memory support: DDR4-3200 or LPDDR4-4266 in [[Multi-channel memory architecture#Dual-channel architecture|dual-channel]] mode.
* All the CPUs support 16 [[Engineering:PCI Express#PCI Express 3.0|PCIe 3.0]] lanes.
=====U=====
=====H=====

==== "Lucienne" (2021) ====
{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 7&nbsp;nm by TSMC
* Socket FP6
* [[Engineering:Die (integrated circuit)|Die]] size: 156&nbsp;mm²
* 9.8 billion transistors on one single 7&nbsp;nm monolithic die{{Citation needed|date=November 2021}}
* Up to eight [[Engineering:Zen 2|Zen 2]] CPU cores
* Fifth generation GCN-based GPU (7&nbsp;nm Vega)


==== "Cezanne" (2021) ====
{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 7&nbsp;nm by TSMC
* Socket FP6
* [[Engineering:Die (integrated circuit)|Die]] size: 180&nbsp;mm²
* Up to eight [[Engineering:Zen 3|Zen 3]] CPU cores
* L1 [[Cache (computing)|cache]]: 64&nbsp;KB (32&nbsp;KB data + 32&nbsp;KB instruction) per core.
* L2 cache: 512&nbsp;KB per core.
* Fifth generation GCN-based GPU
* Memory support: DDR4-3200 or LPDDR4-4266 in [[Multi-channel memory architecture#Dual-channel architecture|dual-channel]] mode.
* All the CPUs support 16 [[Engineering:PCI Express#PCI Express 3.0|PCIe 3.0]] lanes.
=====U=====

=====H=====


===="Barceló" (2022) ====
{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 7&nbsp;nm by TSMC
* Socket FP6
* [[Engineering:Die (integrated circuit)|Die]] size: 180&nbsp;mm²
* Up to eight [[Engineering:Zen 3|Zen 3]] CPU cores
* L1 [[Cache (computing)|cache]]: 64&nbsp;KB (32&nbsp;KB data + 32&nbsp;KB instruction) per core.
* L2 cache: 512&nbsp;KB per core.
* Fifth generation GCN-based GPU
* Memory support: DDR4-3200 or LPDDR4-4266 in [[Multi-channel memory architecture#Dual-channel architecture|dual-channel]] mode.
* All the CPUs support 16 [[Engineering:PCI Express#PCI Express 3.0|PCIe 3.0]] lanes.

==== "Rembrandt" (2022) ====
{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 6&nbsp;nm by TSMC
* Socket FP7
* [[Engineering:Die (integrated circuit)|Die]] size: 210&nbsp;mm²
* Up to eight [[Engineering:Zen 3|Zen 3+]] CPU cores
* Second generation [[Engineering:RDNA 2|RDNA]]-based GPU

==== "Phoenix" (2023) ====

{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 4&nbsp;nm by [[Company:TSMC|TSMC]]
* Up to eight [[Engineering:Zen 4|Zen 4]] CPU cores
* Dual-channel DDR5 or LPDDR5x memory controller
* RDNA3 iGPU
* XDNA accelerator

==== "Dragon Range" (2023) ====
{{Main|Engineering:Ryzen}}
* [[Engineering:Semiconductor device fabrication|Fabrication]] 5&nbsp;nm (CCD) and 6&nbsp;nm (cIOD) by [[Company:TSMC|TSMC]]
* Up to sixteen [[Engineering:Zen 4|Zen 4]] CPU cores
* Dual-channel DDR5 memory controller
* Basic RDNA2 iGPU

== Ultra-mobile APUs ==
=== Brazos: "Desna", "Ontario", "Zacate" (2011) === <!-- AMD E-series redirects here -->
* [[Engineering:Semiconductor device fabrication|Fabrication]] 40&nbsp;nm by [[Company:TSMC|TSMC]]
* Socket FT1 (BGA-413)
* Based on the Bobcat microarchitecture<ref name="AMD Brazos Platform Preview">{{cite web|url=http://www.anandtech.com/show/4003/previewing-amds-brazos-part-1-more-details-on-zacateontario-and-fusion/2|title=Previewing AMD's Brazos, Part 1: More Details on Zacate/Ontario and Fusion|first=Anand Lal|last=Shimpi|website=Anandtech.com|access-date=July 20, 2018}}</ref>
* L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], AMD64, AMD-V
* [[Engineering:PowerNow!|PowerNow!]]
* DirectX 11 integrated graphics with UVD 3.0
* Z-series denote ''Desna''; C-series denote ''Ontario''; and the E-series denotes ''Zacate''
* 2.50 GT/s UMI (PCIe 1.0 ×4)

{| class="wikitable sortable" style="text-align: center"
|-
! rowspan=3 | Model 
! rowspan=3 | Released
! rowspan=3 | Fab
! rowspan=3 | Step.
! colspan="5" | CPU
! colspan=5 | GPU
! rowspan=3 | DDR3
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]
! rowspan=2 | Clock
(GHz)
! rowspan=2 | Turbo
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/>}}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | Turbo
(MHz)
! rowspan=2 | GFLOPS{{efn|name="SFLOPS"}}
|-
! L1
! L2
|-
! {{rh}} | {{visible anchor|Z-01|text=[https://web.archive.org/web/20140907122326/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=55 Z-01]}}
| June 1, 2011
| rowspan=10 | 40&nbsp;nm
| rowspan=4 | B0
| 2 (2)
| 1.0
| rowspan=4 {{n/a}}
| rowspan=10 | 32KB inst.<br />32KB data<br /><br />per core
| 2× 512KB
| rowspan=4 | HD 6250
| rowspan=10 | 80:8:4
| rowspan=5 | 276
| rowspan=4 {{n/a}}
| rowspan=5 | 44.1
| rowspan=5 | 1066
| 5.9
| XMZ01AFVB22GV
|-
! colspan="2" |  || colspan="2" | || || colspan="2" |
|-
! {{rh}} | {{visible anchor|C-30|text=[https://web.archive.org/web/20140907095918/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=3 C-30]}}
| rowspan=2 | January 4, 2011
| 1 (1)
| 1.2
| 512KB
| rowspan=3 | 9
| CMC30AFPB12GT
|-
! {{rh}} | {{visible anchor|C-50|text=[https://web.archive.org/web/20110906045550/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=4 C-50]}}
| rowspan=2 | 2 (2)
| rowspan=2 | 1.0
| rowspan=2 | 2× 512KB
| CMC50AFPB22GT
|-
! {{rh}} | C-60
| August 22, 2011
| C0
| 1.33
| HD 6290
| 400
| CMC60AFPB22GV
|-
! colspan="2" | 
! colspan="4" | ||  || || colspan="6" |
|-
! {{rh}} | {{visible anchor|E-240|text=[https://web.archive.org/web/20140907122038/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=2 E-240]}}
| January 4, 2011
| rowspan=3 | B0
| 1 (1)
| 1.5
| rowspan=4 {{n/a}}
| 512KB
| rowspan=3 | HD 6310
| 500
| rowspan=3 {{n/a}}
| 80
| rowspan=3 | 1066
| rowspan=4 | 18
| EME240GBB12GT
|-
! {{rh}} | {{visible anchor|E-300|text=[https://web.archive.org/web/20140907122001/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=22 E-300]}}
| August 22, 2011
| rowspan=3 | 2 (2)
| 1.3
| rowspan=3 | 2×
512KB
| 488
| 78
| EME300GBB22GV
|-
! {{rh}} | {{visible anchor|E-350|text=[https://web.archive.org/web/20110424032501/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=1 E-350]}}
| January 4, 2011
| 1.6
| 492
| 78.7
| EME350GBB22GT
|-
! {{rh}} | {{visible anchor|E-450|text=[https://web.archive.org/web/20120207142240/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=21 E-450]}}
|August 22, 2011
| B0<br />C0
| 1.65
| HD 6320
| 508
| 600
| 81.2
| 1333
| EME450GBB22GV
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

=== Brazos 2.0: "Ontario", "Zacate" (2012) ===
* [[Engineering:Semiconductor device fabrication|Fabrication]] 40&nbsp;nm by [[Company:TSMC|TSMC]]
* Socket FT1 (BGA-413)
* Based on the Bobcat microarchitecture<ref name="AMD Brazos Platform Preview" />
* L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], AMD64, AMD-V
* PowerNow!
* DirectX 11 integrated graphics
* C-series denote ''Ontario''; and the E-series denotes ''Zacate''
* 2.50 GT/s UMI (PCIe 1.0 ×4)

{| class="wikitable sortable" style="text-align: center"
|-
! rowspan=3 | Model 
! rowspan=3 | Released
! rowspan=3 | Fab
! rowspan=3 | Step.
! colspan=6 | CPU
! colspan=5 | GPU
! rowspan=3 | DDR3
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]
! rowspan=2 | Clock
(GHz)
! rowspan=2 | Turbo
(GHz)
! colspan=3 | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }} 
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | Turbo
(MHz)
! rowspan=2 | GFLOPS{{efn|name="SFLOPS"}}
|-
! L1
! L2
! L3
|-
! {{rh}} | {{visible anchor|C-70|text=[https://web.archive.org/web/20140907122248/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=61 C-70]}}
| September 15, 2012
| rowspan=6 | 40&nbsp;nm
| C0
| rowspan=6 | 2 (2)
| 1.0
| 1.33
| rowspan=6 | 32 KB inst.<br />32 KB data<br /><br />per core
| rowspan=6 | 2× 512KB
| rowspan=6 {{n/a}}
| HD 7290
| rowspan=6 | 80:8:4
| 276
| 400
| 44.1
| 1066
| 9
| CMC70AFPB22GV
|-
! colspan="2" | 
! || colspan="2" | || || || colspan="6" |
|-
! {{rh}} | {{visible anchor|E1-1200|text=[https://web.archive.org/web/20140907121909/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=40 E1-1200]}}
|June 6, 2012
| rowspan=4 | C0
| 1.4
| rowspan=4 {{n/a}}
| rowspan=2 | HD 7310
| 500
| rowspan=2 {{n/a}}
| 80
| rowspan=2 | 1066
| rowspan=4 | 18
| EM1200GBB22GV
|-
! {{rh}} | E1-1500
|January 7, 2013
| 1.48
| 529
| 84.6
|
|-
! {{rh}} | {{visible anchor|E2-1800|text=[https://web.archive.org/web/20131029023350/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=39 E2-1800]}}
| June 6, 2012
| 1.7
| rowspan=2 | HD 7340
| 523
| 680
| 83.6
| rowspan=2 | 1333 
| EM1800GBB22GV
|-
! {{rh}} | E2-2000
| January 7, 2013
| 1.75
| 538
| 700
| 86
|
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

=== Brazos-T: "Hondo" (2012) ===
* [[Engineering:Semiconductor device fabrication|Fabrication]] 40&nbsp;nm by [[Company:TSMC|TSMC]]
* Socket FT1 (BGA-413)
* Based on the Bobcat microarchitecture<ref name="AMD Brazos Platform Preview" />
* L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* Found in tablet computers
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], AMD64, AMD-V
* PowerNow!
* DirectX 11 integrated graphics
* 2.50 GT/s UMI (PCIe 1.0 ×4)

{| class="wikitable" style="text-align: center"
|-
! rowspan=3 | Model
! rowspan=3 | Released
! rowspan=3 | Fab
! rowspan=3 | Step.
! colspan=4 | CPU
! colspan=4 | GPU
! rowspan=3 | DDR3<br />Memory<br />support
! rowspan=3 | TDP (W)
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]
! rowspan=2 | Clock (GHz)
! colspan=2 | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as "kilobyte" and as equal to 1024 B (i.e., 1 [[Kibibyte|KiB]]), and MB, which it defines as "megabyte" and as equal to 1024 KB (1 MiB).<ref name="AMD_54945"/>}}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock (MHz)
! rowspan=2 | GFLOPS{{efn|name="SFLOPS"}}
|-
! L1
! L2
|-
! {{rh}} | {{visible anchor|Z-60|text=[https://web.archive.org/web/20140907100151/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=56 Z-60]}}
| October 9, 2012 
| 40&nbsp;nm
| C0
| 2 (2)
| 1.0
| 32KB inst.<br />32KB data<br /><br />per core
| 2× 512 KB
| HD 6250
| 80:8:4
| 276
| 44.1
| 1066
| 4.5
| XMZ60AFVB22GV
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

=== "Kabini", "Temash" (2013) ===
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm by [[Company:TSMC|TSMC]]
* Socket FT3 (BGA)
* 2 to 4 CPU Cores ([[Engineering:Jaguar (microarchitecture)|Jaguar (microarchitecture)]])
* L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, SSE4.1, SSE4.2, [[Advanced Vector Extensions|AVX]], [[F16C]], CLMUL, [[AES instruction set|AES]], MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], AMD-V support
* Turbo Dock Technology, C6 and CC6 low power states
* GPU based on [[Graphics Core Next]] (GCN)
* AMD Eyefinity multi-monitor for up to two displays

==== Temash, Elite Mobility APU ====
{| class="wikitable sortable" style="text-align: center"
|-
! rowspan=3 | Model
! rowspan=3 | Released 
! rowspan=3 | Fab
! rowspan=3 | Step.
! colspan="5" | CPU
! colspan=4 | GPU
! rowspan=3 | DDR3L
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]
! rowspan=2 | Clock
(GHz)
! rowspan=2 | Turbo
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | Turbo
(MHz)
|-
! L1
! L2
(MB)
|-
! {{rh}} | {{visible anchor|A4-1200|text=[https://web.archive.org/web/20140907095801/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=87 A4-1200]}}
| rowspan=4 | May 23, 2013
| rowspan=4 | 28&nbsp;nm
| rowspan=4 | KB-A1
| rowspan=2 | 2 (2)
| rowspan=4 | 1.0
| rowspan=3 {{n/a}}
| rowspan=4 | 32 KB inst.<br />32 KB data<br /><br />per core
| rowspan=2 | 1
| HD 8180
| rowspan=4 | 128:8:4<br />2 CU
| 225
| rowspan=3 {{n/a}}
| 1066
| 4
| AT1200IFJ23HM
|-
! {{rh}} | {{visible anchor|A4-1250|text=[https://web.archive.org/web/20140907122328/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=86 A4-1250]}}
| rowspan=2 | HD 8210
| rowspan=3 | 300
| 1333
| rowspan=3 | 8
| AT1250IDJ23HM
|-
! {{rh}} | {{visible anchor|A4-1350|text=[https://web.archive.org/web/20150620124214/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=96 A4-1350]}}
| rowspan=2 | 4 (4)
| rowspan=2 | 2
| rowspan=2 | 1066
| AT1350IDJ44HM
|-
! {{rh}} | {{visible anchor|A6-1450|text=[https://web.archive.org/web/20140907100154/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=85 A6-1450]}}
| 1.4
| HD 8250
| 400
| AT1450IDJ44HM
|}
{{notelist}}

==== Kabini, Mainstream APU ====
{| class="wikitable sortable" style="text-align: center"
|-
! rowspan=3 | Model 
! rowspan=3 | Released
! rowspan=3 | Fab
! rowspan=3 | Step.
! colspan=5 | CPU
! colspan=3 | GPU
! rowspan=3 | DDR3L
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]
! rowspan=2 | Clock
(GHz)
! colspan=3 | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
|-
! L1
! L2
(MB)
! L3
|-
! {{rh}} | {{visible anchor|E1-2100|text=[http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E1-Series-APU-for-Laptops/E1-2100-with-Radeon%E2%84%A2-HD-8210/91 E1-2100]}}
| May 2013
| rowspan=9 | 28&nbsp;nm
| rowspan=9 | KB-A1
| rowspan=4 | 2 (2)
| 1.0
| rowspan=9 | 32KB inst.<br />32KB data<br /><br />per core
| rowspan=4 | 1
| rowspan=9 {{n/a}}
| rowspan=2 | HD 8210
| rowspan=9 | 128:8:4<br />2 CU
| rowspan=2 | 300
| rowspan=3 | 1333
| rowspan=2 | 9
| EM2100ICJ23HM
|-
! {{rh}} | {{visible anchor|E1-2200|text=[http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E1-Series-APU-for-Laptops/E1-2200-with-Radeon%E2%84%A2-HD-8210/92 E1-2200]}}
| Feb 2014
| 1.05
| EM2200ICJ23HM
|-
! {{rh}} | {{visible anchor|E1-2500|text=[http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E1-Series-APU-for-Laptops/E1-2500-with-Radeon%E2%84%A2-HD-8240/93 E1-2500]}}
| rowspan=2 |May 2013
| 1.4
| HD 8240
| 400
| rowspan=5 | 15
| EM2500IBJ23HM
|-
! {{rh}} | {{visible anchor|E2-3000|text=[http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E2-Series-APU-for-Laptops/E2-3000-with-Radeon%E2%84%A2-HD-8280/100 E2-3000]}}
| 1.65
| rowspan=2 | HD 8280 
| rowspan=2 | 450
| rowspan=6 | 1600
| EM3000IBJ23HM
|-
! {{rh}} | {{visible anchor|E2-3800|text=[http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E2-Series-APU-for-Laptops/E2-3800-with-Radeon%E2%84%A2-HD-8280/96 E2-3800]}}
| Feb 2014
| rowspan=5 | 4
| 1.3
| rowspan=5 | 2
| EM3800IBJ44HM
|-
! {{rh}} | {{visible anchor|A4-5000|text=[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Laptops/A4-5000-with-Radeon%E2%84%A2-HD-8330/40 A4-5000]}}
| May 2013
| 1.5
| rowspan=2 | HD 8330
| rowspan=2 | 497
| AM5000IBJ44HM
|-
! {{rh}} | {{visible anchor|A4-5100|text=[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Laptops/A4-5100-with-Radeon%E2%84%A2-HD-8330/33 A4-5100]}}
| Feb 2014
| 1.55
| AM5100IBJ44HM
|-
! {{rh}} | {{visible anchor|A6-5200|text=[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Desktops/A6-5200-with-Radeon%E2%84%A2-HD-8400/41 A6-5200]}}
| May 2013
| 2.0
| HD 8400
| 600
| rowspan=2 | 25
| AM5200IAJ44HM
|-
! {{rh}} | {{visible anchor|A4 Pro-3340B|text=[http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A4-APU-for-Laptops/A4-PRO-3340B-with-Radeon%E2%84%A2-HD-8240-Graphics/154 A4 Pro-3340B]}}
| Nov 2014
| 2.2
| HD 8240
| 400
| AM334BIAJ44HM
|}
{{notelist}}

=== "Beema", "Mullins" (2014) ===
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* Socket FT3b (BGA)
* CPU: 2 to 4 ([[Engineering:Puma (microarchitecture)|Puma cores]])
** L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* GPU based on [[Graphics Core Next]] (GCN)
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, SSE4.1, SSE4.2, [[Advanced Vector Extensions|AVX]], [[F16C]], CLMUL, [[AES instruction set|AES]], MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], AMD-V support
* Intelligent Turbo Boost
* Platform Security Processor, with an integrated ARM Cortex-A5 for TrustZone execution

==== Mullins, Tablet/2-in-1 APU ====
{| class="wikitable sortable" style="text-align: center"
|-
! rowspan=3 | Model
! rowspan=3 | Released 
! rowspan=3 | Fab
! rowspan=3 | Step.
! colspan=6 | CPU
! colspan=4 | GPU
! rowspan=3 | DDR3L
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]
! rowspan=2 | Clock
(GHz)
! rowspan=2 | Turbo
(GHz)
! colspan=3 | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/>}}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | Turbo
(MHz)
|-
! L1
! L2
(MB)
! L3
|-
! {{rh}} | {{visible anchor|E1 Micro-6200T|text=[https://web.archive.org/web/20150623145036/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=111 E1 Micro-6200T]}}
| rowspan=3 | Q2 2014 
| rowspan=3 | 28&nbsp;nm
| rowspan=3 | ML-A1
| 2 (2)
| rowspan=2 | 1.0
| 1.4
| rowspan=3 | 32 KB inst.<br />32 KB data<br /><br />per core
| 1
| rowspan=3 {{n/a}}
| R2
| rowspan=3 | 128:8:4<br />2 CU
| 300
| 600
| 1066
| 3.95
| EM620TIWJ23JB
|-
! {{rh}} | {{visible anchor|A4 Micro-6400T|text=[https://web.archive.org/web/20150623142121/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=110 A4 Micro-6400T]}}
| rowspan=2 | 4 (4)
| 1.6
| rowspan=2 | 2
| R3
| 350
| 686
| rowspan=2 | 1333
| rowspan=2 | 4.5
| AM640TIVJ44JB
|-
! {{rh}} | {{visible anchor|A10 Micro-6700T|text=[https://web.archive.org/web/20150623162603/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=109 A10 Micro-6700T]}}
| 1.2
| 2.2
| R6
| 500
| {{n/a}}
| AM670TIVJ44JB
|}
{{notelist}}

==== Beema, Notebook APU ====
{| class="wikitable sortable" style="text-align: center"
|-
! rowspan=3 | Model 
! rowspan=3 | Released
! rowspan=3 | Fab
! rowspan=3 | Step.
! colspan=6 | CPU
! colspan=4 | GPU
! rowspan=3 | DDR3 Memory support
! rowspan=3 | TDP (W)
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]] [[Thread (computing)|(threads)]] [[Floating-point unit|[FPUs]]]
! rowspan=2 | Clock (GHz)
! rowspan=2 | Turbo (GHz)
! colspan=3 | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock (MHz)
! rowspan=2 | Turbo (MHz)
|-
! L1
! L2 (MB)
! L3
|-
! {{rh}} | {{visible anchor|E1-6010|text=[http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E1-Series-APU-for-Laptops/E1-6010-with-Radeon%E2%84%A2-R2-Graphics/94 E1-6010]}}
| Q2 2014
| rowspan="7" | 28&nbsp;nm
| rowspan="7" | ML-A1
| rowspan=2 | 2 (2)
| 1.35
| rowspan=5 {{n/a}}
| rowspan="7" | 32 KB inst. 32 KB data per core
| rowspan=2 | 1
| rowspan=7 {{n/a}}
| rowspan=3 | R2
| rowspan="7" | 128:8:4<br />2 CU
| rowspan=3 | 300
| rowspan=3 | 600
| rowspan=2 | (L)1333
| rowspan=2 | 10
| EM6010IUJ23JB
|-
! {{rh}} | E1-6015<ref>{{cite web |url=http://h10032.www1.hp.com/ctg/Manual/c04655538 |title=Archived copy |access-date=May 26, 2015 |url-status=dead |archive-url=https://web.archive.org/web/20150527023525/http://h10032.www1.hp.com/ctg/Manual/c04655538 |archive-date=May 27, 2015 }}</ref>
| Q2 2015
| 1.4
| 
|-
! {{rh}} | {{visible anchor|E2-6110|text=[https://web.archive.org/web/20150623144907/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=114 E2-6110]}}
| rowspan=5 | Q2 2014
| rowspan="5" | 4 (4)
| 1.5
| rowspan="5" | 2
| rowspan=3 | (L)1600
| rowspan=2 | 15
| EM6110ITJ44JB
|-
! {{rh}} | {{visible anchor|A4-6210|text=[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Laptops/A4-6210-with-Radeon%E2%84%A2-R3-Graphics/36 A4-6210]}}
| 1.8
| rowspan=2 | R3
| rowspan=2 | 350
| rowspan=2 | 686
| AM6210ITJ44JB
|-
! {{rh}} | A4-6250J<ref>{{cite web |url=https://store.hp.com/GermanyStore/Merch/Product.aspx?id=J4B15EA&opt=ABD&sel=PBDT |title=HP ProDesk 405 G2 Microtower-PC |access-date=February 24, 2015}}</ref>
| 2.0
| 25
|-
! {{rh}} | {{visible anchor|A6-6310|text=[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Laptops/A6-6310-with-Radeon%E2%84%A2-R4-Graphics/53 A6-6310]}}
| 1.8
| rowspan="2" | 2.4
| R4
| rowspan="2" | 300
| rowspan="2" | 800
| rowspan=2 | (L)1866
| rowspan="2" | 15
| AM6310ITJ44JB
|-
! {{rh}} | {{visible anchor|A8-6410|text=[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Laptops/A8-6410-with-Radeon%E2%84%A2-R5-Graphics/131 A8-6410]}}
| 2.0
| R5
| AM6410ITJ44JB
|}
{{notelist}}

=== "Carrizo-L" (2015) ===
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* Socket FT3b (BGA), FP4 (µBGA)<ref>{{cite web|url=http://www.anandtech.com/show/9246/amds-carrizo-l-apus-unveiled-12-25w-quad-core-puma|title=AMD's Carrizo-L APUs Unveiled: 12-25W Quad Core Puma+|first=Ian|last=Cutress|website=Anandtech.com|access-date=July 20, 2018}}</ref>
* CPU: 2 to 4 ([[Engineering:Puma (microarchitecture)#Puma+|Puma+ cores]])
** L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* GPU based on [[Graphics Core Next]] (GCN)
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, SSE4.1, SSE4.2, [[Advanced Vector Extensions|AVX]], [[F16C]], CLMUL, [[AES instruction set|AES]], MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], AMD-V support
* Intelligent Turbo Boost
* Platform Security Processor, with an integrated ARM Cortex-A5 for TrustZone execution
* All models except A8-7410 available in both laptop and all-in-one desktop versions

{| class="wikitable sortable" style="text-align: center"
|-
! rowspan=3 | Model
! rowspan=3 | Released
! rowspan=3 | Fab
! rowspan=3 | Step.
! colspan="5" | CPU
! colspan=4 | GPU
! rowspan=3 | DDR3<br />Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]<br />[[Floating-point unit|[FPUs]]]
! rowspan=2 | Clock
(GHz)
! rowspan=2 | Turbo
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
! rowspan=2 | Turbo
(MHz)
|-
! L1
! L2
(MB)
|-
! {{rh}} | {{visible anchor|E1-7010|text=[http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E1-Series-APU-for-Laptops/E1-7010-with-Radeon%E2%84%A2-R2-Graphics/140 E1-7010]}}
| rowspan=5 | May 2015 
| rowspan=6 | 28&nbsp;nm
| rowspan=6 | ML-A1
| 2
| 1.5
| rowspan=2 {{n/a}}
| rowspan=6 | 32 KB inst.<br />32 KB data<br /><br />per core
| 1
| R2
| rowspan=6 | 128:8:4<br />2 CU
|
| 400
| (L)1333
| 10
| EM7010IUJ23JB<br /> EM7010JCY23JB<br /> EM7010JCY23JBD
|-
! {{rh}} | {{visible anchor|E2-7110|text=[http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E2-Series-APU-for-Laptops/E2-7110-with-Radeon%E2%84%A2-R2-Graphics/139 E2-7110]}}
| rowspan=5 | 4
| rowspan=2 | 1.8
| rowspan=5 | 2
| R2
|
| 600
| rowspan=2 | (L)1600
| rowspan=3 | 12–25
| EM7110ITJ44JB<br /> EM7110JBY44JB<br /> EM7110JBY44JBD
|-
! {{rh}} | {{visible anchor|A4-7210|text=[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Laptops/A4-7210-with-Radeon%E2%84%A2-R3-Graphics/133 A4-7210]}}
| 2.2
| R3
|
| 686
| AM7210ITJ44JB<br /> AM7210JBY44JBD
|-
! {{rh}} | {{visible anchor|A6-7310|text=[http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Laptops/A6-7310-with-Radeon%E2%84%A2-R4-Graphics/137 A6-7310]}}
| 2.0
| 2.4
| R4
|
| 800
| rowspan=2 | (L)1866
| AM7310ITJ44JB<br /> AM7310JBY44JB<br /> AM7310JBY44JBD
|-
! {{rh}} | {{visible anchor|A8-7410|text=[https://www.amd.com/en/product/5956 A8-7410]}}
| 2.2
| 2.5
| R5
|
| 847
| rowspan=2 | 15
| AM7410JBY44JB
|-
! {{rh}} | {{visible anchor|A4 PRO-3350B|text=[https://www.amd.com/en/product/6111 A4 PRO-3350B]}}
| May 2016
| 2.0
| 2.4
| R4
|
| 800
| 1600
| AM335BITJ44JB
|}
{{notelist}}

=== "Stoney Ridge" (2016) ===
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* Socket FP4<ref name="AMDGen7" /> / FT4
* 2 "[[Engineering:Excavator (microarchitecture)|Excavator+]]" x86 CPU cores
* L1 Cache: 32 KB Data per core and 96 KB Instructions per module
* Single-channel DDR4 memory controller
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], [[RDRAND]], Turbo Core
* GPU based on [[Graphics Core Next]] 3rd Generation with [[VP9]] decoding

{| class="wikitable sortable" style="text-align:center;"
! style="text-align:left;" rowspan="3" | Model number
! rowspan=3 | Released
! rowspan=3 | Fab
! colspan="5" | CPU
! colspan=4 | GPU
! rowspan=3 | DDR4
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [Modules/[[Floating-point unit|FPUs]]]
[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! rowspan=2 | Clock
(GHz)
! rowspan=2 | Turbo
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | GFLOPS{{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
|-
! style="text-align:left;" | E2-9000e
|November 2016
| rowspan=22 | 28&nbsp;nm
| rowspan=22 | [1]2
| 1.5
| 2.0
| rowspan=22 | 96 KB inst.<br />per module<br /><br />32 KB data<br />per core
| rowspan=22 | 1
| rowspan=3 | R2
| rowspan=5 | 128:8:4<br />2 CU
| rowspan=3 | 600
| rowspan=3 | 153.6
| rowspan=3 | 1866
| 6
| EM900EANN23AC
|-
! style="text-align:left;" | E2-9000
| rowspan=2 | June 2016
| 1.8
| 2.2
| 10
| EM9000AKN23AC
|-
! style="text-align:left;" | [http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E2-Series-APU-for-Laptops/7th-Gen-E2-9010-APU/200 E2-9010]
| 2.0
| 2.2
| 10–15
| EM9010AVY23AC
|-
! style="text-align:left;" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Laptops/7th-Gen-A4-9120-APU/235 A4-9120]
| Q2 2017
| 2.2
| 2.5
| rowspan=2 | R3
| 655
| 167.6
| rowspan=2 | 2133
| rowspan=2 | 10–15
| AM9120AYN23AC
|-
! style="text-align:left;" | [https://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Laptops/7th-Gen-A4-9125-APU/268 A4-9125]
| Q2 2018
| 2.3
| 2.6
| 686
| 175.6
| AM9125AYN23AC
|-
! style="text-align:left | [https://www.amd.com/en/products/apu/7th-gen-a4-9120c-apu A4-9120C]
| January 6, 2019
| 1.6
| 2.4
| rowspan=6 | R4
| rowspan=17 | 192:12:8<br />3 CU
| rowspan=4 | 600
| rowspan=4 | 230.4
| 1866
| rowspan=2 | 6
| AM912CANN23AC
|-
! style="text-align:left;" | A6-9200e
| rowspan=2 | November 2016
| 1.8
| 2.7
| rowspan=5 | 2133
| AM920EANN23AC
|-
! style="text-align:left;" | A6-9200
| 2.0
| 2.8
| 10
| AM9200AKN23AC
|-
! style="text-align:left;" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Laptops/7th-Gen-A6-9210-APU/199 A6-9210]
| June 2016
| 2.4
| 2.8
| 10–15
| AM9210AVY23AC
|-
! style="text-align:left;" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Laptops/7th-Gen-A6-9220-APU/234 A6-9220]
| Q2 2017
| 2.5
| 2.9
| 655
| 251.5
| rowspan=2 | 10–15
| AM9220AYN23AC
|-
! style="text-align:left;" | [https://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Laptops/7th-Gen-A6-9225-APU/267 A6-9225]
| Q2 2018
| 2.6
| 3.0
| 686
| 263.4
| AM9225AYN23AC
|-
! style="text-align:left | [https://www.amd.com/en/products/apu/7th-gen-a6-9220c-apu A6-9220C]
| January 6, 2019
| 1.8
| 2.7
| rowspan=11 | R5
| 720
| 276.4
| 1866
| 6
| AM922CANN23AC
|-
! style="text-align:left;" | A9-9400
| November 2016
| 2.4
| 3.2
| rowspan=2 | 800
| rowspan=2 | 307.2
| rowspan=4 | 2133
| 10
| AM9400AKN23AC
|-
! style="text-align:left;" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A9-Series-APU-for-Laptops/7th-Gen-A9-9410-APU/198 A9-9410]
|June 2016
| 2.9
| 3.5
| rowspan=3 | 10–25
| AM9410AFY23AC
|-
! style="text-align:left;" | [http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A9-Series-APU-for-Laptops/7th-Gen-A9-9420-APU/233 A9-9420]
| Q2 2017
| 3.0
| 3.6
| 847
| 325.2
| AM9420AYN23AC
|-
! style="text-align:left;" | [https://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A9-Series-APU-for-Laptops/7th-Gen-A9-9425-APU/266 A9-9425]
| Q2 2018
| 3.1
| 3.7
| 900
| 345.6
| AM9425AYN23AC
|-
! style="text-align:left;" | A9-9430<ref>{{cite web|url=http://store.hp.com/us/en/pdp/hp-pavilion-desktop-570-a135m|title=HP Pavilion Desktops - HP® Official Store|website=Store.hp.com|access-date=July 20, 2018}}</ref>
| Q2 2017
| 3.2
| 3.5
| 847
| 325.2
| 2400
| 25
| AD9430AJN23AC
|-
! colspan="2" |  || colspan="2" | || || colspan="4" | 
|-
! style="text-align:left;" | [https://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A4-APU-for-Laptops/7th-Gen-AMD-PRO-A4-4350B-APU/248 Pro A4-4350B]
| Q1 2018
| 2.5
| 2.9
| 655
| 251.5
| rowspan=4 | 2133
| rowspan=4 | 15
| 
|-
! style="text-align:left;" | [https://www.amd.com/en/products/apu/7th-gen-amd-pro-a4-5350b-apu Pro A4-5350B]
| Q1 2020
| rowspan=2 |3.0
| rowspan=2 |3.6
| rowspan=2 |847
| rowspan=2 |325.2
| 
|-
! style="text-align:left;" | [https://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A6-APU-for-Laptops/7th-Gen-AMD-PRO-A6-7350B-APU/249 Pro A6-7350B]
| Q1 2018
|
|-
! style="text-align:left;" | [https://www.amd.com/en/products/apu/7th-gen-amd-pro-a6-8350b-apu Pro A6-8350B]
| Q1 2020
| 3.1
| 3.7
| 900
| 345.6
|
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

=== "Dalí" (2020) ===

* [[Engineering:Semiconductor device fabrication|Fabrication]] 14&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* Socket FP5
* Two Zen CPU cores
* Over 30% die size reduction over predecessor (Raven Ridge)
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[FMA instruction set#FMA3 instruction set|FMA3]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[RDRAND]], Turbo Core
*Dual-channel RAM
=== "Pollock" (2020) ===

* [[Engineering:Semiconductor device fabrication|Fabrication]] 14&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* Socket FT5
* Two Zen CPU cores
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[FMA instruction set#FMA3 instruction set|FMA3]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[RDRAND]], Turbo Core
*Single-channel RAM

=== "Mendocino" (2022) ===
{{Main|Engineering:Ryzen}}

== Embedded APUs ==
{{further|Embedded system}}

=== G-Series ===

==== Brazos: "Ontario" and "Zacate" (2011) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 40&nbsp;nm
* [[Engineering:Socket FT1|Socket FT1]] (BGA-413)
* CPU microarchitecture: Bobcat<ref>{{cite web|url=https://www.amd.com/us/press-releases/Pages/apu-embedded-systems-2011jan19.aspx|title=Welcome to AMD - Processors - Graphics and Technology - AMD|website=Amd.com|access-date=July 20, 2018}}</ref>
* L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], AMD64, AMD-V
* GPU microarchitecture: TeraScale 2 (VLIW5) "Evergreen"
* Memory support: single-channel, support up to two DIMMs of DDR3-1333 or DDR3L-1066 
* 5&nbsp;GT/s UMI

{| class="wikitable sortable" style="text-align: center"
|-
! rowspan=3 | Model 
! rowspan=3 | Released
! rowspan=3 | Fab
! rowspan=3 | Step.
! colspan="4" | CPU
! colspan=4 | GPU
! rowspan=3 | DDR3
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]
! rowspan=2 | Clock
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | Processing<br />power<br />(GFLOPS){{efn|name="SFLOPS"}}
|-
! L1
! L2
|-
! {{rh}} | G-Series T24L
| March 1, 2011<br />May 23, 2011
| rowspan=15 | 40&nbsp;nm
| rowspan=3 | B0
| rowspan="2" | 1 (1)
| 0.8<br />1.0
| rowspan=15 | 32 KB inst.<br />32 KB data<br /><br />per core
| rowspan=2 | 512 KB
| rowspan=3 colspan=4 {{n/a}}
| rowspan=3 | 1066
| 5
| GET24LFPB12GTE<br />GET24LFQB12GVE
|-
! {{rh}} | G-Series T30L
|March 1, 2011<br />May 23, 2011
| rowspan=2 | 1.4
| rowspan=2 | 18
| GET30LGBB12GTE<br />GET30LGBB12GVE
|-
! {{rh}} | G-Series T48L
| March 1, 2011<br />May 23, 2011
| 2 (2)
| 2 × 512 KB
| GET48LGBB22GTE<br />GET48LGBB22GVE
|-
! colspan="2" | 
! colspan="3" | ||  || colspan="7" |
|-
! {{rh}} | G-Series T16R
| June 25, 2012
| rowspan=11 | B0
| rowspan=2 | 1 (1)
| 0.615
| rowspan=2 | 512 KB
| rowspan=3 | HD 6250
| rowspan=11 | 80:8:4
| 276
| 44.1
| (L)1066
| 4.5
| GET16RFWB12GVE
|-
! {{rh}} | G-Series T40R
| rowspan=2 |May 23, 2011
| rowspan=4 | 1.0
| rowspan=6 | 280
| rowspan=6 | 44.8
| rowspan=7 | 1066
| 5.5
| GET40RFQB12GVE
|-
! {{rh}} | G-Series T40E
| rowspan=2 | 2 (2)
| rowspan=2 | 2 × 512 KB
| 6.4
| GET40EFQB22GVE
|-
! {{rh}} | G-Series T40N
|January 19, 2011<br />May 23, 2011
| HD 6250<br />HD 6290
| 9
| GET40NFPB22GTE<br />GET40NFPB22GVE
|-
! {{rh}} | G-Series T40R
| May 23, 2011
| rowspan=2 | 1 (1)
| rowspan=2 | 512 KB
| rowspan=3 | HD 6250
| 5.5
| GET40RFSB12GVE
|-
! {{rh}} | G-Series T44R
| January 19, 2011<br />May 23, 2011
| 1.2
| 9
| GET44RFPB12GTE<br />GET44RFPB12GVE
|-
! {{rh}} | G-Series T48E
|June 25, 2012
| rowspan=2 | 2 (2)
| rowspan=2 | 1.4
| rowspan=2 | 2 × 512 KB
| rowspan=5 | 18
| GET48EGBB22GVE
|-
! {{rh}} | G-Series T48N
| January 19, 2011<br /> May 23, 2011
| rowspan=2 | HD 6310
| 500<br />520
| 80<br /> 83.2
| GET48NGBB22GTE<br />GET48NGBB22GVE
|-
! {{rh}} | G-Series T52R
|January 19, 2011<br /> May 23, 2011
| 1 (1)
| 1.5
| 512 KB
| 500
| 80
| 1066<br /> 1333
| GET52RGBB12GTE<br />GET52RGBB12GVE
|-
! {{rh}} | G-Series T56E
| June 25, 2012
| rowspan=2 | 2 (2)
| 1.65
| rowspan=2 | 2 × 512 KB
| HD 6250
| 275
| 44
| 1333
| GET56EGBB22GVE
|-
! {{rh}} | G-Series T56N
|January 19, 2011<br /> May 23, 2011
| 1.6<br /> 1.65
| HD 6310<br />HD 6320
| 500
| 80
| 1066<br />1333
| GET56NGBB22GTE<br />GET56NGBB22GVE
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== "Kabini" (2013, [[System on a chip|SoC]]) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm
* Socket FT3 (769-BGA)<ref>{{cite web|url=https://www.amd.com/en-us/products/embedded/processors/g-series#|title=Embedded Products - High Performance GPU - AMD|website=Amd.com|access-date=July 20, 2018}}</ref>
* CPU microarchitecture: [[Engineering:Jaguar (microarchitecture)|Jaguar]]
* L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, SSE4.1, SSE4.2, [[Advanced Vector Extensions|AVX]], [[F16C]], CLMUL, [[AES instruction set|AES]], MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], AMD-V support. No support for [[FMA instruction set|FMA (Fused Multiply-Accumulate)]]. [[Software:Trusted Platform Module|Trusted Platform Module]] (TPM) 1.2 support
* GPU microarchitecture: [[Graphics Core Next]] (GCN) with Unified Video Decoder 3 (H.264, VC-1, MPEG2, etc.)
* Single channel DDR3-1600, 1.25 and 1.35 V voltage level support, support for [[ECC memory]]
* Integrates Controller Hub functional block, HD audio, 2 SATA channels, USB 2.0 and USB 3.0 (except GX-210JA)

{| class="wikitable sortable" style="text-align: center"
! {{rh}} rowspan=3 | Model
! rowspan=3 | Released 
! rowspan=3 | Fab
! rowspan=3 | Step.
! colspan="4" | CPU
! colspan=4 | GPU
! rowspan=3 | DDR3
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | [[Physics:Junction temperature|Junction temperature]] (°C)
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]
! rowspan=2 | Clock
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | Processing<br />power<br />(GFLOPS){{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
|-
! {{rh}} | GX-210UA
| {{unk}}
| rowspan=9 |28&nbsp;nm
| rowspan=9 | B0
| rowspan=5 | 2 (2)
| rowspan=4 | 1.0
| rowspan=9 | 32 KB inst.<br />32 KB data<br /><br />per core
| rowspan=5 | 1
| colspan=4 {{n/a}}
| 1333
| 8.5
| rowspan=2 | 0-90
| GE210UIGJ23HM
|-
! {{rh}} | GX-210JA
| July 30, 2013 
| HD 8180E
| rowspan=6 | 128:8:4<br />2 CU
| 225
| 57.6
| rowspan=2 | 1066
| 6
| GE210JIHJ23HM
|-
! {{rh}} | GX-209HA
| {{unk}}
| HD 8400E
| 600
| 153.6
| rowspan=2 | 9
| -40-105
| GE209HISJ23HM
|-
! {{rh}} | GX-210HA
| rowspan=2 | June 1, 2013
| HD 8210E
| 300
| 76.8
| 1333
| rowspan=2 | 0-90
| GE210HICJ23HM
|-
! {{rh}} | GX-217GA
| 1.65
| HD 8280E
| 450
| 115.2
| 1600
| rowspan=4 | 15
| GE217GIBJ23HM
|-
! {{rh}} | GX-411GA
| {{unk}}
| rowspan=4 | 4 (4)
| 1.1
| rowspan=4 | 2
| HD 8210E
| 300
| 76.8
| 1066
| -40-105
| GE411GIRJ44HM
|-
! {{rh}} | GX-415GA
| rowspan=3 | June 1, 2013
| 1.5
| HD 8330E
| 500
| 128
| rowspan=3 | 1600
| rowspan=3 | 0-90 
| GE415GIBJ44HM
|-
! {{rh}} | GX-416RA
| 1.6
| colspan=4 {{n/a}}
| GE416RIBJ44HM
|-
! {{rh}} | GX-420CA
| 2.0
| HD 8400E
| 128:8:4<br />2 CU
| 600
| 153.6
| 25
| GE420CIAJ44HM
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== "Steppe Eagle" (2014, [[System on a chip|SoC]]) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm
* Socket FT3b (769-BGA)
* CPU microarchitecture: [[Engineering:Puma (microarchitecture)|Puma]]
* L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, SSE4.1, SSE4.2, [[Advanced Vector Extensions|AVX]], [[F16C]], CLMUL, [[AES instruction set|AES]], MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], AMD-V support

{| class="wikitable sortable" style="text-align: center"
! {{rh}} rowspan="3" | Model
! rowspan=3 | Released 
! rowspan=3 | Fab
! rowspan=3 | Step.
! colspan="4" | CPU
! colspan="4" | GPU
! rowspan=3 | DDR3
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | [[Physics:Junction temperature|Junction temperature]] (°C)
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]<br />[[Floating-point unit|[FPUs]]]
! rowspan=2 | Clock
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | Processing<br />power<br />(GFLOPS){{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
|-
! {{rh}} | GX-210JC
| rowspan=6 | June 4, 2014 
| rowspan=6 | 28&nbsp;nm
| rowspan=6 | ML-A1
| rowspan=4 | 2 (2) [1]
| 1.0
| rowspan=6 | 32 KB inst.<br />32 KB data<br /><br />per core
| rowspan=4 | 1
| R1E
| rowspan=6 | 128:8:4<br />2 CU
| 267
| 68.3
| 1600
| rowspan=2 | 6
| -40-105
| GE210JIZJ23JB
|-
! {{rh}} | GX-212JC
| 1.2
| R2E
| rowspan=2 | 300
| rowspan=2 | 76.8
| 1333
| 0-90
| GE212JIYJ23JB
|-
! {{rh}} | GX-216HC
| 1.6
| R4E
| 1066
| 10
| -40-105
| GE216HHBJ23JB
|-
! {{rh}} | GX-222GC
| 2.2
| R5E
| 655
| 167.6
| 1600
| 15
| rowspan=3 | 0-90
| GE222GITJ23JB
|-
! {{rh}} | GX-412HC
| rowspan=2 | 4 (4) [2]
| 1.2
| rowspan=2 | 2 
| R3E
| 300
| 76.8
| 1333
| 7
| GE412HIYJ44JB
|-
! {{rh}} | GX-424CC
| 2.4
| R5E
| 497
| 127.2
| 1866
| 25
| GE424CIXJ44JB
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== "Crowned Eagle" (2014, [[System on a chip|SoC]]) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm
* Socket FT3b (769-BGA)
* CPU microarchitecture: [[Engineering:Puma (microarchitecture)|Puma]]
* L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, SSE4.1, SSE4.2, [[Advanced Vector Extensions|AVX]], [[F16C]], CLMUL, [[AES instruction set|AES]], MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], AMD-V support
* no GPU

{| class="wikitable sortable" style="text-align: center" 
|-
!rowspan=3 | Model 
!rowspan=3 | Released 
!rowspan=3 | Fab
! colspan="4" | CPU
! rowspan="3"|GPU
!rowspan=3 | DDR3
Memory<br />support
!rowspan=3 | TDP
(W)
!rowspan=3 | [[Physics:Junction temperature|Junction]]
[[Physics:Junction temperature|temperature]]

(°C)
!rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]<br />[[Floating-point unit|[FPUs]]]
! rowspan=2 | Clock
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
|-
! L1
! L2
(MB)
|-
! {{rh}} | GX-224PC 
| rowspan=4 | June 4, 2014 
| rowspan=4 | 28&nbsp;nm
| 2 (2) [1]
| 2.4
| rowspan=4 | 32 KB inst.<br />32 KB data<br /><br />per core
| 1
| rowspan=4 {{n/a}}
| 1866
| 25
| 0-90
| GE224PIXJ23JB
|-
! {{rh}} | GX-410VC
| rowspan=3 | 4 (4) [2]
| 1.0
| rowspan=3 | 2
| 1066
| 7
| -40-105
| GE410VIZJ44JB
|-
! {{rh}} | GX-412TC
| 1.2
| rowspan=2 | 1600
| 6
| rowspan=2 | 0-90
| GE412TIYJ44JB
|-
! {{rh}} | GX-420MC
| 2.0
| 17.5
| GE420MIXJ44JB
|}
{{notelist}}

==== LX-Family (2016, [[System on a chip|SoC]]) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm
* Socket FT3b (769-BGA)
* 2 [[Engineering:Puma (microarchitecture)|Puma]] x86 cores with 1MB shared L2 cache
* L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, SSE4.1, SSE4.2, [[Advanced Vector Extensions|AVX]], [[F16C]], CLMUL, [[AES instruction set|AES]], MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], AMD-V support
* GPU microarchitecture: [[Graphics Core Next]] (GCN) (1CU) with support for DirectX 11.2
* Single channel 64-bit DDR3 memory with [[ECC memory|ECC]]
* Integrated Controller Hub supports: PCIe® 2.0 4×1, 2 USB3 + 4 USB2 ports, 2 SATA 2.0/3.0 ports
{| class="wikitable sortable" style="text-align: center"
! {{rh}} rowspan="3" | Model
! rowspan=3 | Released 
! rowspan=3 |Fab
! rowspan=3 | Step.
! colspan="4" | CPU
! colspan=4 | GPU
! rowspan=3 | DDR3
Memory<br />support
! rowspan=3 | TDP
(W)
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]]<br />[[Thread (computing)|(threads)]]<br />[[Floating-point unit|[FPUs]]]
! rowspan=2 | Clock
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | Processing<br />power<br />(GFLOPS){{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
|-
! {{rh}} | GX-208JL
| February 23, 2016 
| rowspan=6 | 28&nbsp;nm
| rowspan=6 | ML-A1
| rowspan=6 | 2
| 0.8
| rowspan=6 | 32 KB inst.<br />32 KB data<br /><br />per core
| rowspan=6 | 1
| rowspan=6 | R1E
| rowspan=6 | 64:4:1<br />1 CU
| rowspan=4 | 267
| rowspan=4 | 34.1
| 1333
| 6
| GE208JIVJ23JB
|-
| {{rh}} | GX-210HL
| 2017
| rowspan=3 | 1.0
| 1066
| 7
| GE208HIZJ23JB
|-
! {{rh}} | GX-210JL
| February 23, 2016
| rowspan=2 | 1333
| 6
| GE210JIVJ23JB
|-
| {{rh}} | GX-210KL
| 2017
| 4.5
| GE210KIVJ23JB
|-
! {{rh}} | GX-215GL
| rowspan=2 | February 23, 2016
| 1.5
| rowspan=2 | 497
| rowspan=2 | 63.6
| rowspan=2 | 1600
| rowspan=2 | 15
| GE215GITJ23JB
|-
! {{rh}} | GX-218GL
|  1.8
| GE218GITJ23JB
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== I-Family: "Brown Falcon" (2016, [[System on a chip|SoC]]) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm
* Socket FP4<ref>https://www.amd.com/Documents/I-Family-Product-Brief.pdf {{Bare URL PDF|date=March 2022}}</ref>
* 2 or 4 [[Engineering:Excavator (microarchitecture)|Excavator]] x86 cores with 1MB shared L2 cache
* L1 Cache: 32 KB Data per core and 96 KB Instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], [[RDRAND]]
* GPU microarchitecture: [[Graphics Core Next]] (GCN) (up to 4 CUs) with support for DirectX 12
* Dual channel 64-bit DDR4 or DDR3 memory with [[ECC memory|ECC]]
* 4K × 2K H.265 decode capability and multi format encode and decode
* Integrated Controller Hub supports: PCIe 3.0 1×4, PCIe 2/3 4×1, 2 USB3 + 2 USB2 ports, 2 SATA 2.0/3.0 ports
{| class="wikitable sortable" style="text-align: center"
! {{rh}} rowspan="3" | Model !! rowspan="3" | Released 
! rowspan="3" |Fab!! colspan="5" | CPU !! colspan="4" | GPU !! rowspan="3" | Memory<br />support !! rowspan="3" | TDP
(W)
! rowspan="3" | Part number
|-
! rowspan="2" | [Modules/[[Floating-point unit|FPUs]]]<br />[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]] !! rowspan="2" | Clock
(GHz)
! rowspan="2" | Turbo
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan="2" | Model !! rowspan="2" | Config{{NoteTag|name=fn_2}} !! rowspan="2" | Clock
(MHz)
! rowspan="2" | Processing<br />power<br />(GFLOPS){{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
|-
! {{rh}} | GX-217GI
| February 23, 2016 
| rowspan="2" |28&nbsp;nm|| [1] 2 || 1.7 || 2.0 || rowspan="2" | 96&nbsp;KB inst.<br />per module<br /><br />32&nbsp;KB data<br />per core || 1 || R6E || 256:16:4<br />4 CU || 758 || 388 || DDR3/DDR4-1600 || 15 || GE217GAAY23KA
|-
! {{rh}} | GX-420GI<ref>https://store.hp.com/us/en/pdp/hp-t630-thin-client-p-2zv00at-aba-1?pStoreID=epp </ref><ref>{{cite web|url=http://www.cpu-world.com/CPUs/Bulldozer/AMD-G-Series%20GX-420GI.html |title=AMD G-Series GX-420GI - GE420GAAY43KA |publisher=Cpu-world.com |date=July 6, 2022 |accessdate=August 22, 2022}}</ref>
| 2016 || [2] 4 || 2.0 || 2.2 || 2 || R6E<br /><br /><br />R7E || 256:16:4<br />4 CU<br /><br />384:24:4<br />6 CU || 758<br /><br /><br />626 || 388<br /><br /><br />480.7 || DDR4-1866 || 16.1 || GE420GAAY43KA
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== J-Family: "Prairie Falcon" (2016, [[System on a chip|SoC]]) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm
* Socket FP4<ref>https://www.amd.com/Documents/J-Family-Product-Brief.pdf {{Bare URL PDF|date=March 2022}}</ref>
* 2 "[[Engineering:Excavator (microarchitecture)|Excavator+]]" x86 cores with 1MB shared L2 cache
* L1 Cache: 32 KB Data per core and 96 KB Instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], [[RDRAND]]
* GPU microarchitecture: Radeon R5E [[Graphics Core Next]] (GCN) (up to 3 CUs) with support for DirectX 12
* Single channel 64-bit DDR4 or DDR3 memory
* 4K × 2K H.265 decode capability with 10-bit compatibility and multi format encode and decode
* Integrated Controller Hub supports: PCIe 3.0 1×4, PCIe 2/3 4×1, 2 USB3 + 2 USB2 ports, 2 SATA 2.0/3.0 ports
{| class="wikitable sortable" style="text-align: center"
! {{rh}} rowspan="3" | Model !! rowspan="3" | Released 
! rowspan="3" |Fab!! colspan="5" | CPU !! colspan="5" | GPU !! rowspan="3" | Memory<br />support !! rowspan="3" | TDP
(W)
! rowspan="3" | [[Physics:Junction temperature|Junction temperature]] (°C) !! rowspan="3" | Part number
|-
! rowspan="2" | [Modules/[[Floating-point unit|FPUs]]]<br />[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]] !! rowspan="2" | Clock
(GHz)
! rowspan="2" | Turbo
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan="2" | Model !! rowspan="2" | Config{{NoteTag|name=fn_2}} !! rowspan="2" | Clock
(MHz)
! rowspan="2" | Turbo !! rowspan="2" | Processing<br />power<br />(GFLOPS){{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
|-
! {{rh}} | GX-212JJ
| 2018 
| rowspan="4" |28&nbsp;nm|| rowspan="4" | [1] 2 || 1.2 || 1.6 || rowspan="4" | 96&nbsp;KB inst.<br />per module<br /><br />32&nbsp;KB data<br />per core || rowspan=4| 1 || R1E || 64:4:1<br />1 CU || rowspan="4" | 600 || rowspan=4 {{n/a}} || 76.8 || DDR3-1333<br />DDR4-1600 || rowspan="2" | 6–
10
| rowspan="4" | 0-90 || GE212JAWY23AC
|-
! {{rh}} | GX-215JJ
| 2017 || 1.5 || 2.0 || rowspan="2" | R2E || rowspan="2" | 128:8:2<br />2 CU || rowspan="2" | 153.6 || rowspan="2" | DDR3-1600<br />DDR4-1866 || GE215JAWY23AC
|-
! {{rh}} | GX-220IJ
| 2018 || 2.0 || 2.2 || rowspan="2" | 10–
15
| GE220IAVY23AC
|-
! {{rh}} | GX-224IJ
| 2017 || 2.4 || 2.8 || R4E || 192:12:3<br />3 CU || 230.4 || DDR3-1866<br />DDR4-2133 || GE224IAVY23AC
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

=== R-Series ===

==== Comal: "Trinity" (2012) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 32&nbsp;nm
* Socket FP2 (BGA-827), FS1r2
* CPU microarchitecture: [[Engineering:Piledriver (microarchitecture)|Piledriver]]
* L1 Cache: 16 KB Data per core and 64 KB Instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]] 1.1, [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]],<ref name="auto"/> [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]]
* GPU microarchitecture: TeraScale 3 (VLIW4) "Northern Islands"
* Memory support: dual-channel 1.35&nbsp;V DDR3L-1600 memory, in addition to regular 1.5&nbsp;V DDR3
* 2.5&nbsp;GT/s UMI
* Die size: 246&nbsp;mm²; Transistors: 1.303&nbsp;billion
* OpenCL 1.1 and OpenGL 4.2 support

{| class="wikitable sortable" style="text-align: center"
! {{rh}} rowspan="3" | Model 
! rowspan="3" |Released
! rowspan="3" |Fab!! rowspan="3" | Step. !! colspan="5" | CPU !! colspan="5" | GPU !! rowspan="3" | DDR3
Memory<br />support
! rowspan="3" | TDP
(W)
! rowspan="3" | Part number
|-
! rowspan="2" | [Modules/[[Floating-point unit|FPUs]]]<br />[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]] !! rowspan="2" | Clock
(GHz)
! rowspan="2" | Turbo
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan="2" | Model !! rowspan="2" | Config{{NoteTag|name=fn_2}} !! rowspan="2" | Clock
(MHz)
! rowspan="2" | Turbo
(MHz)
! rowspan="2" | Processing<br />power<br />(GFLOPS){{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
|-
! {{rh}} | R-252F
| rowspan="8" |May 21, 2012
| rowspan="8" |32&nbsp;nm
| rowspan="8" | B0 || rowspan="4" | [1] 2 || 1.9 || 2.4 || rowspan="8" | 64&nbsp;KB inst.<br />per module<br /><br />16&nbsp;KB data<br />per core || 1 || HD 7400G || 192:12:4<br />3 CU || 333 || 417 || 127.8 || rowspan="2" | 1333 || rowspan="2" | 17 || RE252FSHE23HJE
|-
! {{rh}} | R-260H
| 2.1 || 2.6 || 2? || HD 7500G || 256:16:8<br />4 CU || 327 || 424 || 167.4 || RE260HSHE24HJE
|-
! {{rh}} | R-268D
| 2.5 || 3.0 || rowspan="2" | 1 || HD 7420G || rowspan="2" | 192:12:4<br />3 CU || 470 || 640 || 180.4 || rowspan="4" | 1600 || rowspan="2" | 35 || RE268DDEC23HJE
|-
! {{rh}} | R-272F
| 2.7 || 3.2 || HD 7520G || 497 || 686 || 190.8 || RE272FDEC23HJE
|-
! {{rh}} | R-452L
| rowspan="4" | [2] 4 || 1.6 || 2.4 || rowspan="4" | 2 × 2&nbsp;MB || HD 7600G || rowspan="2" | 256:16:8<br />4 CU || 327 || 424 || 167.4 || 19 || RE452LSHE44HJE
|-
! {{rh}} | R-460H
| 1.9 || rowspan="2" | 2.8 || HD 7640G || 497 || 655 || 254.4 || 35 || RE460HDEC44HJE
|-
! {{rh}} | R-460L
| 2.0 || HD 7620G || rowspan="2" | 384:24:8<br />6 CU || 360 || 497 || 276.4 || 1333 || 25 || RE460LSIE44HJE
|-
! {{rh}} | R-464L
| 2.3 || 3.2 || HD 7660G || 497 || 686 || 381.6 || 1600 || 35 || RE464LDEC44HJE
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== "Bald Eagle" (2014) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm
* Socket FP3 
* Up to 4 [[Engineering:Steamroller (microarchitecture)|Steamroller]] x86 cores<ref>https://www.amd.com/Documents/2nd_Gen_Rseries_Product_Brief.pdf {{Bare URL PDF|date=March 2022}}</ref>
* L1 Cache: 16 KB Data per core and 96 KB Instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]] 1.1, [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]],<ref name="auto"/> [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]]
* GPU microarchitecture: [[Graphics Core Next]] (GCN) (up to 8 CUs) with support for DirectX 11.1 and OpenGL 4.2
* Dual channel DDR3 memory with [[ECC memory|ECC]]
* Unified Video Decode (UVD) 4.2 and Video Coding Engine (VCE) 2.0

{| class="wikitable sortable" style="text-align: center"
! {{rh}} rowspan="3" | Model 
! rowspan="3" |Released
! rowspan="3" |Fab!! colspan="5" | CPU !! colspan="5" | GPU !! rowspan="3" | DDR3
Memory<br />support
! rowspan="3" | TDP
(W)
! rowspan="3" | [[Physics:Junction temperature|Junction temperature]] (°C) !! rowspan="3" | Part number
|-
! rowspan="2" | [Modules/[[Floating-point unit|FPUs]]]<br />[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]] !! rowspan="2" | Clock
(GHz)
! rowspan="2" | Turbo
(GHz)
! colspan="2" | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan="2" | Model !! rowspan="2" | Config{{NoteTag|name=fn_2}} !! rowspan="2" | Clock
(MHz)
! rowspan="2" | Turbo
(MHz)
! rowspan="2" | Processing<br />power<br />(GFLOPS){{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
|-
! {{rh}} | RX-219NB
| rowspan="5" |May 20, 2014
| rowspan="5" |28&nbsp;nm|| rowspan="2" | [1] 2 || rowspan="2" | 2.2 || rowspan="2" | 3.0 || rowspan="5" | 96&nbsp;KB inst.<br />per module<br /><br />16&nbsp;KB data<br />per core || rowspan="2" | 1 || colspan="5" {{n/a}} || rowspan="2" | 1600 || rowspan="2" | 15-
17
| rowspan="5" | 0-100 || RE219NECH23JA
|-
! {{rh}} | RX-225FB
| R4 || 192:12:4<br />3 CU || 464 || 533 || 178.1 || RE225FECH23JA
|-
! {{rh}} | RX-425BB
| rowspan="3" | [2] 4 || 2.5 || 3.4 || rowspan="3" | 4 || R6 || 384:24:8<br />6 CU || 576 || 654 || 442.3 || 1866 || 30-
35
| RE425BDGH44JA
|-
! {{rh}} | RX-427BB
| rowspan="2" | 2.7 || rowspan="2" | 3.6 || R7  || 512:32:8<br />8 CU || 600 || 686 || 614.4 || rowspan="2" | 2133 || rowspan="2" | 30-
35
| RE427BDGH44JA
|-
! {{rh}} | RX-427NB
| colspan="5" {{n/a}} 
| RE427NDGH44JA
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

==== "Merlin Falcon" (2015, [[System on a chip|SoC]]) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 28&nbsp;nm
* Socket FP4 
* Up to 4 [[Engineering:Excavator (microarchitecture)|Excavator]] x86 cores<ref>https://www.amd.com/Documents/merlin-falcon-product-brief.pdf {{Bare URL PDF|date=March 2022}}</ref>
* L1 Cache: 32 KB Data per core and 96 KB Instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], FMA4, [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], [[RDRAND]]
* GPU microarchitecture: [[Graphics Core Next]] (GCN) (up to 8 CUs) with support for DirectX 12
* Dual channel 64-bit DDR4 or DDR3 memory with [[ECC memory|ECC]]
* Unified Video Decode (UVD) 6 (4K H.265 and H.264 decode) and Video Coding Engine (VCE) 3.1 (4K H.264 encode)
* Dedicated AMD Secure Processor supports secure boot with AMD Hardware Validated Boot (HVB)
* Integrated FCH featuring PCIe 3.0 USB3.0, SATA3, SD, GPIO, SPI, I2S, I2C, UART
{| class="wikitable sortable" style="text-align: center"
! {{rh}} rowspan="3" | Model !! rowspan="3" | Released 
! rowspan="3" |Fab!! rowspan="3" | Stepping !! colspan="6" | CPU !! colspan="5" | GPU !! rowspan="3" | Memory<br />support !! rowspan="3" | TDP
(W)
! rowspan="3" | [[Physics:Junction temperature|Junction temperature]] (°C) !! rowspan="3" | Part number
|-
! rowspan="2" | [Modules/[[Floating-point unit|FPUs]]]<br />[[Engineering:Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]] !! rowspan="2" | Clock
(GHz)
! rowspan="2" | Turbo
(GHz)
! colspan=3 | Cache{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945"/> }}
! rowspan="2" | Model !! rowspan="2" | Config{{NoteTag|name=fn_2}} !! rowspan="2" | Clock
(GHz)
! rowspan="2" | Turbo !! rowspan="2" | Processing<br />power<br />(GFLOPS){{efn|name="SFLOPS"}}
|-
! L1
! L2
(MB)
! L3
|-
! {{rh}} | RX-216TD
| rowspan="2" | October 21, 2015 
| rowspan="6" |28&nbsp;nm||  || rowspan="2" | [1] 2 || rowspan="3" | 1.6 || rowspan="2" | 3.0 || rowspan="6" | 96&nbsp;KB inst.<br />per module<br /><br />32&nbsp;KB data<br />per core || rowspan="2" | 1 || rowspan=6 {{n/a}} || colspan="5" {{n/a}} || rowspan="3" | DDR3/DDR4-1600 || rowspan="2" | 12-
15
| rowspan="2" | 0-90 || RE216TAAY23KA
|-
! {{rh}} | RX-216GD
| || R5 || 256:?:?<br />4 CU || 0.8 || rowspan=4 {{n/a}} || 409.6 || RE216GAAY23KA
|-
! {{rh}} | RX-416GD
| || || rowspan="4" | [2] 4 || 2.4 || rowspan="4" | 2 || rowspan="2" | R6 || 384:?:?<br />6 CU || 0.72 || 552.9 || 15 || -40-105 || RE416GATY43KA
|-
! {{rh}} | RX-418GD
| rowspan="3" | October 21, 2015 || || 1.8 || 3.2 || 384:?:?<br />6 CU || rowspan="2" | 0.8 || 614.4 || rowspan="3" | DDR3-2133<br />DDR4-2400 || rowspan="3" | 12-
35
| rowspan="3" | 0-90 || RE418GAAY43KA
|-
! {{rh}} | RX-421BD
| || rowspan="2" | 2.1 || rowspan="2" | 3.4 || R7 || 512:?:?<br />8 CU || 819.2 || RE421BAAY43KA
|-
! {{rh}} | RX-421ND
| || colspan="5" {{n/a}} || RE421NAAY43KA
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a FMA operation.}}
}}

===1000-Series===
==== V1000-Family: "Great Horned Owl" (2018, [[System on a chip|SoC]]) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 14&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* Up to 4 Zen cores
* Socket FP5
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[FMA instruction set#FMA3 instruction set|FMA3]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[RDRAND]], Turbo Core
* Dual channel DDR4 memory with [[ECC memory|ECC]]
* Fifth generation [[Graphics Core Next#GCN 5th Generation (Vega)|GCN]] based GPU

==== R1000-Family: "Banded Kestrel" (2019, [[System on a chip|SoC]]) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 14&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* Up to 2 Zen cores
* Socket FP5
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[FMA instruction set#FMA3 instruction set|FMA3]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[RDRAND]], Turbo Core
* Dual channel DDR4 memory with [[ECC memory|ECC]]
* Fifth generation [[Graphics Core Next#GCN 5th Generation (Vega)|GCN]] based GPU

===2000-Series===
==== V2000-Family: "Grey Hawk" (2020, [[System on a chip|SoC]]) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 7&nbsp;nm by [[Company:TSMC|TSMC]]
* Up to 8 [[Engineering:Zen 2|Zen 2]] cores
* Fifth generation [[Graphics Core Next#GCN 5th Generation (Vega)|GCN]] based GPU
==== R2000-Family: "River Hawk" (2022, [[System on a chip|SoC]]) ====
* [[Engineering:Semiconductor device fabrication|Fabrication]] 12&nbsp;nm by [[Company:GlobalFoundries|GlobalFoundries]]
* Up to 4 [[Engineering:Zen+|Zen+]] cores
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], AVX2, [[FMA instruction set#FMA3 instruction set|FMA3]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[RDRAND]], Turbo Core

== Custom APUs ==
As of May 1, 2013, AMD opened the doors of their "semi-custom" business unit.<ref>{{cite web |url=http://www.xbitlabs.com/news/other/display/20130501231534_AMD_Establishes_Semi_Custom_Business_Unit_to_Create_Tailored_Products_with_Customer_Specific_IP.html |title=AMD Establishes Semi-Custom Business Unit to Create Tailored Products with Customer-Specific IP |access-date=November 10, 2013 |url-status=dead |archive-url=https://web.archive.org/web/20131001071304/http://www.xbitlabs.com/news/other/display/20130501231534_AMD_Establishes_Semi_Custom_Business_Unit_to_Create_Tailored_Products_with_Customer_Specific_IP.html |archive-date=October 1, 2013 }}</ref> Since these chips are custom-made for specific customer needs, they vary widely from both consumer-grade APUs and even the other custom-built ones. Some notable examples of semi-custom chips that have come from this sector include the chips from the PlayStation&nbsp;4 and [[Engineering:Xbox One|Xbox One]].<ref>{{cite web |url=http://www.polygon.com/2013/6/15/4431474/amd-xbox-one-ps4-wii-u-e3-1023 |title=Three for three: How AMD won the war for the heart of next-gen consoles |website=Polygon |date=June 15, 2013 |access-date=November 10, 2013}}</ref> So far the size of the integrated GPU in these semi-custom APUs exceed by far the GPU size in the consumer-grade APUs.


== See also ==
* [[Engineering:List of AMD chipsets|List of AMD chipsets]]
* [[Engineering:List of AMD FX microprocessors|List of AMD FX microprocessors]]
* [[Engineering:List of AMD graphics processing units|List of AMD graphics processing units]]
* [[Engineering:Ryzen|Ryzen]]

== Notes ==
{{Notefoot|refs=
<!--{{NoteTag|name=fn_1|The clock multiplier applies to the 200&nbsp;MHz base clock. (AMD default clock base is 200&nbsp;MHz)}}-->
{{NoteTag|name=fn_2|[[Unified shader model|Unified shader processors]] (USPs): [[Texture mapping unit]]s (TMUs): [[Render output unit]]s (ROPs). 1 CU (Compute Unit) {{=}} 64 USPs: 4 TMUs : 1 ROPs}}
<!--{{NoteTag|name=fn_3|Models enabled by Turbo Core technology, up to 10% clock speed increase is planned. With CPU boost, only one core of a dual-core model has boost enabled.}}-->
<!--{{NoteTag|name=fn_5|One AMD module consists of two integer cores and two FPUs, which can be combined into one wide FPU for executing certain instructions, such as FMA. The two cores share certain resources, but are two separate units.}}-->
}}

== References ==
{{reflist|30em}}

== External links ==
* [http://products.amd.com/en-us/ Technical specification AMD products]
* [https://www.amd.com/us/products/Pages/products.aspx AMD products and technologies]

{{AMD processors}}
{{AMD CPU sockets}}
{{AMD graphics}}

{{DEFAULTSORT:AMD accelerated processing units, List of}}
[[Category:Lists of microprocessors]]

{{Sourceattribution|List of AMD processors with 3D graphics}}