View source for Engineering:List of Intel CPU microarchitectures

{{Short description|None}}
{{Incomplete list|date=December 2020}}
The following is a ''partial'' list of [[Company:Intel|Intel]] CPU [[Microarchitecture|microarchitecture]]s. The list is ''incomplete'', additional details can be found in Intel's [[Engineering:Tick–tock model|Tick–tock model]], [[Engineering:Process–architecture–optimization model|Process–architecture–optimization model]] and Template:Intel processor roadmap.

== x86 microarchitectures ==
{| class="wikitable floatright sortable mw-datatable"
|+x86 microarchitectures
! Year
! Micro-<wbr />architecture
! style="width:9.5em" | Pipeline stages
! Max<br />clock<br />(MHz)
! Process node
|-
| 1978
| [[Engineering:Intel 8086|8086]] (8086, [[Engineering:Intel 8088|8088]])
| {{0}}2
| {{0}}5
| rowspan="2" | 3000 nm
|-
| 1982
| [[Engineering:Intel 80186|186]] (80186, [[Engineering:Intel 80188|80188]])
| {{0}}2
| {{0}}25
|-
| 1982
| [[Engineering:Intel 80286|286]] (80286)
| {{0}}3
| {{0}}25
| rowspan="2" | 1500 nm
|-
| 1985
| [[Engineering:Intel 80386|386]] (80386)
| {{0}}6<ref>Rant, Jon; "Extending the Legacy of Leadership: The 80386 Arrives", Intel Corporation, Special 32-Bit Issue Solutions, November/December 1985, page 2</ref>
| {{0}}33
|-
| 1989
| [[Engineering:Intel 80486|486]] (80486)
| {{0}}5
| {{0}}100
| 1000 nm
|-
| 1993
| [[Engineering:P5 (microarchitecture)|P5]] (Pentium)
| {{0}}5
| {{0}}200
| 800, 600, 350 nm
|-
| 1995
| [[Engineering:P6 (microarchitecture)|P6]] (Pentium Pro, Pentium II)
| 14 (17 with load & store/<wbr />retire)
| {{0}}450
| 500, 350, 250 nm
|-
| 1997
| [[Engineering:P5 (microarchitecture)|P5]] (Pentium MMX)
| {{0}}6
| {{0}}233
| 350&nbsp;nm
|-
| 1999
| [[Engineering:P6 (microarchitecture)#From Pentium Pro to Pentium III|P6]] (Pentium III)
| 12 (15 with load & store/retire)
| 1400
| 250, 180, [[Engineering:130 nm process|130]] nm
|-
| 2000
| [[Engineering:NetBurst|NetBurst]]&nbsp;(Pentium&nbsp;4)<br />(Willamette)
| rowspan="2" | 20 unified with branch prediction
| 2000
| 180&nbsp;nm
|-
|2002
|NetBurst&nbsp;(Pentium&nbsp;4)<br />(Northwood, Gallatin)
|3466
|130&nbsp;nm
|-
| 2003
| Pentium M (Banias, Dothan)<br />Enhanced Pentium M (Yonah)
| 10 (12 with fetch/<wbr />retire)
| 2333
|130, [[Engineering:90 nm process|90]], 65 nm
|-
| 2004
| NetBurst&nbsp;(Pentium&nbsp;4, Pentium D)<br />([[Engineering:NetBurst#Revisions|Prescott]])
| 31 unified with branch prediction
| 3800
| 90, 65&nbsp;nm
|-
| 2006
| [[Engineering:Intel Core (microarchitecture)|Intel Core]]
| rowspan="2" | 12 (14 with fetch/retire)
| 3000
| 65&nbsp;nm
|-
| 2007
| [[Engineering:Penryn (microarchitecture)|Penryn]] (die shrink)
| 3333
| rowspan="3" | 45 nm
|-
| rowspan="2" | 2008
| [[Engineering:Nehalem (microarchitecture)|Nehalem]]
| 20 unified (14 without miss prediction)
| 3600
|-
| ''[[Engineering:Bonnell (microarchitecture)|Bonnell]]''
| 16 (20 with prediction miss)
| 2100
|-
| 2010
| [[Engineering:Westmere (microarchitecture)|Westmere]] (die shrink)
| 20 unified (14 without miss prediction)
| 3866
| rowspan="3" | 32 nm
|-
| rowspan="2" | 2011
| ''Saltwell (die shrink)''
| 16 (20 with prediction miss)
| 2130
|-
| [[Engineering:Sandy Bridge|Sandy Bridge]]
| rowspan="2" | 14 (16 with fetch/retire)
| 4000
|-
| 2012
| Ivy Bridge (die shrink)
| 4100
| rowspan="3" | [[Engineering:22 nm process|22]] nm
|-
| rowspan="2" | 2013
| ''[[Engineering:Silvermont|Silvermont]]''
| 14–17 (16–19 with fetch/retire)
| 2670
|-
| [[Haswell (microarchitecture)|Haswell]]
| rowspan="2" | 14 (16 with fetch/retire)
| 4400
|-
| 2014
| [[Broadwell (microarchitecture)|Broadwell]] (die shrink)
| 3700
| rowspan="5" | 14 nm
|-
| rowspan="2" | 2015
| ''Airmont (die shrink)''
| 14–17 (16–19 with fetch/retire)
| 2640
|-
| [[Skylake (microarchitecture)|Skylake]]
| 14 (16 with fetch/retire)
| 5200
|-
| 2016
| ''[[Engineering:Goldmont|Goldmont]]''
| 20 unified with branch prediction
| 2600
|-
| 2017
| ''[[Engineering:Goldmont Plus|Goldmont Plus]]''
| 20 unified with branch prediction (?)
| 2800
|-
| 2018
| Palm Cove
| 14 (16 with fetch/retire)
| 3200
| rowspan="4" | [[Engineering:10 nm process|10]] nm
|-
| 2019
| Sunny Cove
| 14–20 (misprediction)
| 4100
|-
| rowspan="2" | 2020
| [[Engineering:Tremont (microarchitecture)|''Tremont'']]
| 20 unified 
|3300
|-
| Willow Cove
| 14 unified 
|5300
|-
| rowspan="3" | 2021
| Cypress Cove 
| 14 unified 
| 5300
| 14 nm
|-
| [[Engineering:Golden Cove|Golden Cove]] 
| 12 unified
| 5500
| rowspan="3" | Intel 7
|-
| [[Engineering:Gracemont (microarchitecture)|''Gracemont'']] 
| 20 unified with misprediction penalty 
| 4300
|-
| 2022
| Raptor Cove
| 12 unified
| 6000
|-
| rowspan="2" |2023
|Redwood Cove
|
|
| rowspan="2" |[[Engineering:5 nm process|Intel 4]]
|-
|''Crestmont''
|
|
|-
! colspan="5" |<small>Note: Atom/Power efficient microarchitectures are in ''Italic''</small>
|}

=== [[16-bit computing|16-bit]] ===
; [[Engineering:Intel 8086|8086]]: first [[X86|x86]] processor; initially a temporary substitute for the iAPX 432 to compete with [[Company:Motorola|Motorola]], Zilog, and [[Company:National Semiconductor|National Semiconductor]] and to top the successful Z80. [[Engineering:Intel 8088|8088]] version, with an 8-bit bus, used in the original [[Engineering:IBM Personal Computer|IBM Personal Computer]].
; [[Engineering:Intel 80186|186]]: included a [[Direct memory access|DMA]] controller, interrupt controller, timers, and [[Engineering:Chip select|chip select]] logic. A small number of additional instructions.  The [[Engineering:Intel 80188|80188]] was a version with an 8-bit bus.
; [[Engineering:Intel 80286|286]]: first [[X86|x86]] processor with [[Protected mode|protected mode]] including segmentation based virtual memory management. Performance improved by a factor of 3 to 4 over 8086. Included instructions relating to protected mode.

=== [[32-bit computing|32-bit]] ([[IA-32]]) ===
; [[Engineering:Intel 80386|i386]]: first [[32-bit|32-bit]] [[X86|x86]] processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.
; [[Engineering:Intel 80486|i486]]: Intel's second generation of [[32-bit|32-bit]] [[X86|x86]] processors, introduced built-in floating point unit (FPU), 8&nbsp;KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.
; [[Engineering:P5 (microarchitecture)|P5]]: original Pentium microprocessors, first x86 processor with [[Superscalar processor|super-scalar]] architecture and branch prediction.
; [[Engineering:P6 (microarchitecture)|P6]]: used in [[Engineering:Pentium Pro|Pentium Pro]], [[Engineering:Pentium II|Pentium II]], Pentium II Xeon, [[Engineering:Pentium III|Pentium III]], and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, RISC μop decode scheme, integrated register renaming and [[Out-of-order execution|out-of-order execution]]. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, [[Physical Address Extension|"Physical Address Extension (PAE)"]].
:* Pentium M: updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.
:* Enhanced Pentium M: updated, dual core version of the Pentium M microarchitecture used in the first Intel Core microprocessors, first x86 to have [[Register file|shadow register architecture]] and speed step technology.
; [[Engineering:NetBurst|NetBurst]]:commonly referred to as '''P7''' although its internal name was P68 (P7 was used for [[Engineering:Itanium|Itanium]]). Used in [[Engineering:Pentium 4|Pentium 4]], [[Engineering:Pentium D|Pentium D]], and some [[Engineering:Xeon|Xeon]] microprocessors. Very long [[Instruction pipelining|pipeline]]. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's [[X86-64|x86-64]] architecture, enhanced branch prediction and trace cache, and eventually support was added for the [[NX bit|NX (No eXecute)]] bit to implement [[Executable space protection|executable-space protection]].

=== [[64-bit computing|64-bit]] ([[X86-64|x86-64]]) ===
; [[Engineering:Intel Core (microarchitecture)|Core]]: reengineered P6-based microarchitecture used in [[Engineering:Intel Core 2|Intel Core 2]] and [[Engineering:Xeon|Xeon]] microprocessors, built on a 65&nbsp;nm process, supporting [[X86-64|x86-64]] level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
:* [[Engineering:Penryn (microarchitecture)|Penryn]]: 45&nbsp;nm shrink of the Core microarchitecture with larger cache, higher [[Engineering:Front-side bus|FSB]] and clock speeds, [[SSE4|SSE4.1]] instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.
; [[Engineering:Nehalem (microarchitecture)|Nehalem]]: released November 17, 2008, built on a 45&nbsp;nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, [[SSE4|SSE4.2]].
:* [[Engineering:Westmere (microarchitecture)|Westmere]]: 32&nbsp;nm shrink of the Nehalem microarchitecture with several new features.
;
; [[Engineering:Sandy Bridge|Sandy Bridge]]:32&nbsp;nm microarchitecture, released January 9, 2011. Formerly called Gesher but renamed in 2007.<ref>{{cite web | url=http://blogs.intel.com/technology/2010/05/an_update_on_our_graphics-rela.php | title=An Update On Our Graphics-related Programs | date=May 25, 2010}}</ref> First x86 to introduce 256&nbsp;bit [[Advanced Vector Extensions|AVX]] instruction set and implementation of YMM registers.
:* Ivy Bridge: successor to Sandy Bridge, using 22&nbsp;nm process, released in April 2012.
; [[Haswell (microarchitecture)|Haswell]]: 22&nbsp;nm microarchitecture, released June 3, 2013. Added a number of new instructions, including AVX2 and [[FMA instruction set|FMA]].
:* [[Broadwell (microarchitecture)|Broadwell]]: 14&nbsp;nm derivative of the Haswell microarchitecture, released in September 2014. Three-cycle FMUL latency, 64 entry scheduler. Formerly called Rockwell.
; [[Skylake (microarchitecture)|Skylake]]:14&nbsp;nm microarchitecture, released August 5, 2015.
:* [[Kaby Lake]]: successor to Skylake, released in August 2016, broke Intel's Tick-Tock schedule due to delays with the 10&nbsp;nm process.
:** Amber Lake: ultra low power, mobile-only successor to Kaby Lake, using 14+ nm process, released in August 2018 (no architecture changes)<ref name="anandtech13301">{{Cite news|url=https://www.anandtech.com/show/13301/spectre-and-meltdown-in-hardware-intel-clarifies-whiskey-lake-and-amber-lake|title=Spectre and Meltdown in Hardware: Intel Clarifies Whiskey Lake and Amber Lake|last=Cutress|first=Ian|website=[[AnandTech]]|access-date=2018-09-02}}</ref>
:** [[Engineering:Whiskey Lake|Whiskey Lake]]: mobile-only successor to Kaby Lake Refresh, using 14++ nm process, released in August 2018 (has hardware mitigations for some vulnerabilities)<ref name="anandtech13301" />
:* [[Skylake (microarchitecture)|Skylake-X]]: high-end desktop, workstation and server microarchitecture, released on June 19, 2017 (HEDT), July 11, 2017 (SP) and August 29, 2017 (W). Introduces support for [[AVX-512]] instruction set.
:* [[Coffee Lake]]: successor to Kaby Lake, using 14++ nm process, released in October 2017
:* [[Engineering:Cascade Lake (microprocessor)|Cascade Lake]]: server and high-end desktop successor to Kaby Lake-X and [[Skylake (microarchitecture)|Skylake-X]], using 14++ nm process, released in April 2019
:* [[Engineering:Comet Lake|Comet Lake]]: successor to Coffee Lake, using 14++ nm process, released in August 2019<ref>{{cite web|url=https://newsroom.intel.com/news/intel-expands-10th-gen-intel-core-mobile-processor-family-offering-double-digit-performance-gains/|title=Intel Expands 10th Gen Intel Core Mobile Processor Family, Offering Double Digit Performance Gains|website=Intel Newsroom|language=en-US|access-date=2019-08-21}}</ref>
:* Cooper Lake: server-only, optimized for [[Artificial intelligence|AI]] oriented workloads using [[Bfloat16 floating-point format|bfloat16]], with limited availability only to Intel priority partners, using 14++ nm process, released in 2020<ref name="cooper-lake-fades-away">{{cite web|url=https://www.anandtech.com/show/15631/intels-cooper-lake-plans-the-chip-that-wasnt-meant-to-exist-dies-for-you|title=Intel's Cooper Lake Plans: The Chip That Wasn't Meant to Exist, Fades Away|last=Cutress|first=Ian|website=[[AnandTech]]|access-date=2020-03-18}}</ref><ref>{{cite web|url=https://www.servethehome.com/intel-cooper-lake-rationalized-still-launching-1h-2020/|title=Intel Cooper Lake Rationalized Still Launching 1H 2020|last=Kennedy|first=Patrick|date=2020-03-16|website=ServeTheHome|language=en-US|access-date=2020-03-18}}</ref>
:
; Palm Cove: After releasing the Palm Cove core, Intel has changed their microarchitecture naming scheme, decoupling the CPU cores from their manufacturing nodes.<ref>{{cite web|url=https://fuse.wikichip.org/news/1941/intel-reveals-10nm-sunny-cove-core-a-new-core-roadmap-and-teases-ice-lake-chips/|title=Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips|first=David|last=Schor|date=December 23, 2018|website=WikiChip Fuse}}</ref><ref>{{cite web|last=Paul|first=Ian|title=CPUs Decoded: Understanding Intel's Microarchitecture Names|url=https://www.howtogeek.com/680036/cpus-decoded-understanding-intels-microarchitecture-names/|access-date=2021-04-06|website=How-To Geek|language=en-US}}</ref><br />Successor to Skylake (canceled), includes the [[AVX-512]] instruction set.<ref>{{cite web|last=Cutress|first=Ian|title=Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review|url=https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review|access-date=2021-04-06|website=www.anandtech.com}}</ref><ref>{{cite web|url=https://en.wikichip.org/wiki/intel/microarchitectures/palm_cove|title=Palm Cove - Microarchitectures - Intel - WikiChip|website=en.wikichip.org|language=en|access-date=2020-01-05}}</ref>
:* Cannon Lake: mobile-only successor of Kaby Lake, using Intel's 10&nbsp;nm process, first and only microarchitecture to implement the Palm Cove core, released in May 2018. Formerly called Skymont, discontinued in December 2019.<ref>{{cite web|url=https://www.tomshardware.com/news/intel-fires-10nm-cannon-lake-nuc-into-oblivion|title=Intel Fires 10nm Cannon Lake NUC Into Oblivion|first=Zhiye|last=Liu|date=October 31, 2019|website=[[Tom's Hardware]]}}</ref>
; Sunny Cove:Successor to the Palm Cove core, first non-Atom core to include hardware acceleration for [[Secure Hash Algorithms|SHA]] hashing algorithms.<ref>{{cite web|url=https://en.wikichip.org/wiki/intel/microarchitectures/sunny_cove|title=Sunny Cove - Microarchitectures - Intel|website=WikiChip Chips & Semi}}</ref>
:* [[Engineering:Ice Lake (microprocessor)|Ice Lake]]: low power, mobile-only successor to Whiskey Lake, using 10&nbsp;nm process, released in September 2019
:* Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Sunny Cove is used in the singular performance core (P-core) of Lakefield processors.<ref name="anandtech-lakefield-deep-dive">{{cite web|title=The Intel Lakefield Deep Dive: Everything To Know About the First x86 Hybrid CPU|url=https://www.anandtech.com/show/15877/intel-hybrid-cpu-lakefield-all-you-need-to-know|first=Ian|last=Cutress|date=July 2, 2020|website=[[AnandTech]]}}</ref> AVX and more advanced instruction sets are disabled due to the E-core not supporting them.
:* Ice Lake-SP: server-only successor to Cascade Lake, using 10&nbsp;nm process, released in April 2021<ref name="cooper-lake-fades-away" /><ref>{{cite web|url=https://newsroom.intel.com/news/new-intel-processors-accelerate-5g-network-transformation/ |title=New Intel Processors Accelerate 5G Network Transformation |publisher=Newsroom.intel.com |date=2021-04-06 |accessdate=2022-05-08}}</ref>
; Cypress Cove: Backport of Sunny Cove to Intel's 14&nbsp;nm process
:* [[Engineering:Rocket Lake|Rocket Lake]]: Successor to Comet Lake, using Intel's 14++&nbsp;nm process, released on March 30, 2021<ref>{{cite web|url=https://www.anandtech.com/show/16495/intel-rocket-lake-14nm-review-11900k-11700k-11600k|title=Intel octet Lake (14nm) Review: Core i911900K, Core i7-11700K, and Core i5-11600K|first=Ian|last=Cutress|date=March 30, 2021|website=[[AnandTech]]}}</ref><ref>{{cite web|url=https://www.anandtech.com/show/16145/intel-confirms-rocket-lake-on-desktop-for-q1-2021-with-pcie-40|title=Intel Confirms Rocket Lake on Desktop for Q1 2021, with PCIe 4.0|website=[[AnandTech]]|access-date=2020-10-07}}</ref><ref name=":3">{{cite web|url=https://www.anandtech.com/show/16205/intels-11th-gen-core-rocket-lake-detailed-ice-lake-core-with-xe-graphics|title=Intel's 11th Gen Core Rocket Lake Detailed: Ice Lake Core with Xe Graphics|first=Ian|last=Cutress|date=October 29, 2020|website=[[AnandTech]]}}</ref>
; Willow Cove:Successor to the Sunny Cove core, includes new security features and redesigns the cache subsystem.<ref>{{cite web|url=https://en.wikichip.org/wiki/intel/microarchitectures/willow_cove|title=Willow Cove - Microarchitectures - Intel|website=WikiChip Chips & Semi}}</ref>
:* [[Tiger Lake]]: successor to Ice Lake, using Intel's 10&nbsp;nm SuperFin (10SF) process, released in Q4 2020
; [[Engineering:Golden Cove|Golden Cove]]:Successor to the Willow Cove core, includes improvements to performance and power efficiency. Also includes new instructions.<ref>{{cite web|last=Cutress|first=Dr Ian|title=Intel Alder Lake: Confirmed x86 Hybrid with Golden Cove and Gracemont for 2021|url=https://www.anandtech.com/show/15979/intel-alder-lake-confirmed-x86-hybrid-with-golden-cove-and-gracemont-for-2021|access-date=2021-04-10|website=www.anandtech.com}}</ref>
:* [[Engineering:Alder Lake|Alder Lake]]: hybrid processor, succeeds Rocket Lake and Tiger Lake; uses Intel&nbsp;7 process (previously known as 10ESF),<ref name=":5">{{cite web|last=Cutress|first=Dr Ian|title=Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!|url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros|access-date=2021-07-27|website=www.anandtech.com}}</ref> released on November 4, 2021.<ref>{{cite web|url=https://www.anandtech.com/show/15686/intel-updates-isa-manual-new-instructions-for-alder-lake-also-bf16-for-sapphire-rapids|title=Intel Updates ISA Manual: New Instructions for Alder Lake, also BF16 for Sapphire Rapids|first=Ian|last=Cutress|date=April 1, 2020|website=[[AnandTech]]}}</ref> Golden Cove is used in P-cores of Alder Lake processors.<ref name="anandtech-alder-lake-detailed">{{cite web|url=https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures|title=Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed|date=2021-08-19|last1=Cutress|first1=Ian|last2=Frumusanu|first2=Andrei|website=[[AnandTech]]|language=en|access-date=2021-08-25}}</ref>
:* [[Engineering:Sapphire Rapids|Sapphire Rapids]]: server and workstation-only, successor to Ice Lake-SP, manufactured on Intel&nbsp;7 process,<ref name=":5" /><ref name="pirzada1">{{cite web|last=Pirzada|first=Usman|date=2020-10-07|title=Intel Sapphire Rapids: MCM Design, 56 Golden Cove Cores, 64GB HBM2 On-Board Memory, Massive IPC Improvement and 400 Watt TDP|url=https://wccftech.com/intel-sapphire-rapids-mcm-design-56-golden-cove-cores-64gb-hbm2-on-board-memory-massive-ipc-improvement-and-400-watt-tdp/|access-date=2021-04-06|website=Wccftech|language=en-US}}</ref> released on January 10, 2023. Introduces [[Advanced Matrix Extensions|AMX]].
; Raptor Cove:A refresh of Golden Cove with increased L2 and L3 caches and core clocks.
:* [[Engineering:Raptor Lake|Raptor Lake]]: successor to Alder Lake with increased cache sizes, core clocks and the number of E-cores, released on October 20, 2022. Manufactured using Intel&nbsp;7 process. Raptor Cove is used in the P-cores while the E-cores are still implemented using Gracemont microarchitecture.

=== x86 [[Ultra-low-voltage processor|ULV]] ([[Engineering:Intel Atom|Atom]]) ===

;[[Engineering:Bonnell (microarchitecture)|Bonnell]]
: 45&nbsp;nm, low-power, in-order microarchitecture for use in [[Engineering:Intel Atom|Atom]] processors.
:* Saltwell: 32&nbsp;nm shrink of the Bonnell microarchitecture.

;[[Engineering:Silvermont|Silvermont]]
: 22&nbsp;nm, out-of-order microarchitecture for use in Atom processors, released on May 6, 2013.
:* Airmont: 14&nbsp;nm shrink of the Silvermont microarchitecture.

;[[Engineering:Goldmont|Goldmont]]
: 14&nbsp;nm [[Engineering:Atom (system on chip)|Atom]] microarchitecture iteration after Silvermont but borrows heavily from Skylake processors (e.g., GPU), released in April 2016.<ref name="software.intel.com">{{cite web|title=Intel Software Development Emulator|url=http://software.intel.com/en-us/articles/intel-software-development-emulator}}</ref><ref name="forums.anandtech.com">{{cite web|title="Goldmont"- the sequel to Silvermont Atom?|url=https://forums.anandtech.com/threads/goldmont-the-sequel-to-silvermont-atom.2332517/|access-date=2020-03-02}}</ref>
:* [[Engineering:Goldmont Plus|Goldmont Plus]]: successor to Goldmont microarchitecture, still based on the 14&nbsp;nm process, released on December 11, 2017.

; [[Engineering:Tremont (microarchitecture)|Tremont]]:10&nbsp;nm [[Engineering:Atom (system on chip)|Atom]] microarchitecture iteration after Goldmont Plus.<ref name="the-tremont-core" />
:* Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Tremont is used in efficiency cores (E-cores) of Lakefield processors.<ref name="anandtech-lakefield-deep-dive"/>
:* [[Engineering:Tremont (microarchitecture)#Desktop processors (Jasper Lake)|Jasper Lake]]: Celeron and Pentium Silver desktop and mobile processors, released in Q1 2021.
:* Elkhart Lake: embedded processors targeted at [[Internet of things|IoT]], released in Q1 2021.

;[[Engineering:Gracemont (microarchitecture)|Gracemont]]
:Intel&nbsp;7 process<ref name=":5" /> [[Engineering:Atom (system on chip)|Atom]] microarchitecture iteration after Tremont. First Atom class core with AVX and AVX2 support.
:* [[Engineering:Alder Lake|Alder Lake]]: hybrid processor, succeeds Rocket Lake and Tiger Lake, released on November 4, 2021. Gracemont is used in E-cores of Alder Lake processors.<ref name="anandtech-alder-lake-detailed"/>
:* [[Engineering:Raptor Lake|Raptor Lake]]: a refresh of Alder Lake, released on October 20, 2022.

== Other microarchitectures ==

=== [[Engineering:IA-64|IA-64]] ([[Engineering:Itanium|Itanium]]) ===
; [[Engineering:Itanium#Itanium (Merced): 2001|Merced]]: original Itanium microarchitecture.  Used only in the first [[Engineering:Itanium|Itanium]] microprocessors.
; McKinley: enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor. Madison is the 130&nbsp;nm version.
; [[Engineering:Montecito (processor)|Montecito]]: enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors.  Added dual core, coarse multithreading, and other improvements. The Montvale update added demand-based switching ([[Engineering:SpeedStep|SpeedStep]]) and core-level [[Lockstep (computing)|lockstep]] execution.
; [[Engineering:Tukwila (processor)|Tukwila]]: enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, an integrated memory controller, QuickPath Interconnect, and other improvements e.g. a more active SoEMT.
; Poulson: Itanium processor featuring an all-new microarchitecture.<ref name="xbit-070719">{{cite web | url=http://www.xbitlabs.com/news/cpu/display/20070619230827.html | title=Intel Plans to change Itanium Micro-Architecture | date=June 19, 2007 | author=Anton Shilov | publisher=X-bit Labs | access-date=2007-10-05 | url-status=dead | archive-url=https://web.archive.org/web/20071005082838/http://www.xbitlabs.com/news/cpu/display/20070619230827.html | archive-date=October 5, 2007 }}</ref> 8 cores, decoupling in pipeline and in multithreading. 12-wide issue with partial out-of-order execution.<ref>{{cite web|author=David Kanter |url=https://www.realworldtech.com/poulson/ |title=Poulson: The Future of Itanium Servers |publisher=Realworldtech.com |date=2011-05-18 |accessdate=2022-05-08}}</ref>
; Kittson: the last Itanium. It has the same microarchitecture as Poulson, but slightly higher clock speed for the top two models.

=== Miscellaneous ===

;[[Engineering:XScale|XScale]]
: a microarchitecture implementing the [[ARM architecture|ARM]] architecture instruction set.
;[[Engineering:Larrabee (microarchitecture)|Larrabee]] (cancelled 2010)
: multi-core in-order [[X86-64|x86-64]] updated version of P5 microarchitecture, with wide [[SIMD]] vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).

==Roadmap==
===Pentium 4 / Core lines===
{| class="wikitable sortable mw-collapsible collapsible floatleft mw-datatable" style="margin:0.5em auto; text-align:center; min-width:80em;"
|+Pentium 4 / Core roadmap
|-
! rowspan="2" | [[Engineering:Semiconductor device fabrication|{{abbr|Fab|Fabrication}}<br />process]]
! rowspan="2" | Micro-<br />{{abbr|arch|architecture}}
! rowspan="2" | Code<br />names
! rowspan="2" | Core<br />{{abbr|gen|generation}}
! rowspan="2" | Xeon<br />Scalable<br />{{abbr|gen|generation}}
! rowspan="2" | Release<br />date
! colspan="5" | Processors
|-
! Desktop
! Mobile
! Enthusiast<br />/<abbr title="Workstation">WS</abbr>
! 2P<br />Server/<abbr title="Workstation">WS</abbr>
! 4P/8P<br />Server
|-
| 180 nm
| rowspan="4" | [[Engineering:P6 (microarchitecture)|P6]],<br/>[[Engineering:NetBurst|NetBurst]]
| Willamette
| colspan="2" rowspan="3" {{N/A}}
| 2000-11-20
| Willamette
| colspan="2" {{N/A}}
| Foster
| Foster MP
|-
| [[Engineering:130 nm process|130 nm]]
| Northwood/<br/>Mobile Pentium&nbsp;4<br />[[Engineering:Pentium M|Banias]]<br/>
| 2002-01-07
| Northwood
| Northwood Mobile<br />[[Engineering:Pentium M|Banias]]<br/>
| Northwood-XE
| Prestonia<br />Gallatin
| Gallatin
|-
| [[Engineering:90 nm process|90 nm]]
| Prescott<br />[[Engineering:Pentium M|Dothan]]<br/>
| 2004-02-01
| Prescott<br/>Smithfield
| [[Engineering:Pentium M|Dothan]]<br/>
| Prescott 2M-XE<br/>Smithfield-XE
| Nocona<br />Irwindale<br />Paxville
| Potomac<br />Cranford<br />Paxville
|-
| rowspan="2" | 65 nm
| [[Engineering:Pentium 4#Cedar Mill|Cedar Mill]]<br/>[[Engineering:Yonah (microprocessor)|Yonah]]<br/>Presler
| Core<br />(Yonah only)
| rowspan="3" {{N/A}}
| 2006-01-05
| [[Engineering:Pentium 4#Cedar Mill|Cedar Mill]]<br/>[[Engineering:Pentium D#Presler|Presler]]
| [[Engineering:Yonah (microprocessor)|Yonah]]
| [[Engineering:Pentium D#Presler|Presler-XE]]
| Dempsey<br />Sossaman
| [[Engineering:List of Intel Xeon microprocessors#"Tulsa" (65 nm)|Tulsa]]
|-
| rowspan="2" | [[Engineering:Intel Core (microarchitecture)|Core]]
| Merom<ref>{{cite web|last=Crothers |first=Brooke |url=http://news.cnet.com/8301-13924_3-10160673-64.html |title=Intel moves up rollout of new chips {{!}} Nanotech - The Circuits Blog - CNET News |publisher=News.cnet.com |date=2009-02-10 |access-date=2014-02-25}}</ref>
| rowspan="2" |Core&nbsp;2
| 2006-07-27<br/><ref>{{cite web|url=http://www.intel.com/pressroom/archive/releases/20060105corp.htm|title=Intel CEO: Latest Platforms, Processors Form New Foundations For Digital Entertainment And Wireless Computing}}</ref><ref>{{cite web|url=http://www.intel.com/pressroom/archive/releases/20060727comp.htm|title=Intel Unveils World's Best Processor}}</ref>
| Conroe
| [[Engineering:Merom (microprocessor)|Merom]]
| [[Engineering:Kentsfield (microprocessor)|Kentsfield]]
| Woodcrest<br />Clovertown
| Tigerton
|-
| rowspan="2" | 45 nm
| [[Engineering:Penryn (microarchitecture)|Penryn]]
| 2007-11-11<br/><ref>{{cite web|url=http://www.intel.com/pressroom/archive/releases/20080107comp.htm|title=Intel Unveils 16 Next-Generation Processors, Including First Notebook Chips Built on 45nm Technology}}</ref>
| [[Engineering:Wolfdale (microprocessor)|Wolfdale]]
| [[Engineering:Penryn (microprocessor)|Penryn]]
| [[Engineering:Yorkfield|Yorkfield]]
| Harpertown
| Dunnington
|-
| rowspan="2" | [[Engineering:Nehalem (microarchitecture)|Nehalem]]
| [[Engineering:Nehalem (microarchitecture)|Nehalem]]
| rowspan="2" | Previous<ref>{{cite web|url=https://ark.intel.com/|title=ARK {{!}} Your source for information on Intel products|date=2013-05-30|website=Intel|archive-url=https://web.archive.org/web/20130530074015/http://ark.intel.com/|archive-date=2013-05-30|url-status=unfit|access-date=2013-05-30}}</ref><br />(Core i)
| rowspan="7" {{N/A}}
| 2008-11-17<br/><ref>{{cite web|url=http://www.intel.com/pressroom/archive/releases/2008/20081117comp_sm.htm|title=Intel Launches Fastest Processor on the Planet|website=www.intel.com}}</ref>
| [[Engineering:Lynnfield (microprocessor)|Lynnfield]]
| [[Engineering:Clarksfield (microprocessor)|Clarksfield]]
| [[Engineering:Bloomfield (microprocessor)|Bloomfield]]
| [[Engineering:List of Intel Xeon microprocessors#"Gainestown" (45 nm)|Gainestown]]
| [[Engineering:List of Intel Xeon microprocessors#"Beckton" (45 nm)|Beckton]]
|-
| rowspan="2" | 32 nm
| [[Engineering:Westmere (microarchitecture)|Westmere]]
| 2010-01-04<br/><ref name="MarkBohr">{{cite web|url=http://download.intel.com/pressroom/kits/32nm/westmere/Mark_Bohr_32nm.pdf|title=Intel 32nm Technology|author=Mark Bohr (Intel Senior Fellow, Logic Technology Development)|date=2009-02-10}}</ref><ref>{{cite web|url=http://www.intel.com/technology/architecture-silicon/32nm/index.htm|title=Intel - Data Center Solutions, IoT, and PC Innovation|website=Intel}}</ref>
| [[Engineering:Clarkdale (microprocessor)|Clarkdale]]
| Arrandale
| [[Gulftown]]
| [[Gulftown|Westmere-EP]]
| Westmere-EX
|-
| rowspan="2" | [[Engineering:Sandy Bridge|Sandy<br/>Bridge]]
| [[Engineering:Sandy Bridge|Sandy<br/>Bridge]]
| 2 (Core i)
| 2011-01-09<br/><ref>{{cite web|url=http://news.cnet.com/8301-13924_3-20022893-64.html|title=Intel Sandy Bridge chip coming January 5}}</ref>
| [[Engineering:Sandy Bridge|Sandy Bridge]]
| [[Engineering:Sandy Bridge|Sandy Bridge-M]]
| Sandy Bridge-E
| [[Engineering:Sandy Bridge|Sandy Bridge-EP]]
| {{N/A}}<ref>{{cite web|url=http://news.softpedia.com/news/Intel-Ivy-Bridge-CPU-Range-Complete-by-Next-Year-263451.shtml|title=Intel Ivy Bridge CPU Range Complete by Next Year|first=Sebastian|last=Pop|date=9 April 2012 }}</ref>
|-
| rowspan="3" | [[Engineering:22 nm process|22&nbsp;nm]]
| Ivy<br/>Bridge
| 3
| 2012-04-29
| Ivy Bridge
| Ivy Bridge-M
| Ivy Bridge-E<br /><ref>{{cite web|url=http://www.techspot.com/news/47849-ivy-bridge-e-delayed-until-second-half-of-2013.html|title=Ivy Bridge-E delayed until second half of 2013}}</ref>
| Ivy Bridge-EP<br /><ref name="vr-z" />
| Ivy Bridge-EX<br/><ref name="vr-z">{{cite web|url=http://vr-zone.com/articles/ivy-bridge-ep-and-ex-coming-up-in-a-year-s-time--the-multi-socket-platform-heaven/15488.html|title=Ivy Bridge EP and EX coming up in a year's time - the multi-socket platform heaven|date=9 April 2012}}</ref>
|-
| rowspan="3" | [[Haswell (microarchitecture)|Haswell]]
| [[Haswell (microarchitecture)|Haswell]]
| rowspan="2" | 4
| 2013-06-02
| Haswell-DT<br /><ref name="hsw-specs">{{cite web |url=http://technewspedia.com/leaked-specifications-of-haswell-gt1gt2gt3-igp |title=Leaked specifications of Haswell GT1/GT2/GT3 IGP |publisher=Tech News Pedia |date=2012-05-20 |access-date=2014-02-25 |archive-url=https://web.archive.org/web/20120919234611/http://technewspedia.com/leaked-specifications-of-haswell-gt1gt2gt3-igp/ |archive-date=2012-09-19 |url-status=dead }}</ref>
| Haswell-MB<br />Haswell-H<br />Haswell-ULP/ULX<ref name="hsw-specs" />
| Haswell-E
| Haswell-EP
| Haswell-EX
|-
| Devil's<br/>Canyon
| 2014-06
| Haswell-DT
| colspan="4" {{N/A}}
|-
| rowspan="10" | 14&nbsp;nm
| [[Broadwell (microarchitecture)|Broadwell]]
| 5
| 2014-09-05
| Broadwell-DT
| Broadwell-H<br />Broadwell-U<br />Broadwell-Y
| Broadwell-E
| Broadwell-EP<ref name="BroadwellEP" />
| Broadwell-EX<ref name="BroadwellEP">{{cite web|url=http://www.kitguru.net/components/cpu/anton-shilov/intel-to-release-22-core-xeon-e5-v4-broadwell-ep-late-in-2015-company/|title=Intel to release 22-core Xeon E5 v4 "Broadwell-EP" late in 2015 - KitGuru|website=www.kitguru.net}}</ref>
|-
| rowspan="8" | [[Skylake (microarchitecture)|Skylake]]{{Efn|Cascade Lake and Cooper Lake microprocessors have additional instructions that enable Intel Deep Learning Boost.|name=r_a}}
| [[Skylake (microarchitecture)|Skylake]]
| 6
| 1
| 2015-08-05<br/><ref>{{cite web|url=http://www.digitaltrends.com/computing/unlocked-intel-skylake-s-processors-reportedly-coming-august-5th/|title=The wait for Skylake is almost over, first desktop chips likely to hit August 5|date=6 July 2015}}</ref>
| Skylake-S
| Skylake-H<br />Skylake-U<br />Skylake-Y
| Skylake-X<ref name="auto">{{cite web|last1=Mujtaba|first1=Hassan|title=Intel X299 HEDT Platform For Skylake X and Kaby Lake X Processors Announcement on 30th May, Launch on 26th June – Reviews Go Live on 16th June|url=https://wccftech.com/intel-x299-hedt-skylake-x-kaby-lake-x-launch-26-june-nda/|website=wccftech.com|date=25 April 2017 |access-date=2 May 2017}}</ref><br />Skylake-W
| colspan="2" |Skylake-SP<br />(formerly Skylake-EP/-EX)<ref>{{cite web|last1=Windeck|first1=Christof|title=Intel Xeon Gold, Platinum: Skylake-SP für Server "Mitte Sommer"|url=https://www.heise.de/newsticker/meldung/Intel-Xeon-Gold-Platinum-Skylake-SP-fuer-Server-Mitte-Sommer-3700559.html|website=heise.de|access-date=2 May 2017}}</ref>
|-
| [[Kaby Lake|Kaby<br/>Lake]]
| 7 / 8
| rowspan="2" {{N/A}}
| 2016-10
| Kaby Lake-S
| Kaby Lake-G<br />Kaby Lake-H<br />Kaby Lake-U<br />Kaby Lake-Y
| Kaby Lake-X<br /><ref name="auto" />
| colspan="2" rowspan="2" {{N/A}}
|-
| [[Coffee Lake|Coffee<br/>Lake]]
| 8 / 9
| 2017-10<br /><ref>{{cite web|url=https://www.golem.de/news/coffee-lake-intels-6c-prozessoren-erfordern-neue-boards-1708-129594.html|title=Coffee Lake: Intels 6C-Prozessoren erfordern neue Boards - Golem.de}}</ref>
| {{nowrap|Coffee Lake-S}}
| {{nowrap|Coffee Lake-B}}<br />{{nowrap|Coffee Lake-H}}<br />{{nowrap|Coffee Lake-U}}
| [[Coffee Lake#Workstation processors|{{nowrap|Coffee Lake-W}}]]
|-
| [[Engineering:Whiskey Lake (microprocessor)|Whiskey<br/>Lake]]
| 8
| rowspan="2" {{N/A}}
| rowspan="2" | 2018-08-28
| rowspan="2" {{N/A}}
| {{nowrap|Whiskey Lake-U}}
| colspan="3" rowspan="2" {{N/A}}
|-
| Amber<br/>Lake
| 8 / 10
| {{nowrap|Amber Lake-Y}}
|-
|[[Engineering:Cascade Lake (microprocessor)|Cascade<br/>Lake]]
| {{N/A}}
| 2
| 2019-04-02
| colspan="2" {{N/A}}
| Cascade Lake-X<br />Cascade Lake-W<br />Cascade Lake-SP
| colspan="2" | Cascade Lake-SP
|-
| [[Engineering:Comet Lake|Comet<br/>Lake]]
| 10
| {{N/A}}
| 2019-09{{efn|name=r_b|retail availability}}
| {{nowrap|Comet Lake-S}}
| {{nowrap|Comet Lake-H}}<br />{{nowrap|Comet Lake-U}}<ref name=":4">{{cite web|url=https://www.heise.de/newsticker/meldung/Comet-Lake-U-15-Watt-CPUs-fuer-Notebook-CPUs-mit-sechs-Kernen-4501680.html|title=Comet Lake-U: 15-Watt-CPUs für Notebook-CPUs mit sechs Kernen|last=online|first=heise|website=c't Magazin|language=de|access-date=2019-08-21}}</ref><br />{{nowrap|Comet Lake-Y}}<ref name=":4" />
| [[Engineering:Comet Lake#Workstation processors|Comet Lake-W]]
| colspan="2" {{N/A}}
|-
| Cooper<br/>Lake
| {{N/A}}
| 3
| 2020-06
| colspan="4" {{N/A}}<ref>{{cite web|url=https://www.heise.de/newsticker/meldung/Intel-streicht-Cooper-Lake-Prozessoren-fuer-viele-Server-4684519.html|title=Intel streicht Cooper-Lake-Prozessoren für viele Server|trans-title=Intel is dropping Cooper Lake processors for many servers|website=heise online|language=de|access-date=2020-03-17}}</ref><ref>{{cite web|url=https://www.servethehome.com/intel-cooper-lake-rationalized-still-launching-1h-2020/|title=Intel Cooper Lake Rationalized Still Launching 1H 2020|last=Kennedy|first=Patrick|date=2020-03-16|website=ServeTheHome|language=en-US|access-date=2020-03-17}}</ref>
| Cooper Lake-SP
|-
| Cypress<br/>Cove<ref>{{cite web|title=Intel's 11th Gen Processor (Rocket Lake-S) Architecture Detailed|url=https://newsroom.intel.com/news/intels-11th-gen-processor-rocket-lake-s-architecture-detailed/|access-date=2020-10-29|website=Intel Newsroom|language=en-US}}</ref><ref>{{cite web|title=Intel "Rocket Lake-S": 11. Core-i-Generation mit mehr Rechenleistung pro Takt|url=https://www.heise.de/news/Intel-Rocket-Lake-S-11-Core-i-Generation-mit-mehr-Rechenleistung-pro-Takt-4942543.html|access-date=2020-10-29|website=heise online|language=de}}</ref>
| [[Engineering:Rocket Lake|Rocket<br/>Lake]]
| 11
| {{N/A}}
| 2021-03
| Rocket Lake-S
| {{N/A}}
| [[Engineering:Rocket Lake#Workstation processors|Rocket<br/>Lake]]
| colspan="2" {{N/A}}
|-
| rowspan="3" | [[Engineering:10 nm process|10 nm]]
| Palm<br/>Cove
| Cannon<br/>Lake
| 8
| {{N/A}}
| 2018-05{{efn|name=r_b|retail availability}}
| rowspan="3" {{N/A}}
| Cannon Lake-U
| colspan="3" {{N/A}}
|-
| Sunny<br/>Cove<ref name=":0">{{cite web|url=https://arstechnica.com/gadgets/2018/12/intel-unveils-a-new-architecture-for-2019-sunny-cove/|title=Intel unveils a new architecture for 2019: Sunny Cove|last=Bright|first=Peter|date=2018-12-12|website=Ars Technica|language=en-us|access-date=2018-12-12}}</ref>
| [[Engineering:Ice Lake (microprocessor)|Ice<br/>Lake]]
| 10
| 3
| 2019-09 <small>(mobile){{efn|name=r_b|retail availability}}</small><small><br></small>2021-04 <small>(server)</small>
| Ice Lake-U<ref name=":2">{{cite web|url=https://www.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html|title=Ice Lake Processor Family|website=Intel|language=en|access-date=2018-12-12}}</ref><br />Ice Lake-Y<ref name=":2" />
| Ice Lake-W
| Ice Lake-SP<ref>{{cite web|url=https://www.golem.de/news/server-cpus-cooper-lake-und-ice-lake-nutzen-gleichen-sockel-1808-135909.html|title=Server-CPUs: Cooper Lake und Ice Lake nutzen gleichen Sockel - Golem.de|website=www.golem.de|language=de-DE|access-date=2019-04-23}}</ref>
| {{N/A}}
|-
| Willow<br/>Cove
| [[Tiger Lake|Tiger<br/>Lake]]
| 11
| rowspan="2" {{N/A}}
| 2020-09
| Tiger Lake-H<br/>Tiger Lake-H35<br/>Tiger Lake-UP3<br/>Tiger Lake-UP4
| colspan="3" rowspan="2" {{N/A}}
|-
| rowspan="4" | Intel 7{{efn|name=r_c|Previously known as 10nm Enhanced Super Fin or 10ESF.<ref name=":5" />}}
| rowspan="2" | [[Engineering:Golden Cove|Golden<br/>Cove]]
| [[Engineering:Alder Lake|Alder<br/>Lake]]<br />(hybrid)
| 12
| 2021-11-04<ref name=":3" /><ref name=":1">{{cite web|title=Intels neuer Anlauf mit "Sunny Cove", Gen-11-GPU und Chiplets|url=https://www.heise.de/newsticker/meldung/Intels-neuer-Anlauf-mit-Sunny-Cove-Gen-11-GPU-und-Chiplets-4248713.html|access-date=2018-12-12|website=heise online|language=de}}</ref>
| Alder Lake-S
| Alder Lake-H<br/>Alder Lake-P<br/>Alder Lake-U
|-
| Sapphire<br/>Rapids<ref name="pirzada1"/>
| {{N/A}}
| 4
| 2023-01-10
| colspan="2" {{N/A}}
| Sapphire Rapids-WS
| colspan="2" | Sapphire Rapids-SP
|-
| rowspan="2" | Raptor<br/>Cove
| [[Engineering:Raptor Lake|Raptor<br/>Lake]]
| 13 / 14
| {{N/A}}
| 2022-10-20
| Raptor Lake-S
| Raptor Lake-HX<br />Raptor Lake-H<br />Raptor Lake-P<br />Raptor Lake-U
| colspan="3" {{N/A}}
|-
| [[Engineering:Emerald Rapids|Emerald<br/>Rapids]]
| {{N/A}}
| 5
| 2023-12-14
| colspan="2" {{N/A}}
| TBA
| colspan="2" | Emerald Rapids&ndash;SP
|-
| [[Engineering:5 nm process|Intel 4]]<ref name=":5" />
| Redwood<br/>Cove
| [[Engineering:Meteor Lake|Meteor<br/>Lake]]
| Core Ultra<br/>Series 1
| {{N/A}}
| 2023-12-14<ref>https://www.intel.com/content/www/us/en/newsroom/news/2023-intel-innovation-day-1-all-news.html</ref>
| N/A{{efn|name=r_d|Meteor Lake will appear in notebooks and [[Engineering:All-in-one computer|All-in-one computer]]s, but not in conventional desktop PCs.<ref>{{Cite web |last=Rißka |first=Volker |date=2023-09-26 |title=Für Notebooks & AIOs: Intel Meteor Lake kommt nicht für "klassische Desktop-PCs" |url=https://www.computerbase.de/2023-09/halbe-rolle-rueckwaerts-intel-meteor-lake-kommt-fuer-notebooks-und-aios/ |access-date=2023-09-27 |website=ComputerBase |language=de}}</ref>}}
| Meteor Lake-H<br/>Meteor Lake-U
| colspan="3" {{N/A}}
|-
| [[Engineering:3 nm process|Intel 3]]
| rowspan="4" | TBA
| Granite<br/>Rapids
| {{N/A}}
| 6
| 2024
| colspan="2" {{N/A}}
| TBA
| colspan="2" | Granite Rapids&ndash;SP
|-
| rowspan="2" | Intel 20A
| Arrow<br/>Lake<ref>{{cite news|title=Intel Client & Server CPU Roadmap Updates: Meteor Lake In 2023, 20A & 18A Powered Xeons & Core Chips Beyond 2024|url=https://wccftech.com/intel-client-server-cpu-roadmap-updates-meteor-lake-in-2023-20a-18a-powered-xeons-core-chips-beyond-2024/|access-date=2022-02-17|website=Wccftech|date=17 February 2022|last1=Mujtaba |first1=Hassan }}</ref>
| rowspan="3" | Core Ultra
| rowspan="3" {{N/A}}
| 2024
| colspan="2" | TBA
| colspan="3" rowspan="3" {{N/A}}
|-
| Lunar<br/>Lake
| 2024
| N/A
| TBA
|-
| Intel 18A
| Panther<br/>Lake
| 2025
| colspan="2" | TBA
|-
! rowspan="2" | [[Engineering:Semiconductor device fabrication|{{abbr|Fab|Fabrication}}<br />process]]
! rowspan="2" | Micro-<br />{{abbr|arch|architecture}}
! rowspan="2" | Code<br />names
! rowspan="2" | Core<br />{{abbr|gen|generation}}
! rowspan="2" | Xeon<br />Scalable<br />{{abbr|gen|generation}}
! rowspan="2" | Release<br />date
! Desktop
! Mobile
! Enthusiast<br />/<abbr title="Workstation">WS</abbr>
! 2P<br />Server/<abbr title="Workstation">WS</abbr>
! 4P/8P<br />Server
|-
! colspan="5" | Processors
|}
{{clear}}
{{notelist}}

{{Clear}}

=== Atom lines<ref name="atom-ticktock">{{cite web|title=Intel's Silvermont Architecture Revealed: Getting Serious About Mobile|url=http://www.anandtech.com/show/6936/intels-silvermont-architecture-revealed-getting-serious-about-mobile|website=[[AnandTech]]}}</ref> ===
{{anchor|atom-roadmap}}
{| class="wikitable mw-collapsible collapsible floatleft mw-datatable" style="margin:0.5em auto; text-align:center; min-width:80em;"
|+Atom roadmap
|-
! rowspan="2" | Fabri-<br/>cation<br/>process
! rowspan="2" | Micro-<br/>archi-<br/>tecture
! rowspan="2" | Release<br/>date
! colspan="8" | Processors/SoCs
|-
! <abbr title="Mobile Internet device">MID</abbr>, smartphone
! Tablet
! Netbook
! Nettop
! Embedded
! Server
! Communication
! <abbr title="Consumer Electronics">CE</abbr>
|-
| rowspan="2" | 45 nm
| rowspan="2" | [[Engineering:Bonnell (microarchitecture)|Bonnell]]
| <!-- April -->2008
| Silverthorne<!-- Menlow -->
| {{n/a}}
| colspan="2" | Diamondville
| rowspan="2" | Tunnel Creek,<br/>Stellarton
| rowspan="2" {{N/A}}
| rowspan="2" {{unk}}
| Sodaville
|-
| 2010
| colspan="2" | Lincroft<!-- Moorestown --><!-- Oak Trail -->
| colspan="2" | Pineview
| Groveland
|-
| 32 nm
| Saltwell
| <!-- November -->2011
| Medfield (Penwell & Lexington),<br/>Clover Trail+ (Cloverview) <!-- Clover Trail+ smartphones, see for example http://newsroom.intel.com/community/intel_newsroom/blog/2013/02/24/intel-accelerates-mobile-computing-push or http://www.tomshardware.com/reviews/atom-z2580-clover-trail-medfield,3446.html -->
| Clover Trail (Cloverview) <!-- Penwell is used in some tablets, see for example http://www.intel.com/content/www/us/en/education-solutions/tablets.html -->
| colspan="2" | Cedar Trail (Cedarview)
| {{unk}}
| Centerton & Briarwood
| {{unk}}
| Berryville
|-
| 22 nm
| [[Engineering:Silvermont|Silvermont]]
| 2013
| Merrifield (Tangier),<ref>{{cite web |last=Hiroshige |first=Goto |title=Intel Products for Tablets & SmartPhones |work=標準 |publisher=Impress |url=http://pc.watch.impress.co.jp/video/pcw/docs/569/575/p2.pdf |url-status=dead |archive-url=https://web.archive.org/web/20131114063059/http://pc.watch.impress.co.jp/video/pcw/docs/569/575/p2.pdf |archive-date=2013-11-14 }}</ref> Slayton,<br/>Moorefield (Anniedale)<ref>{{cite web |title=Import Data and Price of anniedale |url=https://www.zauba.com/import-anniedale-hs-code.html |access-date=2015-09-23 |archive-url=https://web.archive.org/web/20150517225042/https://www.zauba.com/import-anniedale-hs-code.html |archive-date=2015-05-17 |url-status=dead }}</ref>
| Bay Trail-T<br/>(Valleyview)
| Bay Trail-M<br/>(Valleyview)
| Bay Trail-D<br/>(Valleyview)
| Bay Trail-I<br/>(Valleyview)
| Avoton
| Rangeley
| {{unk}}
|-
| rowspan="3" | {{0}}14 nm<ref name="atom-ticktock" />
| Airmont
| 2014
| Binghamton & Riverton
| Cherry Trail-T (Cherryview)<ref>{{cite web |title=アウトオブオーダーと最新プロセスを採用する今後のAtom |date=30 November 2012|url=http://pc.watch.impress.co.jp/docs/column/ubiq/20121130_576105.html}}</ref>
| colspan="3" | Braswell<ref>{{cite web|title=Products (Formerly Braswell)|url=http://ark.intel.com/products/codename/66094/Braswell#@All|website=Intel ARK (Product Specs)|access-date=5 April 2016}}</ref>
| Denverton {{Cancelled}}
| {{unk}}
| {{unk}}
|-
| [[Engineering:Goldmont|Goldmont]]<br/><ref>{{cite news|last1=Smith|first1=Ryan|last2=Cutress|first2=Ian|title=Intel's Changing Future: Smartphone SoCs Broxton & SoFIA Officially Canceled|url=http://www.anandtech.com/show/10288/intel-broxton-sofia-smartphone-socs-cancelled|access-date=29 June 2016|publisher=Anandtech.com|date=29 April 2016}}</ref>
| 2016
| Broxton {{Cancelled}}
| Willow Trail {{Cancelled}}<br/>Apollo Lake
| colspan="3" | Apollo Lake<ref>{{cite web|title=Products (Formerly Apollo Lake)|url=http://ark.intel.com/products/codename/80644/Apollo-Lake|website=Intel ARK (Product Specs)|access-date=6 January 2016}}</ref>
| Denverton<ref>{{cite web|title=Products (Formerly Denverton)|url=https://ark.intel.com/products/codename/63508/Denverton|website=Intel ARK (Product Specs)|access-date=6 January 2016}}</ref>
| {{unk}}
| {{unk}}
|-
| [[Engineering:Goldmont Plus|Goldmont<br/>Plus]]<ref>{{cite web|url=https://www.anandtech.com/show/12146/intel-launches-gemini-lake-pentium-silver-and-celeron-socs-new-cpu-media-features|title=Intel Launches New Pentium Silver and Celeron Atom Processors: Gemini Lake is Here|first=Anton|last=Shilov|date=December 12, 2017|website=[[AnandTech]]}}</ref>
| 2017
| {{unk}}
| {{unk}}
| colspan="3" | Gemini Lake<ref>{{cite web|title=Products (Formerly Gemini Lake)|url=https://ark.intel.com/products/codename/83915/Gemini-Lake|website=Intel ARK (Product Specs)|access-date=11 December 2017}}</ref><br>Gemini Lake Refresh<ref>{{cite web|title=Products (Formerly Gemini Lake Refresh)|url=https://ark.intel.com/content/www/us/en/ark/products/codename/197862/gemini-lake-refresh.html|website=Intel ARK (Product Specs)|access-date=4 November 2019}}</ref>
| {{unk}}
| {{unk}}
| {{unk}}
|-
| [[Engineering:10 nm process|10 nm]]
| [[Engineering:Tremont (microarchitecture)|Tremont]]<ref name="the-tremont-core">{{cite web|url=https://www.anandtech.com/show/15009/intels-new-atom-microarchitecture-the-tremont-core|title=Intel's new Atom Microarchitecture: The Tremont Core in Lakefield|last=Cutress|first=Dr Ian|website=[[AnandTech]]|access-date=2019-11-17}}</ref>
| 2020
| {{unk}}
| Lakefield (hybrid)
| colspan="3" | Lakefield (hybrid)<ref>{{cite web|url=https://ark.intel.com/content/www/us/en/ark/products/codename/81657/lakefield.html|title=Products formerly Lakefield|website=Intel ARK (Product Specs)}}</ref><br> Elkhart Lake<ref>{{cite web|url=https://ark.intel.com/content/www/us/en/ark/products/codename/128825/elkhart-lake.html|title=Products formerly Elkhart Lake|website=Intel ARK (Product Specs)}}</ref><br> Jasper Lake <ref>{{cite web|url=https://ark.intel.com/content/www/us/en/ark/products/codename/128823/jasper-lake.html|title = Products formerly Jasper Lake}}</ref>
| Jacobsville<br> Parker Ridge<ref>{{cite web | url=https://ark.intel.com/content/www/us/en/ark/products/codename/229610/products-formerly-parker-ridge.html | title=Products formerly Parker Ridge }}</ref><br> Snow Ridge<ref>{{cite web|url=https://ark.intel.com/content/www/us/en/ark/products/codename/87586/snow-ridge.html|title=Products formerly Snow Ridge|website=Intel ARK (Product Specs)}}</ref>
| {{unk}}
| {{unk}}
|-
| Intel 7
| [[Engineering:Gracemont (microarchitecture)|Gracemont]]<ref>{{cite web|url=https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures/4|title = Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed}}</ref>
| 2021
| {{unk}}
| {{unk}}
| colspan="3" | [[Engineering:Alder Lake|Alder Lake]] (hybrid)<ref>{{cite web|url=https://ark.intel.com/content/www/us/en/ark/products/codename/147470/alder-lake.html|title=Products formerly Alder Lake|website=Intel ARK (Product Specs)}}</ref><br>[[Engineering:Raptor Lake|Raptor Lake]] (hybrid) <br> Alder Lake-N <ref>{{cite web | url=https://www.intel.com/content/www/us/en/newsroom/news/welcome-the-new-intel-processor.html | title=Intel Introduces New Intel Processor for Upcoming Essential Segment }}</ref><ref>{{cite web | url=https://ark.intel.com/content/www/us/en/ark/products/codename/232598/products-formerly-alder-laken.html | title=Products formerly Alder Lake-N }}</ref>
| {{unk}}
| {{unk}}
| {{unk}}
|-
| [[Engineering:5 nm process#4 nm process nodes|Intel 4]]
| Crestmont
| 2023
| {{unk}}
| {{unk}}
| colspan="3" | [[Engineering:Meteor Lake|Meteor Lake]] (hybrid)
| Grand Ridge
| {{unk}}
| {{unk}}
|-
| [[Engineering:3 nm process|Intel 3]]
| Crestmont
| 2024
| {{unk}}
| {{unk}}
| {{unk}}
| {{unk}}
| {{unk}}
| Sierra Forest-AP
| {{unk}}
| {{unk}}
|-
| Intel 20A
| Skymont
| 2024
| {{unk}}
| {{unk}}
| colspan="3" | Arrow Lake (hybrid)
| {{unk}}
| {{unk}}
| {{unk}}
|-
| Intel 18A
| Darkmont
| 2025
| {{unk}}
| {{unk}}
| {{unk}}
| {{unk}}
| {{unk}}
| Clearwater Forest-AP
| {{unk}}
| {{unk}}
|}

{{Clear}}

== See also ==
* [[Engineering:List of Intel processors|List of Intel processors]] - Consumer Computer or non-consumer workstation
* [[Engineering:List of AMD CPU microarchitectures|List of AMD CPU microarchitectures]]
* [[Engineering:XScale|Marvell Technology Group XScale microarchitecture]]
* [[Transient execution CPU vulnerability]]

== References ==
{{Reflist|colwidth=32em}}

== External links ==
* [http://ark.intel.com/ Intel Automated Relational Knowledgebase]

{{Intel processors}}

[[Category:Intel microprocessors]]
[[Category:Lists of microprocessors|Intel CPU microarchitectures]]
[[Category:Intel microarchitectures]]

{{Sourceattribution|List of Intel CPU microarchitectures}}