View source for Engineering:NetBurst (microarchitecture)

{{short description|Intel processor microarchitecture}}
{{Infobox CPU
| name = NetBurst
| image = 
| image_size = 
| created = {{start date and age|November 20, 2000}}
| model = Celeron Series
| model1 = Celeron D Series
| model2 = Pentium 4 Series
| model3 = Pentium D Series
| model4 = Xeon Series
| cores = 1-2 (2-4 threads with HT)
| cores1 = 
| transistors = 42M 180 nm (B2, C1, D0, E0)
| transistors1 = 55M 130 nm (B0, C1, D1, M0)
| transistors2 = 125M 90 nm (C0, D0, E0, G1)
| transistors3 = 169M 90 nm (M0, N0, R0)
| transistors4 = 230M 90 nm (A0, B0)
| transistors5 = 188M 65 nm (B1, C1, D0)
| transistors6 = 376M 65 nm (B1, C1, D0)
| transistors7 = 1,328M 65 nm (B0)
| clock = 1.3&nbsp;GHz to 3.8&nbsp;GHz
| l1cache = 8 KB to 16 KB per core
| l2cache = 128 KB to 2048 KB
| l3cache = 4 MB to 16 MB shared 
| fsb = 400 MT/s to 1066 MT/s
| arch1 = NetBurst [[X86|x86]]
| instructions = [[X86|x86]], [[X86-64|x86-64]] (some)
| extensions = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]]&nbsp;(some)
| sock1 = Socket 423
| sock2 = Socket 478 
| sock3 = Socket 603
| sock4 = Socket 604
| sock5 = LGA 771
| sock6 = LGA 775
| predecessor = [[Engineering:P6 (microarchitecture)|P6]]
| successor = [[Engineering:Intel Core (microarchitecture)|Intel Core]]<br/>[[Engineering:IA-64|IA-64]]
}}

The '''NetBurst microarchitecture''',<ref>{{cite web|url=https://pdfs.semanticscholar.org/presentation/cfcc/9d5a7480c4ea87e77084386d74aaff9a1ee1.pdf|title=The Intel Pentium 4 Processor|first=Doug|last=Carmean|date=Spring 2002|publisher=[[Company:Intel|Intel]]|archive-url=https://web.archive.org/web/20180419120455/https://pdfs.semanticscholar.org/presentation/cfcc/9d5a7480c4ea87e77084386d74aaff9a1ee1.pdf|archive-date=April 19, 2018}}</ref><ref>{{Cite web|url=http://www.xbitlabs.com/articles/cpu/print/replay.html|title=Replay: Unknown Features of the NetBurst Core|date=March 6, 2016|website=XbitLabs|archive-url=https://web.archive.org/web/20160306140603/http://www.xbitlabs.com/articles/cpu/print/replay.html|archive-date=March 6, 2016}}</ref> called '''P68''' inside [[Company:Intel|Intel]], was the successor to the [[Engineering:P6 (microarchitecture)|P6 microarchitecture]] in the [[X86|x86]] family of [[Central processing unit|central processing unit]]s (CPUs) made by Intel. The first CPU to use this architecture was the [[Engineering:Pentium 4#Willamette|Willamette-core Pentium 4]], released on November 20, 2000 and the first of the [[Engineering:Pentium 4|Pentium 4]] CPUs; all subsequent Pentium 4 and [[Engineering:Pentium D|Pentium D]] variants have also been based on NetBurst. In mid-2004, Intel released the ''Foster'' core, which was also based on NetBurst, thus switching the [[Engineering:Xeon|Xeon]] CPUs to the new architecture as well. Pentium 4-based [[Engineering:Celeron|Celeron]] CPUs also use the NetBurst architecture.

NetBurst was replaced with the [[Engineering:Intel Core (microarchitecture)|Core microarchitecture]] based on P6, released in July 2006.

== Technology ==
The NetBurst microarchitecture includes features such as [[Hyper-threading]], Hyper Pipelined Technology, Rapid Execution Engine, Execution Trace Cache, and replay system which all were introduced for the first time in this particular microarchitecture, and some never appeared again afterwards.

===Hyper-threading===
{{Main|Hyper-threading}}
Hyper-threading is Intel's proprietary [[Simultaneous multithreading|simultaneous multithreading]] (SMT) implementation used to improve parallelization of computations (doing multiple tasks at once) performed on x86 processors. Intel introduced it with NetBurst processors in 2002. Later Intel reintroduced it in the [[Engineering:Nehalem (microarchitecture)|Nehalem microarchitecture]] after its absence in the Core 2.

=== Quad-Pumped Front-Side Bus ===
The Northwood and Willamette cores feature an external Front Side Bus (FSB) that runs at 100&nbsp;MHz which transfers four bits per clock cycle, thus having an effective speed of 400 MHz. Later revisions of the Northwood core, along with the Prescott core ([[Engineering:Pentium D|and derivatives]]) have an effective 800&nbsp;MHz front-side bus (200 MHz quad pumped). [https://arstechnica.com/uncategorized/2004/07/ask-ars-20040710/]

=== Hyper-Pipelined Technology ===
The Wilamette and Northwood cores contain a 20-stage [[Instruction pipelining|instruction pipeline]]. This is a significant increase in the number of stages compared to the Pentium III, which had only 10 stages in its pipeline. The Prescott core increased the length of the pipeline to 31 stages. A drawback of longer pipelines is the increase in the number of stages that need to be traced back in the event that the branch misprediction, increasing the penalty of said misprediction. To address this issue, Intel devised the Rapid Execution Engine and has invested a great deal into its branch prediction technology, which Intel claims reduces [[Branch misprediction|branch misprediction]]s by 33% over [[Engineering:Pentium III|Pentium III]].<ref>{{cite web|date=November 20, 2000|title=The Trace Cache Branch Prediction Unit|url=https://www.tomshardware.com/reviews/intel,264-8.html|access-date=April 30, 2021|work=Intel's New Pentium 4 Processor|publisher=[[Tom's Hardware]]}}</ref> In reality, the longer pipeline resulted in reduced efficiency through a lower number of [[Instructions per cycle|instructions per clock]] (IPC) executed as high enough clock speeds were not able to be reached to offset lost performance due to larger than expected increase in power consumption and heat.

=== Rapid Execution Engine ===
With this technology, the two [[Arithmetic logic unit|arithmetic logic unit]]s (ALUs) in the core of the CPU are double-pumped, meaning that they actually operate at twice the core clock frequency. For example, in a 3.8&nbsp;GHz processor, the ALUs will effectively be operating at 7.6&nbsp;GHz. The reason behind this is to generally make up for the low IPC count; additionally this considerably enhances the integer performance of the CPU. Intel also replaced the high-speed [[Barrel shifter|barrel shifter]] with a shift/rotate execution unit that operates at the same frequency as the CPU core. The downside is that certain instructions are now much slower (relatively and absolutely) than before, making optimization for multiple target CPUs difficult. An example is shift and rotate operations, which suffer from the lack of a barrel shifter which was present on every x86 CPU beginning with the i386, including the main competitor processor, [[Engineering:Athlon|Athlon]].

=== Execution Trace Cache ===
{{Main|Trace cache}}
Within the L1 cache of the CPU, Intel incorporated its Execution Trace Cache. It stores decoded [[Micro-operation|micro-operation]]s, so that when executing a new instruction, instead of fetching and decoding the instruction again, the CPU directly accesses the decoded micro-ops from the trace cache, thereby saving considerable time. Moreover, the micro-ops are cached in their predicted path of execution, which means that when instructions are fetched by the CPU from the cache, they are already present in the correct order of execution.<ref>{{cite web |url=https://www.tomshardware.com/reviews/intel,264-6.html |title=Entering The Execution Pipeline - Pentium 4's Trace Cache, Continued |work=Intel's New Pentium 4 Processor |publisher=[[Tom's Hardware]] |date=November 20, 2000 |access-date=April 30, 2021}}</ref> Intel later introduced a similar but simpler concept with [[Engineering:Sandy Bridge|Sandy Bridge]] called micro-operation cache (UOP cache).

=== Replay system ===
The replay system is a subsystem within the Intel Pentium 4 processor to catch operations that have been mistakenly sent for execution by the processor's scheduler. Operations caught by the replay system are then re-executed in a loop until the conditions necessary for their proper execution have been fulfilled.

=== Branch prediction hints ===
The Intel NetBurst architecture allows branch prediction hints to be inserted into the code to tell whether the static prediction should be taken or not taken, while this feature was abandoned in later Intel processors. According to Intel, NetBurst's branch prediction algorithm is 33% better than the one in P6.<ref name=Fog_Microarchitecture>{{cite web | last = Fog | first = Agner | title = The microarchitecture of Intel, AMD and VIA CPUs | date = December 1, 2016  | url = http://www.agner.org/optimize/microarchitecture.pdf | pages = 36 | access-date = March 22, 2017}}</ref><ref name="urlwww.ece.uah.edu">{{cite web |url=http://www.ece.uah.edu/~milenka/docs/milenkovic_WDDD02.pdf |title=Demystifying Intel Branch Predictors |first1=Milena |last1=Milenkovic |first2=Aleksandar |last2=Milenkovic |first3=Jeffrey |last3=Kulick}}</ref>

== Scaling-up issues ==
Despite these enhancements, the NetBurst architecture created obstacles for engineers trying to scale up its performance. With this microarchitecture, Intel looked to attain clock speeds of 10&nbsp;GHz,<ref>{{Cite news|url=https://www.anandtech.com/show/680/6|title=The future of Intel's manufacturing processes|last=Shimpi|first=Anand Lal|access-date=April 4, 2018}}</ref> but because of rising clock speeds, Intel faced increasing problems with keeping power dissipation within acceptable limits. Intel reached a speed barrier of 3.8&nbsp;GHz in November 2004 but encountered problems trying to achieve even that. Intel abandoned NetBurst in 2006 after the heat problems became unacceptable and then developed the Core microarchitecture, inspired by the P6 Core of the [[Engineering:Pentium Pro|Pentium Pro]] to the ''Tualatin'' [[Engineering:Pentium III|Pentium III]]-S, and most directly the [[Engineering:Pentium M|Pentium M]].

== Revisions ==
{{Main|Engineering:Pentium 4}}

{| class="wikitable" style="float: right; margin-left: 1.5em; margin-right: 0; margin-top: 0;"
|-
! Revision
! Processor Brand(s)
! Pipeline stages
|-
| Willamette (180&nbsp;nm)
| Celeron, Pentium 4
| 20
|-
| Northwood (130&nbsp;nm)
| Celeron, Pentium 4, Pentium 4 HT
| 20
|-
| Gallatin (130&nbsp;nm)
| Pentium 4 HT Extreme Edition, Xeon
| 20
|-
| Prescott (90&nbsp;nm)
| Celeron D, Pentium 4, Pentium 4 HT,<br />Pentium 4 Extreme Edition
| 31
|-
| Cedar Mill (65&nbsp;nm)
| Celeron D, Pentium 4
| 31
|-
| Smithfield (90&nbsp;nm)
| Pentium D
| 31
|-
| Presler (65&nbsp;nm)
| Pentium D 
| 31
|}
Intel replaced the original ''Willamette'' core with a redesigned version of the NetBurst microarchitecture called ''Northwood'' in January 2002. The ''Northwood'' design combined an increased cache size, a smaller 130&nbsp;nm fabrication process, and [[Hyper-threading]] (although initially all models but the 3.06&nbsp;GHz model had this feature disabled) to produce a more modern, higher-performing version of the NetBurst microarchitecture.

In February 2004, Intel introduced '''''Prescott''''', a more radical revision of the microarchitecture. The ''Prescott'' core was produced on a 90&nbsp;nm process, and included several major design changes, including the addition of an even larger cache (from 512 KB in the ''Northwood'' to 1 MB, and 2 MB in Prescott 2M), a much deeper instruction pipeline (31 stages as compared to 20 in the ''Northwood''), a heavily improved [[Branch predictor|branch predictor]], the introduction of the [[SSE3]] instructions, and later, the implementation of Intel 64, Intel's branding for their compatible implementation of the [[X86-64|x86-64]] 64-bit version of the [[X86|x86]] microarchitecture (as with hyper-threading, all ''Prescott'' chips branded Pentium 4 HT have hardware to support this feature, but it was initially only enabled on the high-end [[Engineering:Xeon|Xeon]] processors, before being officially introduced in processors with the [[Engineering:Pentium|Pentium]] trademark). Power consumption and heat dissipation also became major issues with ''Prescott'', which quickly became the hottest-running, and most power-hungry, of Intel's single-core x86 and x86-64 processors. Power and heat concerns prevented Intel from releasing a Prescott clocked above 3.8&nbsp;GHz, along with a mobile version of the core clocked above 3.46&nbsp;GHz.

Intel also released a dual-core processor based on the NetBurst microarchitecture branded Pentium D. The first Pentium D core was codenamed ''Smithfield'', which is actually two Prescott cores in a single die, and later ''Presler'', which consists of two ''Cedar Mill'' cores on two separate dies (''Cedar Mill'' being the 65&nbsp;nm die-shrink of ''Prescott'').

== Roadmap ==

== Successor {{anchor|Future}} ==
Intel had Netburst-based successors in development called [[Engineering:Tejas and Jayhawk|Tejas and Jayhawk]] with between 40 and 50 pipeline stages, but ultimately decided to replace NetBurst with the Core microarchitecture,<ref>{{Cite web|url=https://www.theregister.com/2004/05/07/intel_kills_tejas/|title=Intel says Adios to Tejas and Jayhawk chips|website=The Register}}</ref><ref>{{cite web |last1=Goodwins |first1=Rupert |title=Intel cancels Tejas and Jayhawk |url=https://www.zdnet.com/article/intel-cancels-tejas-and-jayhawk/ |website=ZDNet |access-date=21 August 2019 |language=en}}</ref> released in July 2006; these successors were more directly derived from the [[Engineering:Pentium Pro|Pentium Pro]] ([[Engineering:P6 (microarchitecture)|P6 microarchitecture]]). August 8, 2008 marked the end of Intel NetBurst-based processors.<ref>{{Cite web |url=http://www.xbitlabs.com/news/cpu/display/20070521145938.html |title=The Era of Intel's NetBurst Micro-Architecture Comes to End. |first=Anton |last=Shilov |date=May 21, 2007 |website=XbitLabs |access-date=November 29, 2015 |archive-url=https://web.archive.org/web/20151017144944/http://www.xbitlabs.com/news/cpu/display/20070521145938.html |archive-date=October 17, 2015 |url-status=dead}}</ref> The reason for NetBurst's abandonment was the severe heat problems caused by high clock speeds. While some Core- and Nehalem-based processors have higher [[Thermal design power|TDP]]s, most processors are multi-core, so each core gives off a fraction of the maximum TDP, and the highest-clocked Core-based single-core processors give off a maximum of 27 W of heat. The fastest-clocked desktop Pentium 4 processors (single-core) had TDPs of 115 W, compared to 88 W for the fastest clocked mobile versions. Although, with the introduction of new steppings, TDPs for some models were eventually lowered.

The Nehalem microarchitecture, the successor to the Core microarchitecture, was supposed to be an evolution of NetBurst according to Intel roadmaps dating back to 2000.{{citation needed|date=October 2021}} Nehalem reimplements certain features of NetBurst, including the Hyper-Threading technology first introduced in the 3.06&nbsp;GHz ''Northwood'' core, and L3 cache, first implemented on a consumer processor in the ''Gallatin'' core used in the Pentium 4 Extreme Edition.

== NetBurst-based chips ==
{{Div col|colwidth=25em}}
* [[Engineering:Celeron#NetBurst-based Celerons|Celeron (NetBurst)]]
* [[Engineering:Celeron#Prescott-256|Celeron D]]
* [[Engineering:Pentium 4|Pentium 4]]
* [[Engineering:Pentium 4#Gallatin (Extreme Edition)|Pentium 4 Extreme Edition]]
* [[Engineering:Pentium D|Pentium D]]
* [[Engineering:Pentium D#Pentium D.2FExtreme Edition|Pentium Extreme Edition]]
* [[Engineering:Xeon|Xeon]], from 2001 through 2006
{{div col end}}

== See also ==
* [[Megahertz myth]]
* [[Engineering:List of Intel CPU microarchitectures|List of Intel CPU microarchitectures]]
* [[Engineering:List of Intel Celeron processors#Netburst based Celerons|List of Intel Celeron processors (NetBurst-based)]]
* [[Engineering:List of Intel Pentium 4 processors|List of Intel Pentium 4 processors]]
* [[Engineering:List of Intel Pentium D processors|List of Intel Pentium D processors]]
* [[Engineering:List of Intel Xeon processors (NetBurst-based)|List of Intel Xeon processors (NetBurst-based)]]
* [[Engineering:Tick–tock model|Tick–tock model]]

== References ==
{{Reflist}}

== External links ==
* [http://www.ecs.umass.edu/ece/koren/ece568/papers/Pentium4.pdf The Microarchitecture of the Pentium 4 Processor]

{{Intel processors|netburst}}

[[Category:Intel x86 microprocessors]]
[[Category:Intel microarchitectures]]

{{Sourceattribution|NetBurst (microarchitecture)|1}}