View source for Engineering:Network interface controller

{{Infobox Computer Hardware Generic
| name        = Network interface controller
| image       = Network card.jpg
| caption     = A 1990s [[Ethernet]] network interface card that connects to the motherboard via the now-obsolete ISA bus. This combination card features both a [[Engineering:BNC connector|BNC connector]] (left) for use in (now obsolete) [[10BASE2|10BASE2]] networks and an 8P8C connector (right) for use in [[10BASE-T|10BASE-T]] networks.
| invent-date =
| invent-name =
| conn1       = [[Engineering:Motherboard|Motherboard]]
| via1_1      = integrated in [[Engineering:Chipset|chipset]] or [[System on a chip|SoC]]
| via1_2      = [[Engineering:Motherboard#Integrated peripherals|discrete onboard]]
| via1_3      = [[Engineering:Peripheral Component Interconnect|PCI]] Connector
| via1_4      = [[Engineering:Industry Standard Architecture|ISA]] Connector
| via1_5      = PCIe (including Mini PCIe and [[Engineering:M.2|M.2]])
| via1_6      = FireWire
| via1_7      = [[Engineering:USB|USB]]
| via1_8      = [[Engineering:Thunderbolt (interface)|Thunderbolt]]
| conn2       = Network
| via2_1      = [[Ethernet]]
| via2_2      = [[Wi-Fi]]
| via2_3      = [[Engineering:Fibre Channel|Fibre Channel]]
| via2_4      = [[Asynchronous Transfer Mode|ATM]]
| via2_5      = FDDI
| via2_6      = [[Token Ring]]
| via2_7      = [[ARCNET]]
| class-name  = Speeds
| class1      = Full-duplex or half-duplex:
| class2 = {{bulleted list|10 Mbit/s|100 Mbit/s|1 Gbit/s}}
| class3 = Full-duplex:<ref>{{Cite web|title=Port speed and duplex mode configuration|url=http://docs.ruckuswireless.com/fastiron/08.0.70/fastiron-08070-managementguide/GUID-EDD7D44C-A627-4B76-A9FE-D7657FFF62D3.html|access-date=2020-09-25|website=docs.ruckuswireless.com|language=en-US}}</ref><ref>{{Cite web|last=Admin|first=Arista|date=2020-04-23|title=Section 11.2: Ethernet Standards - Arista|url=https://www.arista.com/en/um-eos/eos-section-11-2-ethernet-standards|access-date=2020-09-28|website=Arista Networks|language=en-gb}}</ref>
| class4      = {{bulleted list|2.5 Gbit/s|5 Gbit/s|10 Gbit/s|up to {{nowrap|160 Gbit/s}}}}
| manuf1      = [[Company:Intel|Intel]]
| manuf2      = [[Company:Realtek|Realtek]]
| manuf3      = [[Company:Broadcom|Broadcom]] (includes former Avago, [[Company:Emulex|Emulex]])
| manuf4      = [[Company:Marvell Technology Group|Marvell Technology Group]]
| manuf5      = [[Company:Cavium|Cavium]] (formerly [[Company:QLogic|QLogic]])
| manuf6      = Mellanox
| manuf7      = Chelsio
}}

A '''network interface controller''' ('''NIC''',<!--"Controller" is correct; once upon a time, they might all have been add-in cards, and called "network interface cards", but most of them are probably on the motherboard or in the SoC these days.--> also known as a '''network interface card''',<ref name="Dell"/> '''network adapter''', '''LAN adapter''' and '''physical network interface'''<ref>{{cite web|url=https://technet.microsoft.com/en-us/library/dd392944(v=ws.10).aspx|title=Physical Network Interface|publisher=[[Company:Microsoft|Microsoft]]|date=January 7, 2009}}</ref>) is a [[Computer hardware|computer hardware]] component that connects a [[Computer|computer]] to a [[Computer network|computer network]].<ref name=networking_01>{{cite web
|url         = http://www.windowsnetworking.com/articles_tutorials/networking-basics-part1.html
|title       = Networking Basics: Part 1 - Networking Hardware
|author      = Posey, Brien M.
|year        = 2006
|work        = Windowsnetworking.com
|publisher   = TechGenix Ltd
|access-date  = 2012-06-09
}}</ref>

Early network interface controllers were commonly implemented on [[Engineering:Expansion card|expansion card]]s that plugged into a computer bus. The low cost and ubiquity of the [[Ethernet]] standard means that most newer computers have a network interface built into the [[Engineering:Motherboard|motherboard]], or is contained into a [[Engineering:USB|USB]]-connected [[Engineering:Dongle|dongle]], although network cards remain available.

Modern network interface controllers offer advanced features such as [[Interrupt|interrupt]] and [[Direct memory access|DMA]] interfaces to the host processors, support for multiple receive and transmit queues, partitioning into multiple logical interfaces, and on-controller network traffic processing such as the [[TCP offload engine]].

== Purpose ==
The network controller implements the electronic circuitry required to communicate using a specific [[Physical layer|physical layer]] and [[Data link layer|data link layer]] standard such as [[Ethernet]] or [[Wi-Fi]].{{efn|Although other network technologies exist, Ethernet ([[IEEE 802.3]]) and Wi-Fi ([[IEEE 802.11]]) have achieved near-ubiquity as LAN technologies since the mid-1990s.}} This provides a base for a full network [[Protocol stack|protocol stack]], allowing communication among computers on the same [[Engineering:Local area network|local area network]] (LAN) and large-scale network communications through routable protocols, such as [[Internet Protocol]] (IP).

The NIC allows computers to communicate over a computer network, either by using cables or wirelessly. The NIC is both a physical layer and data link layer device, as it provides physical access to a networking medium and, for [[IEEE 802]] and similar networks, provides a low-level addressing system through the use of [[MAC address]]es that are uniquely assigned to network interfaces.

== Implementation ==
[[File:12 early PC network cards.jpg|thumb|12 early ISA 8 bit and 16 bit PC network cards. The lower right-most card is an early wireless network card, and the central card with partial beige plastic cover is a PSTN [[modem]].]]
[[File:Intel Ophir 82571 Dual Port Gigabit Ethernet Controller Die Shot.png|thumb|Intel Ophir 82571 dual-port Gigabit Ethernet controller [[Die (integrated circuit)|die]]]]
Network controllers were originally implemented as expansion cards that plugged into a computer bus. The low cost and ubiquity of the Ethernet standard means that most new computers have a network interface controller built into the motherboard. Newer [[Server (computing)|server]] motherboards may have multiple network interfaces built-in. The Ethernet capabilities are either [[Engineering:Integrated circuit|integrated]] into the motherboard [[Engineering:Chipset|chipset]] or implemented via a low-cost dedicated Ethernet chip. A separate network card is typically no longer required unless additional independent network connections are needed or some non-Ethernet type of network is used. A general trend in computer hardware is towards [[System on a chip|integrating the various components of systems on a chip]], and this is also applied to network interface cards.

An Ethernet network controller typically has an 8P8C socket where the network cable is connected. Older NICs also supplied [[Engineering:BNC connector|BNC]], or [[Attachment Unit Interface|AUI]] connections. Ethernet network controllers typically support {{val|10|ul=Mbit/s}} Ethernet, [[Fast Ethernet|{{nowrap|100 Mbit/s}} Ethernet]], and [[Gigabit Ethernet|{{nowrap|1000 Mbit/s}} Ethernet]] varieties. Such controllers are designated as ''10/100/1000'', meaning that they can support data rates of 10, 100 or {{nowrap|1000 Mbit/s}}. [[10 Gigabit Ethernet|10 Gigabit Ethernet]] NICs are also available, and, {{As of|2014|11|lc=yes}}, are beginning to be available on computer motherboards.<ref>{{cite web |url=http://www.networkcomputing.com/networking/will-2014-be-the--year-of-10-gigabit-ethernet/a/d-id/1234640 |title=Will 2014 Be The Year Of 10 Gigabit Ethernet? |author=Jim O'Reilly |publisher=Network Computing |date=2014-01-22 |access-date=2015-04-29 |archive-date=2015-05-10 |archive-url=https://web.archive.org/web/20150510043419/http://www.networkcomputing.com/networking/will-2014-be-the--year-of-10-gigabit-ethernet/a/d-id/1234640 |url-status=dead }}</ref><ref>{{cite web |url=http://www.asrock.com/news/index.asp?id=2517 |title=Breaking Speed Limits with ASRock X99 WS-E/10G and Intel 10G BASE-T LANs |website=asrock.com |date=24 November 2014 |access-date=19 May 2015}}</ref>

[[File:Qle3442-cu 10gbe nic.jpg|thumb|A [[Qlogic]] QLE3442-CU SFP+ dual-port NIC]]
Modular designs like [[Small Form-factor Pluggable|SFP and SFP+]] are highly popular, especially for [[Physics:Fiber-optic communication|fiber-optic communication]]. These define a standard receptacle for media-dependent transceivers, so users can easily adapt the network interface to their needs.

[[Engineering:LED|LED]]s adjacent to or integrated into the network connector inform the user of whether the network is connected, and when data activity occurs.

The NIC may include ROM to store its factory-assigned [[MAC address]].<ref>{{cite web |url=https://www.itprotoday.com/cloud-computing/how-can-i-change-network-adapter-cards-mac-address |title=How can I change a network adapter card's MAC address? |author=John Savill |date=Nov 12, 2000 |access-date=2023-11-06}}</ref>

The NIC may use one or more of the following techniques to indicate the availability of packets to transfer:
* [[Polling (computer science)|Polling]] is where the CPU examines the status of the [[Engineering:Peripheral|peripheral]] under program control.
* [[Interrupt request|Interrupt]]-driven I/O is where the peripheral alerts the CPU that it is ready to transfer data.

NICs may use one or more of the following techniques to transfer packet data:
* Programmed input/output, where the CPU moves the data to or from the NIC to memory.
* [[Direct memory access]] (DMA), where a device other than the CPU assumes control of the [[Engineering:System bus|system bus]] to move data to or from the NIC to memory. This removes load from the CPU but requires more logic on the card. In addition, a packet buffer on the NIC may not be required and [[Engineering:Latency (engineering)|latency]] can be reduced.

== {{Anchor|RSS|XPS|MULTIQUEUE|NPAR|FLOW-DIRECTOR}}Performance and advanced functionality ==
[[File:ForeRunnerLE 25 ATM Network Interface (1).jpg|thumb|right|An [[Asynchronous Transfer Mode]] (ATM) network interface]]
[[File:An Intel 82574L Gigabit Ethernet NIC, PCI Express x1 card.jpg|thumb|right|[[Company:Intel|Intel]] 82574L [[Gigabit Ethernet]] NIC, a PCI Express ×1 card, which provides two hardware receive queues<ref>{{cite web
 | url = http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
 | title = Intel 82574 Gigabit Ethernet Controller Family Datasheet
 | date = June 2014 | access-date = November 16, 2014
 | publisher = [[Company:Intel|Intel]] | page = 1
}}</ref>]]

'''Multiqueue NICs''' provide multiple transmit and receive [[Queue (abstract data type)|queues]], allowing packets received by the NIC to be assigned to one of its receive queues. The NIC may distribute incoming traffic between the receive queues using a [[Hash function|hash function]]. Each receive queue is assigned to a separate [[Interrupt|interrupt]]; by routing each of those interrupts to different CPUs or [[Multi-core processor|CPU cores]], processing of the interrupt requests triggered by the network traffic received by a single NIC can be distributed improving performance.<ref name="linux-net-scaling">{{cite web
 | url = https://www.kernel.org/doc/Documentation/networking/scaling.txt
 | title = Linux kernel documentation: Documentation/networking/scaling.txt
 | date = May 9, 2014 | access-date = November 16, 2014
 | author1 = Tom Herbert | author2 = Willem de Bruijn
 | publisher = [[Software:Kernel.org|kernel.org]]
}}</ref><ref>{{cite web
 | url = http://www.mouser.com/pdfdocs/i210brief.pdf
 | title = Intel Ethernet Controller i210 Family Product Brief
 | year = 2012 | access-date = November 16, 2014
 | publisher = [[Company:Intel|Intel]] }}</ref>

The hardware-based distribution of the interrupts, described above, is referred to as receive-side scaling (RSS).<ref name="intel-grantley">{{cite web
 | url = http://www.intel.com/content/dam/technology-provider/secure/us/en/documents/product-marketing-information/tst-grantley-launch-presentation-2014.pdf
 | title = Intel Look Inside: Intel Ethernet
 | work = Xeon E5 v3 (Grantley) Launch
 | date = November 27, 2014 | access-date = March 26, 2015
 | publisher = [[Company:Intel|Intel]]
 | archive-url = https://web.archive.org/web/20150326095816/http://www.intel.com/content/dam/technology-provider/secure/us/en/documents/product-marketing-information/tst-grantley-launch-presentation-2014.pdf
 | archive-date = March 26, 2015
}}</ref>{{rp|82}} Purely software implementations also exist, such as the receive packet steering (RPS), receive flow steering (RFS),<ref name="linux-net-scaling" /> and [[Company:Intel|Intel]] ''Flow Director''.<ref name="intel-grantley" />{{rp|98,99}}<ref>{{cite web
 | url = https://www.kernel.org/doc/Documentation/networking/ixgbe.txt
 | title = Linux kernel documentation: Documentation/networking/ixgbe.txt
 | date = December 15, 2014 | access-date = March 26, 2015
 | publisher = [[Software:Kernel.org|kernel.org]]
}}</ref><ref>{{cite web
 | url = http://www.intel.com/content/www/us/en/ethernet-controllers/ethernet-flow-director-video.html
 | title = Intel Ethernet Flow Director
 | date = February 16, 2015 | access-date = March 26, 2015
 | publisher = [[Company:Intel|Intel]]
}}</ref><ref>{{cite web
 | url = http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/intel-ethernet-flow-director.pdf
 | title = Introduction to Intel Ethernet Flow Director and Memcached Performance
 | date = October 14, 2014 | access-date = October 11, 2015
 | publisher = [[Company:Intel|Intel]] }}</ref> Further performance improvements can be achieved by routing the interrupt requests to the CPUs or cores executing the applications that are the ultimate destinations for [[Network packet|network packet]]s that generated the interrupts. This technique improves [[Locality of reference|locality of reference]] and results in higher overall performance, reduced latency and better hardware utilization because of the higher utilization of [[CPU cache]]s and fewer required [[Context switch|context switch]]es.

With multi-queue NICs, additional performance improvements can be achieved by distributing outgoing traffic among different transmit queues. By assigning different transmit queues to different CPUs or CPU cores, internal operating system contentions can be avoided. This approach is usually referred to as '''transmit packet steering''' (XPS).<ref name="linux-net-scaling" />

Some products feature '''NIC partitioning''' ('''NPAR''', also known as '''port partitioning''') that uses SR-IOV virtualization to divide a single 10 Gigabit Ethernet NIC into multiple discrete virtual NICs with dedicated bandwidth, which are presented to the firmware and operating system as separate PCI device functions.<ref name="Dell">{{cite web
 | url = http://www.dell.com/downloads/global/products/pedge/en/Dell-Broadcom-NPAR-White-Paper.pdf
 | title = Enhancing Scalability Through Network Interface Card Partitioning
 | date = April 2011 | access-date = May 12, 2014
 | publisher = [[Company:Dell|Dell]] }}</ref><ref>{{cite web
 | url = http://www.intel.com/content/dam/www/public/us/en/documents/solution-briefs/10-gbe-ethernet-flexible-port-partitioning-brief.pdf
 | title = An Introduction to Intel Flexible Port Partitioning Using SR-IOV Technology
 | date = September 2011 | access-date = September 24, 2015
 | author1 = Patrick Kutch | author2 = Brian Johnson | author3 = Greg Rose
 | publisher = [[Company:Intel|Intel]] }}</ref>

Some NICs provide a [[TCP offload engine]] to offload processing of the entire TCP/IP stack to the network controller. It is primarily used with high-speed network interfaces, such as Gigabit Ethernet and 10 Gigabit Ethernet, for which the processing overhead of the network stack becomes significant.<ref>{{cite web
 | url = https://lwn.net/Articles/243949/
 | title = Large receive offload
 | date = August 1, 2007 | access-date = May 2, 2015
 | author = Jonathan Corbet | publisher = LWN.net
}}</ref>

{{Anchor|SOLARFLARE|OPENONLOAD|USER-LEVEL-NETWORKING}}
Some NICs offer integrated [[Engineering:Field-programmable gate array|field-programmable gate array]]s (FPGAs) for user-programmable processing of network traffic before it reaches the host computer, allowing for significantly reduced [[Engineering:Latency (engineering)|latencies]] in time-sensitive workloads.<ref>{{cite web|title=High Performance Solutions for Cyber Security|url=http://newwavedv.com/markets/defense/cyber-security/|website=New Wave Design & Verification|publisher=New Wave DV}}</ref> Moreover, some NICs offer complete low-latency TCP/IP stacks running on integrated FPGAs in combination with userspace libraries that intercept networking operations usually performed by the operating system kernel; Solarflare's open-source '''OpenOnload''' network stack that runs on [[Software:Linux|Linux]] is an example. This kind of functionality is usually referred to as '''user-level networking'''.<ref>{{cite web
 | url = https://www.theregister.co.uk/2012/02/08/solarflare_application_onload_engine/
 | title = Solarflare turns network adapters into servers: When a CPU just isn't fast enough
 | date = 2012-02-08 | access-date = 2014-05-08
 | author = Timothy Prickett Morgan | website = The Register
}}</ref><ref>{{cite web
 | url = http://www.openonload.org/
 | title = OpenOnload
 | date = 2013-12-03 | access-date = 2014-05-08
 | website = openonload.org
}}</ref><ref>{{cite web
 | url = http://www.openonload.org/openonload-google-talk.pdf
 | title = OpenOnload: A user-level network stack
 | date = 2008-03-21
 | access-date = 2014-05-08
 | author1 = Steve Pope
 | author2 = David Riddoch
 | website = openonload.org
 | archive-date = 2014-07-24
 | archive-url = https://web.archive.org/web/20140724083136/http://www.openonload.org/openonload-google-talk.pdf
 | url-status = dead
 }}</ref>

== See also ==
* [[Converged network adapter]] (CNA)
* [[Engineering:Host adapter|Host adapter]]
* Intel Data Direct I/O (DDIO)
* Loopback interface
* [[Network monitoring interface card]] (NMIC)
* [[Virtual network interface]] (VIF)
* [[Engineering:Wireless network interface controller|Wireless network interface controller]] (WNIC)

==Notes==
{{notelist}}

==References==
{{reflist}}

== External links ==
* {{cite web |url=https://technet.microsoft.com/en-us/library/dd392944(v=ws.10).aspx |title=Physical Network Interface |publisher=Microsoft}}
* {{cite web |url=http://www.freedesktop.org/wiki/Software/systemd/PredictableNetworkInterfaceNames/ |title=Predictable Network Interface Names |website=[[Organization:Freedesktop.org|Freedesktop.org]]}}
* [https://greenhost.nl/2013/04/10/multi-queue-network-interfaces-with-smp-on-linux/ Multi-queue network interfaces with SMP on Linux]

{{Basic computer components}}

[[Category:Ethernet]]
[[Category:Networking hardware]]

{{Sourceattribution|Network interface controller}}