View source for Engineering:Operand isolation

In electronic low power digital [[Synchronous circuit|synchronous circuit]] design, '''operand isolation''' is a technique for minimizing the energy overhead associated with redundant operations by selectively blocking the propagation of switching activity through the circuit.<ref>
[http://portal.acm.org/citation.cfm?id=224095 "Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers"]
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This technique isolates sections of the circuit (operation) from "seeing" changes on their inputs (operands) unless they are expected to respond to them.
This is usually done using latches at the inputs of the circuit. The latches become transparent only when the result of the operation is going to be used. One can also use multiplexers or simple [[Engineering:AND gate|AND gate]]s instead of latches.

==Overhead==
There is some area overhead associated with this technique since the circuit designer needs to add extra circuitry, i.e. latches, at the inputs. Also, if the latches are being added in a [[Pipeline (computing)|pipeline]] stage, they might change the critical path, and hence increase the [[Engineering:Propagation delay|propagation delay]] and cycle time. In cases where the overhead is not acceptable, one can think of [[Engineering:Clock gating|clock gating]] as an alternative method of [[Physics:Low-power electronics|low power]] design.

==See also==
* [[Glitch removal]]
* [[Engineering:Clock gating|Clock gating]]
* {{ill|Switching loss|lt=Switching losses|de|Schaltverluste}}
* Distributive law - a similar idea in mathematics
* [[Reduction (mathematics)]] - a similar idea in mathematics
* Reducing a fraction - a similar idea in mathematics
* Reduced Karnaugh map (RKM) - a similar technique in logic optimization
* Infrequent variables - a similar technique in logic optimization

==References==
<references/>


[[Category:Electrical circuits]]

{{Sourceattribution|Operand isolation}}