View source for Engineering:RDNA 3

{{Short description|GPU microarchitecture by AMD}}
{{Infobox GPU microarchitecture
| name                   = RDNA 3
| image                  = AMD RDNA-3 Logo.png
| caption                = <!-- A caption for the image -->
| alt                    = <!-- Mouse over text for the image -->
| launched               = {{Start date and age|2022|12|13}}
| discontinued           = 
| soldby                 = [[Company:Advanced Micro Devices|AMD]]
| designfirm             = [[Company:Advanced Micro Devices|AMD]]
| manuf1                 = [[Company:TSMC|TSMC]]
| process                = {{ubl |[[Company:TSMC|TSMC]] [[Engineering:5 nm process|N4]] |[[Company:TSMC|TSMC]] [[Engineering:5 nm process|N5]] |[[Company:TSMC|TSMC]] N6}}
| codename               = {{ubl |Plum Bonito |Wheat Nas |Hotpink Bonefish}}

<!------------------  Product Series  ------------------->
| products-desktop1      = [[Radeon RX 7000 series]]
| products-hedt1         = Radeon Pro W7000 series
| products-server1       = <!-- (1..5) Server/datacenter product series that use the architecture, e.g. AMD Instinct MI300 -->

<!------------------  Supported Graphics APIs  ------------------->

| direct3d-version       = [[Software:Direct3D#Direct3D 12|Direct3D 12.0 Ultimate]] (feature level 12 2) 
| shadermodel-version    = [[High-Level Shader Language|Shader Model 6.7]]
| opencl-version         = [[OpenCL#OpenCL 2.1|OpenCL 2.1]]
| opengl-version         = [[Software:OpenGL#OpenGL 4.6|OpenGL 4.6]]
| opengles-version       = 
| cuda-version           = 
| optix-version          = 
| mantle-api             = 
| vulkan-api             = [[Software:Vulkan#Vulkan 1.3|Vulkan 1.3]]

<!------------------  Supported Compute APIs  ------------------->
| opengl-compute-version = <!-- Version number of OpenGL Compute supported by the GPU architecture -->
| cuda-compute-version   = <!-- Version number of CUDA Compute supported by the GPU architecture -->
| directcompute-version  = <!-- Version number of DirectCompute supported by the GPU architecture -->

<!------------------  Specifications  ------------------->
| compute                = {{ubl |122.8{{nbsp}}TFLOPS (FP16) |61.42{{nbsp}}TFLOPS (FP32) |1.919{{nbsp}}TFLOPS (FP64)}}
| slowest                = 1500
| slow-unit              = MHz
| fastest                = 2500
| fast-unit              = MHz
| shader-clock           = 2269{{nbsp}}MHz
| l0-cache               = 64{{nbsp}}KB (per {{abbr|WGP|Work Group Processor}}): <br /> {{bulleted list |32{{nbsp}}KB instructions cache |16{{nbsp}}KB K data cache}}
| l1-cache               = 256{{nbsp}}KB (per array)
| l2-cache               = 6{{nbsp}}MB
| l3-cache               = up to 96{{nbsp}}MB
| memory-support         = GDDR6
| memory-clock           = 20 Gbps
| pcie-support           = [[Engineering:PCI Express#PCI Express 4.0|PCIe 4.0]]

<!------------------  Media  Engine ------------------->
| encode-codec           = {{hlist |[[Advanced Video Coding|H.264]] |[[High Efficiency Video Coding|H.265]] |[[Software:AV1|AV1]]}}
| decode-codec           = {{hlist |[[Advanced Video Coding|H.264]] |[[High Efficiency Video Coding|H.265]] |[[Software:AV1|AV1]]}}
| color-depth            = {{hlist |8-bit |10-bit |12-bit}}
| encoders               = {{hlist |AMF |VCE}}
| display-outputs        = {{ubl |[[DisplayPort#2.1|DisplayPort 2.1]] |[[Engineering:HDMI#Version 2.1|HDMI 2.1a]] |[[DisplayPort#USB-C|USB-C]]}}

<!------------------  History  ------------------->
| predecessor            = [[Engineering:RDNA 2|RDNA 2]]
| variant                = CDNA 3 (datacenter)
| successor              = RDNA 4
}}
'''RDNA 3''' is a [[Graphics processing unit|GPU]] microarchitecture designed by [[Company:Advanced Micro Devices|AMD]], released with the [[Engineering:Radeon|Radeon]] [[Radeon RX 7000 series|RX 7000 series]] on December 13, 2022. Alongside powering the RX 7000 series, RDNA 3 is also featured in the SoCs designed by AMD for the Asus ROG Ally and [[Engineering:Lenovo Legion|Legion Go]] consoles.

== Background ==
On June 9, 2022, AMD held their Financial Analyst Day where they presented a client GPU roadmap which contained mention of RDNA 3 coming in 2022 and RDNA 4 coming in 2024.<ref>{{Cite web |last1=Smith |first1=Ryan |date=June 9, 2022 |title=AMD's 2022-2024 Client GPU Roadmap: RDNA 3 This Year, RDNA 4 Lands in 2024 |url=https://www.anandtech.com/show/17443/amds-client-gpu-roadmap-rdna-3-this-year-rdna-4-lands-in-2024 |website=AnandTech |language=en-US |access-date=April 8, 2023}}</ref> AMD announced to investors their intention to achieve a performance-per-watt uplift of over 50% with RDNA 3 and that the upcoming architecture would be built using chiplet packaging on a 5&nbsp;nm process.<ref>{{Cite web |last1=Walton |first1=Jarred |date=June 9, 2022 |title=AMD GPU Roadmap: RDNA 3 With 5nm GPU Chiplets Coming This Year |url=https://www.tomshardware.com/news/amd-rdna3-roadmap-chiplets-5nm |website=Tom's Hardware |language=en-US |access-date=April 8, 2023}}</ref>

A sneak preview for RDNA 3 was included towards the end of AMD's Ryzen 7000 unveiling event on August 29, 2022. The preview included RDNA 3 running gameplay of ''[[Software:Lies of P|Lies of P]]'', AMD CEO Lisa Su confirming that a chiplet design would be used, and a partial look at AMD's reference design for an RDNA 3 GPU.<ref>{{Cite web |last1=Wickens |first1=Katie |date=August 31, 2022 |title=AMD's Lisa Su confirms chiplet-based RDNA 3 GPU architecture |url=https://www.pcgamer.com/amds-lisa-su-confirms-chiplet-based-rdna-3-gpu-architecture/ |website=PC Gamer |language=en-US |access-date=April 8, 2023}}</ref>

Full details for the RDNA 3 architecture were unveiled on November 3, 2022 at an event in Las Vegas.<ref>{{Cite press release |title=AMD Unveils World's Most Advanced Gaming Graphics Cards, Built on Groundbreaking AMD RDNA 3 Architecture with Chiplet Design |url=https://www.amd.com/en/press-releases/2022-11-03-amd-unveils-world-s-most-advanced-gaming-graphics-cards-built |website=AMD |location=Las Vegas, NV |language=en-US |date=November 3, 2022 |access-date=April 8, 2023}}</ref>

== Architectural details ==
=== Chiplet packaging ===
For the first time ever in a consumer GPU, RDNA 3 utilizes modular [[Engineering:Multi-chip module|chiplets]]. AMD previously had great success with its use of chiplets in its [[Engineering:Ryzen|Ryzen]] desktop and [[Engineering:Epyc|Epyc]] server processors.<ref>{{Cite web |last1=James |first1=Dave |date=June 24, 2022 |title=AMD suggests a Ryzen-like design for RDNA 3 chiplets would be 'a reasonable inference' |url=https://www.pcgamer.com/amd-suggests-a-ryzen-like-chiplet-design-for-rdna-3-gpus-would-be-a-reasonable-inference/ |website=PC Gamer |language=en-US |access-date=April 8, 2023}}</ref>

The decision to move to a chiplet-based GPU microarchitecture was led by AMD Senior Vice President Sam Naffziger who had also lead the chiplet initiative with Ryzen and Epyc.<ref>{{Cite web |last1=Alcorn |first1=Paul |last2=Walton |first2=Jarred |date=June 23, 2022 |title=Into the GPU Chiplet Era: An Interview With AMD's Sam Naffziger |url=https://www.tomshardware.com/features/gpu-chiplet-era-interview-amd-sam-naffziger |website=Tom's Hardware |language=en-US |access-date=April 8, 2023}}</ref> The development of RDNA 3's chiplet architecture began towards the end of 2017 with Naffziger leading the AMD graphics team in the effort.<ref name="Brosdahl">{{Cite web |last1=Brosdahl |first1=Peter |date=November 22, 2022 |title=AMD Lead Engineer Sam Naffziger Explains Advantages of RDNA3 Chiplet Design |url=https://www.thefpsreview.com/2022/11/22/amd-lead-engineer-sam-naffziger-explains-advantages-of-rdna3-chiplet-design/ |website=The FPS Review |language=en-US |access-date=April 8, 2023}}</ref>

==== Memory Cache Dies (MCDs) ====
With a respective 2.05 billion transistors, each Memory Cache Die (MCD) contains large blocks of L3 cache and two physical 32-bit GDDR6 memory interfaces for a combined 64-bit interface per MCD.<ref name="Walton">{{Cite web |last1=Walton |first1=Jarred |date=November 14, 2022 |title=AMD RDNA 3 GPU Architecture Deep Dive: The Ryzen Moment for GPUs |url=https://www.tomshardware.com/news/amd-rdna-3-gpu-architecture-deep-dive-the-ryzen-moment-for-gpus |website=Tom's Hardware |language=en-US |access-date=April 8, 2023}}</ref> The Radeon RX 7900 XTX has a 384-bit memory bus through the use of six MCDs while the RX 7900 XT has a 320-bit bus due to its five MCDs.

==== Chiplet interconnects ====
The chiplet interconnects have a bandwidth of 5.3{{nbsp}}TB/s.<ref>{{Cite web |title=AMD Explains the Economics Behind Chiplets for GPUs |url=https://www.techpowerup.com/301071/amd-explains-the-economics-behind-chiplets-for-gpus |website=TechPowerUp |language=en-US |date=November 14, 2022 |access-date=April 8, 2023}}</ref>

==== Process node ====
According to Naffziger, cache and SRAM do not scale as linearly as logic does on advanced nodes like N5 in terms of density and power consumption so they can instead be fabricated on the cheaper, more mature N6 node. The use of smaller chiplet dies rather than one large monolithic die is beneficial for maximizing wafer yields as more dies can be fitted onto a single wafer.<ref name="Brosdahl"/>

=== Compute Units ===
RDNA 3 includes improved [[Superscalar processor|dual-issue]] shader ALUs with the ability to execute two instructions per cycle. It can contain up to 96 graphics Compute Units that can provide up to 61 TFLOPS of compute.<ref name="Gula">{{Cite web |last1=Gula |first1=Damien |date=November 3, 2022 |title=AMD's RDNA 3 GPUs are Way Cheaper Than the RTX 4090 |url=https://gizmodo.com/amd-rdna-3-gpu-rtx-4090-4080-rx-7900-xtx-xt-price-date-1849741000 |website=Gizmodo |language=en-US |access-date=April 8, 2023}}</ref>

RDNA 3 has dedicated AI acceleration with Wave MMA ([[Matrix multiplication|matrix]] multiply-accumulate) instructions,<ref name=wmma-gpuopen>{{cite web|url=https://gpuopen.com/learn/wmma_on_rdna3/|title=How to accelerate AI applications on RDNA 3 using WMMA|first=Aaryaman|last=Vasishta|date=January 10, 2023|publisher=GPUOpen.com|access-date=2023-08-14|archive-url=https://web.archive.org/web/20230110194947/https://gpuopen.com/learn/wmma_on_rdna3/|url-status=live|archive-date=2023-01-10}}</ref> which can improve AI-based performance by 2.7x and also benefits ray tracing instructions, similar to [[Company:Nvidia|Nvidia]]'s Tensor cores.<ref name="Gula"/>

=== Ray tracing ===
Each RDNA 3 Compute Unit contains one ray tracing accelerator. The overall number of ray tracing accelerators is increased due to the higher number of Compute Units, though the number of ray tracing accelerators per Compute Unit has not increased over RDNA 2.

=== Clock speeds ===
RDNA 3 was designed to support high clock speeds. On RDNA 3, clock speeds have been decoupled with the front end operating at a 2.5{{nbsp}}GHz frequency while the shaders operate at 2.3{{nbsp}}GHz. The shaders operating at a lower clock speed gives up to 25% power savings according to AMD and RDNA 3's shader clock speed is still 15% faster than RDNA 2.<ref>{{Cite web |last1=Olšan |first1=Jan |date=November 7, 2022 |title=AMD RDNA 3 details: architecture changes, AI acceleration, DP 2.1 |url=https://www.hwcooling.net/en/amd-rdna-3-details-architecture-changes-ai-acceleration-dp-2-1-en/ |website=HWCooling |language=en-GB |access-date=April 8, 2023}}</ref>

=== Cache and memory subsystem ===
RDNA 3 GPUs use GDDR6 memory rather than faster GDDR6X due to the latter's increased power consumption.

16{{nbsp}}MB Infinity Cache is included on each MCD. Theoretically, additional L3 cache could be added to the MCDs via AMD's 3D V-Cache die stacking technology as the MCDs contain unused [[Engineering:Through-silicon via|TSV]] connection points.<ref>{{Cite web |last1=Klotz |first1=Aaron |date=January 29, 2023 |title=AMD GPU Appears to Leave Room for Future 3D V-Cache |url=https://www.tomshardware.com/news/3d-vcache-rdna3-amd-gpu |website=Tom's Hardware |language=en-US |access-date=April 8, 2023}}</ref><ref>{{Cite web |last1=Ridley |first1=Jacob |date=January 30, 2023 |title=Tiny spots on AMD's RDNA 3 GPU hint at massive cache potential |url=https://www.pcgamer.com/tiny-spots-on-amds-rdna-3-gpu-hint-at-massive-cache-potential/ |website=PC Gamer |language=en-US |access-date=April 8, 2023}}</ref>

=== Power efficiency ===
AMD claims that RDNA 3 achieves a 54% increase in performance-per-watt which is in line with their previous claims of 50% performance-per-watt increases for both RDNA and RDNA 2.

=== Media engine ===
RDNA 3 is the first RDNA architecture to have a dedicated media engine. It is built into the GCD and is based on VCN 4.0 encoding and decoding core.<ref>{{cite web |last1=Shilov |first1=Anton |date=May 4, 2022 |title=First Details About AMD’s Next Generation Video Engine Revealed |url=https://www.tomshardware.com/news/next-amd-video-engine-may-lack-av1 |website=Tom's Hardware |language=en-US |access-date=April 10, 2023}}</ref> AMD's AMF [[Software:AV1|AV1]] encoder is comparable in quality to Nvidia's NVENC AV1 encoder but can handle a higher number of simultaneous encoding streams compared to the limit of 3 on the [[GeForce 40 series|GeForce RTX 40 series]].<ref>{{Cite web |last1=Klotz |first1=Aaron |date=December 12, 2022 |title=AMD's Radeon RX 7900 AV1 encoder is almost on par with Intel Arc and Nvidia's RTX 40 series |url=https://www.techspot.com/news/96945-amd-radeon-rx-7900-av1-encoder-almost-par.html |website=TechSpot |language=en-US |access-date=April 8, 2023}}</ref>

{| class="wikitable" style="text-align: center;"
|+ Supported encoding frame rates (FPS) per resolution and video coding format<ref>{{Cite web |last1=Taylor |first1=Adam |date=December 14, 2022 |title=Tested: With RDNA 3, AMD Radeon is finally useful for content creators |url=https://www.pcworld.com/article/1434166/amd-rdna-3-radeon-rx-7900-xtx-content-creation-review.html |website=PCWorld |language=en-US |access-date=April 8, 2023}}</ref>
|-
! Resolution
! [[Advanced Video Coding|H.264]]
! [[High Efficiency Video Coding|H.265]]
! [[Software:AV1|AV1]]
|-
! style="text-align: left;" | {{midsize|1080p}}
| 
| 
| 
|-
! style="text-align: left;" | {{midsize|1440p}}
| 
| 
| 
|-
! style="text-align: left;" | {{midsize|4K}}
| 180
| 180
| 240
|-
! style="text-align: left;" | {{midsize|8K}}
| 48
| 48
| 60
|-
|}

=== Display engine ===

RDNA 3 GPUs feature a new display engine called the "Radiance Display Engine". AMD touted its support for [[DisplayPort#2.1|DisplayPort 2.1]] UHBR 13.5, delivering up to 54 Gbit/s bandwidth for high refresh rates at [[4K resolution|4K]] and [[8K resolution|8K]] resolutions.<ref>{{Cite web |last1=Sag |first1=Anshel |date=November 14, 2022 |title=AMD's New Radeon RX 7900XTX And 7900XT Put The Pressure On NVIDIA |url=https://www.forbes.com/sites/moorinsights/2022/11/14/amds-new-radeon-rx-7900xtx-and-7900xt-put-the-pressure-on-nvidia/?sh=21776d571aa3 |website=Forbes |language=en-US |access-date=April 8, 2023}}</ref> The Radeon Pro W7900 and W7800 support UHBR 20. DisplayPort 2.1 can support 4K at 480{{nbsp}}Hz and 8K at 165{{nbsp}}Hz with [[Display Stream Compression]] (DSC). The previous DisplayPort 1.4 standard with DSC was limited to 4K at 240{{nbsp}}Hz and 8K at 60{{nbsp}}Hz.

== Navi 3x dies ==
{| class="wikitable" style="text-align: center;"
! rowspan="2" colspan="3" | 
! colspan="3" | Graphics Compute Die <br> (GCD)
! rowspan="2" | Memory Cache Die <br> (MCD)
|-
! style="width:8em" | [https://www.techpowerup.com/gpu-specs/amd-navi-31.g998 Navi 31]
! style="width:8em" | [https://www.techpowerup.com/gpu-specs/amd-navi-32.g1000 Navi 32]
! style="width:8em" | [https://www.techpowerup.com/gpu-specs/amd-navi-33.g1001 Navi 33]
|-
! style="text-align: left;" colspan="3" | {{midsize|{{Tooltip|Ref.|Reference(s)}}}}
! <ref name="Walton"/>
! 
! 
! 
|-
! style="text-align: left;" colspan="3" | {{midsize|Launch}}
| {{dts|2022|December|13|format=my|abbr=on}}
| {{dts|2023|August|25|format=my|abbr=on}}
| {{dts|2023|January|4|format=my|abbr=on}}
| {{dts|2022|December|13|format=my|abbr=on}}
|-
! style="text-align: left;" colspan="3" | {{midsize|Codename}}
| ''Plum Bonito''
| ''Wheat Nas''
| ''Hotpink Bonefish''
| rowspan="2" {{NA}}
|-
! style="text-align: left;" colspan="3" | {{midsize|Compute units <br/> (Stream processors) <br/> [FP32 cores]}}
| 96 <br/> (6144) <br/> [12288]
| 60 <br/> (3840) <br/> [7680]
| 32 <br/> (2048) <br/> [4096]
|-
! style="text-align: left;" colspan="3" | {{midsize|Process}}
| colspan="2" | [[Company:TSMC|TSMC]] [[Engineering:5 nm process|N5]]
| colspan="2" | [[Company:TSMC|TSMC]] N6
|-
! style="text-align: left;" colspan="3" | {{midsize|Transistors}}
| 45.4B
| 19.9B
| 13.3B
| 2.05B
|-
! style="text-align: left;" colspan="3" | {{midsize|Transistor density}}
| 150.2 MTr/mm<sup>2</sup>
| 101.5 MTr/mm<sup>2</sup>
| 65.2 MTr/mm<sup>2</sup>
| 54.64 MTr/mm<sup>2</sup>
|-
! style="text-align: left;" colspan="3" | {{midsize|Die size}}
| 304.35&nbsp;mm<sup>2</sup>
| 196&nbsp;mm<sup>2</sup>
| 204&nbsp;mm<sup>2</sup>
| 37.52&nbsp;mm<sup>2</sup>
|-
! style="text-align: left;" colspan="3" | {{midsize|Max TDP}}
| 405{{nbsp}}W
| 263{{nbsp}}W
| 200{{nbsp}}W
| {{NA}}
|-
! style="text-align: left;" rowspan="4" | {{midsize|Products}}
! style="text-align: left;" rowspan="2" | {{midsize|Consumer}}
! style="text-align: left;" | {{midsize|Desktop}}
| {{ubl|RX 7900 GRE|RX 7900 XT|RX 7900 XTX}}
| {{ubl|RX 7700 XT|RX 7800 XT}}
| {{ubl|RX 7600}}
| {{ubl|RX 7700 XT (3×)|RX 7800 XT (4×)|RX 7900 GRE (4×)|RX 7900 XT (5×)|RX 7900 XTX (6×)}}
|-
! style="text-align: left;" | {{midsize|Mobile}}
| {{ubl|RX 7900M}}
| {{NA}}
| {{ubl|RX 7600S|RX 7600M|RX 7600M XT|RX 7700S}}
| {{ubl|RX 7900M (4×)}}
|-
! style="text-align: left;" rowspan="2" | {{midsize|Workstation}}
! style="text-align: left;" | {{midsize|Desktop}}
| {{ubl|W7800|W7900}}
| {{ubl|W7700}}
| {{ubl|W7500|W7600}}
| {{ubl|W7700 (4×)|W7800 (4×)|W7900 (6×)}}
|-
! style="text-align: left;" | {{midsize|Mobile}}
| {{NA}}
| {{NA}}
| {{NA}}
| {{NA}}
|}

== Products ==
=== Desktop ===

=== Mobile ===

=== Workstation ===
==== Desktop Workstation ====

=== Integrated graphics processing units (iGPUs) ===
{| class="wikitable" style="text-align: center; font-size: 85%;"
! rowspan="2" | Model
! rowspan="2" | Launch
! rowspan="2" | Codename
! rowspan="2" | [[Microarchitecture|Architecture]] <br /> & [[Engineering:Semiconductor device fabrication|fab]]
! rowspan="2" | Die <br/> size
! colspan="2" | Core
! colspan="2" | [[Fillrate]]{{efn|name="Boost"}}{{efn|name="Texture fill"}}{{efn|name="Pixel fill"}}
! colspan="3" | Processing power{{efn|name="Boost"}}{{efn|name="FLOPS"}}<br />([[FLOPS|GFLOPS]])
! colspan="3" | [[Cache (computing)#GPU cache|Cache]]
! rowspan="2" | [[Thermal design power|TDP]]
! rowspan="2" | Bus <br /> interface
|-
! Config{{efn|name="Core config"}}{{efn|name="Stream processors"}}
! Clock{{efn|name="Boost"}} <br /> ([[Hertz|MHz]])
! Texture <br /> ([[Texel (graphics)|GT]]/s)
! Pixel <br /> ([[Pixel|GP]]/s)
! [[Half-precision floating-point format|Half]]
! [[Single-precision floating-point format|Single]]
! [[Double-precision floating-point format|Double]]
! L0
! L1
! L2
|-
! style="text-align:left;" | {{Nowrap|[https://www.amd.com/en/products/apu/amd-ryzen-5-7540u Radeon 740M]}}
| rowspan="5" | {{dts|2023|April|format=mdy|abbr=on}}
| rowspan="5" | Phoenix
| rowspan="5" | [[Engineering:RDNA 3|RDNA 3]] <br /> [[Company:TSMC|TSMC]]{{nbsp}}[[Engineering:5 nm process|N4]]
| rowspan="5" | 178{{nbsp}}mm<sup>2</sup>
| rowspan="2" | 4 CU <br /> 256:16:8:4 
| 2,500
| 40.0
| 20.0
| 5,120
| 2,560
| 80.0
| rowspan="2" | 64{{nbsp}}KB
| rowspan="2" | 512{{nbsp}}KB
| rowspan="5" | 2{{nbsp}}MB
| 15–30{{nbsp}}W
| rowspan="5" | [[Engineering:PCI Express#PCI Express 4.0|PCIe 4.0]]<br />×8
|-
! style="text-align:left;" | {{Nowrap|[https://www.amd.com/en/products/apu/amd-ryzen-z1 Ryzen Z1]}}
| 2,735
| 43.7
| 21.8
| 5,600
| 2,800
| 87.5
| 9–30{{nbsp}}W
|-
! style="text-align:left;" | {{Nowrap|[https://www.amd.com/en/products/apu/amd-ryzen-5-7640hs Radeon 760M]}}
| 8 CU <br /> 512:32:16:8 
| 1,000 <br /> ''2,600''
| 32.0 <br /> ''83.2''
| 21.3 <br /> ''55.5''
| 4,096 <br /> ''10,649''
| 2,048 <br /> ''5,324''
| 64.0 <br /> ''166.4''
| 128{{nbsp}}KB
| 1{{nbsp}}MB
| 35–54{{nbsp}}W
|-
! style="text-align:left;" |{{Nowrap|[https://www.amd.com/en/products/apu/amd-ryzen-9-7940hs Radeon 780M]}}
| rowspan="2" | 12 CU <br />768:48:24:12
| 2,700 <br /> ''2,800''
| 129.6 <br /> ''134.4''
| 64.8 <br /> ''67.2''
| 16,588 <br /> ''17,203''
| 8,294 <br /> ''8,600''
| 259.2 <br /> ''268.8''
| rowspan="2" | 192{{nbsp}}KB
| rowspan="2" | 1.5{{nbsp}}MB
| 35–54{{nbsp}}W
|-
! style="text-align:left;" |{{Nowrap|[https://www.amd.com/en/products/apu/amd-ryzen-z1-extreme Ryzen Z1 Extreme]}}
| 2,800
| 134.4
| 67.2
| 17,203
| 8,600
| 268.8
| 9–30{{nbsp}}W
|-
|}
{{notelist|refs=
{{efn|name="Boost"|Boost values (if available) are stated below the base value in ''italic''.}}
{{efn|name="Texture fill"|Texture fillrate is calculated as the number of '''Texture Mapping Units''' multiplied by the base (or boost) core clock speed.}}
{{efn|name="Pixel fill"|Pixel fillrate is calculated as the number of '''Render Output Units''' multiplied by the base (or boost) core clock speed.}}
{{efn|name="FLOPS"|Precision performance is calculated from the base (or boost) core clock speed based on a [[Multiply–accumulate operation#Fused multiply–add|FMA]] operation.}}
{{efn|name="Core config"|[[Unified shader model|Unified shaders]] : [[Texture mapping unit]]s : [[Render output unit]]s : [[Ray tracing (graphics)|Ray accelerators]] and [[Graphics Core Next#Compute units|Compute units (CU)]]}}
{{efn|name="Stream processors"|GPUs based on [[Engineering:RDNA (microarchitecture)#RDNA 3|RDNA 3]] have dual-issue '''stream processors''' so that up to two shader instructions can be executed per [[Instructions per cycle|clock cycle]] under certain [[Instruction-level parallelism|parallelism]] conditions.}}
}}

== References ==
{{reflist}}

[[Category:Graphics microarchitectures]]

{{Sourceattribution|RDNA 3}}