View source for Engineering:ST6 and ST7

[[Image:CRQFP80 UV ST62E40.jpg|thumb|ST62E40 microcontroller, based on the ST6 architecture]]
The '''ST6''' and '''ST7''' are 8-bit [[Engineering:Microcontroller|microcontroller]] product lines from [[Company:STMicroelectronics|STMicroelectronics]].  They are commonly used in small embedded applications like washing machines.

Although they use similar peripherals and are marketed as part of the same product line,<ref name=ds6200>Datasheet: ST62T00C/T01C from 1998</ref><ref name="edn_8bit_ISA_2006">{{cite web|title=2006 EDN Microcontroller/Microprocessor directory, 8-bit microprocessors sorted by Instruction Set Architecture |url=http://www.edn.com/contents/images/edn06mpd_8bit_ISA.pdf?industryid=45943|page=26}} 100616 edn.com</ref> the two architectures are actually quite different.

Both have an 8-bit [[Accumulator (computing)|accumulator]] used for most operations, plus two 8-bit index registers (X and Y) used for memory addressing.  Also both have 8-bit instructions followed by up to 2 bytes of operands, and both have support for manipulating and branching on individual bits of memory.

There, the similarities end.

The ST6 is a [[Harvard architecture]] with an 8-bit (256 byte) data address space and a separate 12-bit (4096 byte) program space.  Operands are always 1 byte long, and some instructions support two operands, such as "move 8-bit immediate to 8-bit memory address".  Subroutine calls are done using a separate hardware stack.  Data registers (but not the program counter or flags) are memory-mapped.

The ST6's [[Addressing mode|addressing mode]]s are limited to immediate, 8-bit absolute memory address, and register indirect modes (X) and (Y).

The ST7 is a [[Von Neumann architecture|von Neumann architecture]] with a single 16-bit (64 kiB) address space.  The first 256 bytes of RAM (the [[Zero page|zero page]]) have extra flexibility.  There are no two-operand instructions except for "test bit and branch".  Its registers are not memory-mapped, and it uses general-purpose RAM (plus a stack pointer register) for subroutine calls.

The ST7 supports a wide variety of addressing modes, including base+index and double-indirect.

[[Image:ST62EXX.jpg|thumb|Three members of the ST6 microcontroller family: ST62E01, ST62E20, ST62E25]]
==ST6 architecture==

The ST6 has 64 bytes of RAM and 4096 bytes of program [[Read-only memory|ROM]]. Larger amounts are accessed by bank-switching the low 2K section of the ROM.

The RAM address space is actually 256 bytes, divided as follows:
* 0&ndash;63: Not implemented
* 64&ndash;127: Bank-switchable window into program ROM and data [[Engineering:EPROM|EPROM]].
* 128&ndash;191: General-purpose RAM
* 192&ndash;255: Peripheral control registers (GPIO ports, timers, etc.)  The [[Accumulator (computing)|accumulator]] is mapped at address 255, but is more commonly addressed implicitly.

Not mapped into the address space is a 12-bit program counter and an associated hardware stack (four or six levels deep, depending on model).  There are only two status bits ([[Carry flag|carry]] and [[Zero flag|zero]]), and they are banked based on processor mode, with separate status bits for normal, interrupt and [[Non-maskable interrupt|non-maskable interrupt]] operation.

The first four general-purpose RAM locations are also known as the X, Y, V and W registers, and some instructions can access them using special short addressing modes.  The X and Y registers serve as index registers, and can use indirect addressing modes <code>(X)</code> and <code>(Y)</code>.

The instruction set consists of one byte of opcode, followed by up to two one-byte operands.  The instruction set can be summarized as follows:

{|class="wikitable" style="text-align:center"
|+ ST6 family instruction set<ref name=ST6>{{cite web |title=ST6 Family Programming Manual |version=Revision 2.0 |date=October 2004 |publisher=[[Company:STMicroelectronics|STMicroelectronics]] |url=http://www.st.com/content/ccc/resource/technical/document/programming_manual/4d/05/d1/a5/a0/9e/40/8b/CD00004606.pdf/files/CD00004606.pdf/jcr:content/translations/en.CD00004606.pdf |access-date=2017-02-28}}</ref>

! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || C|| Z || Description
|-
|colspan=14|
|-
!colspan=5| offset ||colspan=2| opc || 0 || &mdash; || &mdash; ||colspan=4| Conditional branches (5-bit PC-relative)
|-
|colspan=5| offset || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| JRNZ ''address'' || || ||align=left| Jump to PC + simm5 if Z == 0
|-
|colspan=5| offset || 1 || 0 || 0 || &mdash; || &mdash; ||align=left| JRZ ''address'' || || ||align=left| Jump to PC + simm5 if Z == 1
|-
|colspan=5| offset || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| JRNC ''address'' || || ||align=left| Jump to PC + simm5 if C == 0
|-
|colspan=5| offset || 1 || 1 || 0 || &mdash; || &mdash; ||align=left| JRC ''address'' || || ||align=left| Jump to PC + simm5 if C == 1
|-
|colspan=14|
|-
!colspan=4| imm4 || c || 0 || 0 || 1 || imm8 || &mdash; ||colspan=4| Unconditional branches (12-bit absolute)
|-
|colspan=4| imm4 || 0 || 0 || 0 || 1 || imm8 || &mdash; ||align=left| CALL ''imm12'' || || ||align=left| Push PC, jump to 12-bit address
|-
|colspan=4| imm4 || 1 || 0 || 0 || 1 || imm8 || &mdash; ||align=left| JP ''imm12'' || || ||align=left| Jump to 12-bit address
|-
|colspan=14|
|- style="background:lightgrey;"
|colspan=3| &mdash; || 0 || 0 || 1 || 0 || 1 || &mdash; || &mdash; ||colspan=4 align=left| (reserved)
|-
|colspan=14|
|-
!colspan=2| reg || c || 1 || c || 1 || 0 || 1 || &mdash; || &mdash; ||colspan=4|Register operations (on X, Y, V or W)
|-
|colspan=2| reg || 0 || 1 || 0 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| INC ''reg'' || Z || ||align=left| Increment register.  Z is set, C is not.
|-
|colspan=2| reg || 1 || 1 || 0 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| LD A,''reg'' || Z || ||align=left| A := {X, Y, V or W}
|-
|colspan=2| reg || 0 || 1 || 1 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| DEC ''reg'' || Z || ||align=left| Decrement register.  Z is set, C is not.
|-
|colspan=2| reg || 1 || 1 || 1 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| LD ''reg'',A || Z || ||align=left| {X, Y, V or W} := A
|-
|colspan=14|
|-
!colspan=3| opcode || 0 || 1 || 1 || 0 || 1 || &mdash; || &mdash; ||colspan=4| Miscellaneous operations
|-
| 0 || 0 || 0 || 0 || 1 || 1 || 0 || 1 || addr || imm8 ||align=left| LDI addr,imm8 || || ||align=left| Set RAM to 8-bit immediate value
|- style="background:lightgrey;"
| 1 || 0 || 0 || 0 || 1 || 1 || 0 || 1 || &mdash; || &mdash; ||colspan=4 align=left| (reserved)
|-
| 0 || 1 || 0 || 0 || 1 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| RETI || || ||align=left| Return from interrupt.  Pop PC, restore flags.
|-
| 1 || 1 || 0 || 0 || 1 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| RET || || ||align=left| Return from subroutine.  Pop PC from hardware stack.
|-
| 0 || 0 || 1 || 0 || 1 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| COM A || Z || C ||align=left| Complement: C := msbit(A); A := ~A
|-
| 1 || 0 || 1 || 0 || 1 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| RLC A || || C ||align=left| A := A + A + C
|-
| 0 || 1 || 1 || 0 || 1 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| STOP || || ||align=left| Halt processor, clock, most peripherals until next interrupt
|-
| 1 || 1 || 1 || 0 || 1 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| WAIT || || ||align=left| Halt processor until next interrupt; clock continues
|-
|colspan=14|
|-
!colspan=3| bit ||colspan=2| opc || 0 || 1 || 1 || address || ? ||colspan=4| Bit operations (absolute address only)
|-
|colspan=3| bit || 0 || 0 || 0 || 1 || 1 || src || simm8 ||align=left| JRR&nbsp;''bit'',''src'',''address'' || || C ||align=left| C := src.bit; jump to PC+simm8 if reset (clear)
|-
|colspan=3| bit || 1 || 0 || 0 || 1 || 1 || src || simm8 ||align=left| JRS ''bit'',''src'',''address'' || || C ||align=left| C := src.bit; jump to PC+simm8 if set
|-
|colspan=3| bit || 0 || 1 || 0 || 1 || 1 || dst || &mdash; ||align=left| RES ''bit'',''dst'' || || ||align=left| Reset (set to 0) dst.bit
|-
|colspan=3| bit || 1 || 1 || 0 || 1 || 1 || dst || &mdash; ||align=left| SET ''bit'',''dst'' || || ||align=left| Set (to 1) dst.bit
|-
|colspan=14|
|-
!colspan=3| opcode ||colspan=2| data || 1 || 1 || 1 || ? || &mdash; ||colspan=4| ALU operations with RAM or immediate
|-
|colspan=3| opcode || 0 || 0 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| (X) || || ||align=left| Operand is (X)
|-
|colspan=3| opcode || 0 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| (Y) || || ||align=left| Operand is (Y)
|-
|colspan=3| opcode || 1 || 0 || 1 || 1 || 1 || imm8 || &mdash; ||align=left| ''imm8'' || || ||align=left| Operand is 8-bit immediate (''source only'')
|-
|colspan=3| opcode || 1 || 1 || 1 || 1 || 1 || addr || &mdash; ||align=left| ''addr'' || || ||align=left| Operand is 8-bit RAM address
|-
| 0 || 0 || 0 ||colspan=2| src || 1 || 1 || 1 || ? || &mdash; ||align=left| LD A,''src'' || Z || ||align=left| A := ''src''
|-
| 1 || 0 || 0 ||colspan=2| dst || 1 || 1 || 1 || ? || &mdash; ||align=left| LD ''dst'',A || Z || ||align=left| ''dst'' := A (''immediate forbidden'')
|-
| 0 || 1 || 0 ||colspan=2| src || 1 || 1 || 1 || ? || &mdash; ||align=left| ADD A,''src'' || Z || C ||align=left| A := A + ''src''
|-
| 1 || 1 || 0 ||colspan=2| src || 1 || 1 || 1 || ? || &mdash; ||align=left| SUB A,''src'' || Z || C<sup>{{Anchor|Carry note-0}}†</sup> ||align=left| A := A − ''src''
|-
| 0 || 0 || 1 ||colspan=2| src || 1 || 1 || 1 || ? || &mdash; ||align=left| CP A,''src'' || Z || C<sup>{{Anchor|Carry note-1}}†</sup> ||align=left| A − ''src''
|-
| 1 || 0 || 1 ||colspan=2| src || 1 || 1 || 1 || ? || &mdash; ||align=left| AND A,''src'' || Z || ||align=left| A := A &amp; ''src''
|-
| 0 || 1 || 1 ||colspan=2| dst || 1 || 1 || 1 || ? || &mdash; ||align=left| INC ''dst'' || Z || ||align=left| ''dst'' := ''dst'' + 1 (''immediate forbidden'')
|-
| 1 || 1 || 1 ||colspan=2| dst || 1 || 1 || 1 || ? || &mdash; ||align=left| DEC ''dst'' || Z || ||align=left| ''dst'' := ''dst'' − 1 (''immediate forbidden'')
|}
{{Anchor|Carry note}}†: ^ <sup>'''a b'''</sup> Confusingly, different models of the ST6 family use different conventions for the value of the carry bit after a subtraction.  ST60 processors use the "carry" convention, which clears the bit if the subtract underflows, while the ST62 and ST63 processors use the "borrow" convention, which sets the bit in that case.{{r|ST6|p=21–22,42}}

== ST7 architecture ==

The ST7 has six registers: the accumulator, X and Y index registers, stack pointer, program counter, and condition code register.  Also, double-indirect addressing allows the zero page of RAM to serve as additional registers.  An unusual but useful feature is that an interrupt pushes four of these registers on the stack (A and X as well as the usual PC and CC), and interrupt return restores them.

ALU instructions fall into two categories, two-operand and one-operand.

Two-operand instructions use the accumulator as the first source.  The addressing mode specifies the second source, which may be:
* 8-bit immediate
* 8-bit absolute address
* 16-bit absolute address
* Indexed (X)
* Indexed plus 8-bit offset (address8,X)
* Indexed plus 16-bit offset (address16,X)
The destination is usually the accumulator, but a few instructions modify the second source.  (Immediate operands are forbidden in such cases.)

One-operand instructions use the specified operand for both source and destination.  The operand may be:
* The accumulator A
* The X register
* 8-bit absolute address
* Indexed (X)
* Indexed plus 8-bit offset (address8,X)

Register plus offset computes a full-width sum, so the 8-bit form may address memory up to 255+255 = 510.

In addition to the above, there are three prefix bytes which may be prepended to any instruction for which they make sense:
* PDY (0x90) changes all references to the X register to Y.  This allows (Y), (address8,Y) and (address16,Y) addressing modes.  This affects implicit operands as well, so the "load X" instruction becomes "load Y".  A consequence of this is that load X can only use the X-relative addressing modes, and load Y can only use the Y-relative ones.
* PIX (0x92) adds an indirection step to the instruction.  The 8- or 16-bit address following the opcode byte is replaced by an 8-bit address of a memory location which holds an 8- or 16-bit address (the latter in big-endian order).  This may then be indexed by the X register as usual.  This allows (address8), (address16), ([address8],X) and ([address8.w],X) addressing modes.
* PIY (0x91) combines the above effects.  This allows the ([address8],Y) and ([address8.w],Y) addressing modes.  (It may also be used with other modes as part of the "load Y" and "store Y" instructions.)

{|class="wikitable" style="text-align:center"
|+ ST7 family instruction set<ref>{{cite web |title=ST7 Family Programming Manual |version=Revision 2 |date=November 2005 |publisher=[[Company:STMicroelectronics|STMicroelectronics]] |url=http://www.st.com/content/ccc/resource/technical/document/programming_manual/f5/1c/5f/0c/c6/8f/44/73/CD00004607.pdf/files/CD00004607.pdf/jcr:content/translations/en.CD00004607.pdf |access-date=2017-02-28}}</ref>

! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || Description
|-
|colspan=12|
|-
! 0 || 0 || 0 || c ||colspan=3| bit || v || address || ? ||colspan=2| Bit operations
|-
| 0 || 0 || 0 || 0 ||colspan=3| bit || 0 || addr8 || soff8 ||align=left| BTJT ''addr8'',#''bit'',''label'' ||align=left| Jump to PC + soff8 if source bit is true (set)
|-
| 0 || 0 || 0 || 0 ||colspan=3| bit || 1 || addr8 || soff8 ||align=left| BTJF ''addr8'',#''bit'',''label'' ||align=left| Jump to PC + soff8 if source bit is false (clear)
|-
| 0 || 0 || 0 || 1 ||colspan=3| bit || 0 || addr8 || &mdash; ||align=left| BSET ''addr8'',#''bit'' ||align=left| Set specified bit to 1
|-
| 0 || 0 || 0 || 1 ||colspan=3| bit || 1 || addr8 || &mdash; ||align=left| BRES ''addr8'',#''bit'' ||align=left| Reset (clear) specified bit to 0
|-
|colspan=12|
|-
! 0 || 0 || 1 || 0 ||colspan=4| condition || soff8 || &mdash; ||colspan=2| Conditional branches (8-bit relative offset)
|-
| 0 || 0 || 1 || 0 || 0 || 0 || 0 || 0 || soff8 || &mdash; ||align=left| JRA ''label'' ||align=left| Branch always (true)
|-
| 0 || 0 || 1 || 0 || 0 || 0 || 0 || 1 || soff8 || &mdash; ||align=left| JRF ''label'' ||align=left| Branch never (false)
|-
| 0 || 0 || 1 || 0 || 0 || 0 || 1 || 0 || soff8 || &mdash; ||align=left| JRUGT ''label'' ||align=left| Branch if unsigned greater than (C=0 and Z=0)
|-
| 0 || 0 || 1 || 0 || 0 || 0 || 1 || 1 || soff8 || &mdash; ||align=left| JRULE ''label'' ||align=left| Branch if unsigned less than or equal (C=1 or Z=1)
|-
| 0 || 0 || 1 || 0 || 0 || 1 || 0 || 0 || soff8 || &mdash; ||align=left| JRNC ''label'' ||align=left| Branch if no carry (C=0)
|-
| 0 || 0 || 1 || 0 || 0 || 1 || 0 || 1 || soff8 || &mdash; ||align=left| JRC ''label'' ||align=left| Branch if carry (C=1)
|-
| 0 || 0 || 1 || 0 || 0 || 1 || 1 || 0 || soff8 || &mdash; ||align=left| JRNE ''label'' ||align=left| Branch if not equal (Z=0)
|-
| 0 || 0 || 1 || 0 || 0 || 1 || 1 || 1 || soff8 || &mdash; ||align=left| JREQ ''label'' ||align=left| Branch if equal (Z=1)
|-
| 0 || 0 || 1 || 0 || 1 || 0 || 0 || 0 || soff8 || &mdash; ||align=left| JRNH ''label'' ||align=left| Branch if not half-carry (H=0)
|-
| 0 || 0 || 1 || 0 || 1 || 0 || 0 || 1 || soff8 || &mdash; ||align=left| JRH ''label'' ||align=left| Branch if half-carry (H=1)
|-
| 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || soff8 || &mdash; ||align=left| JRPL ''label'' ||align=left| Branch if plus (N=0)
|-
| 0 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || soff8 || &mdash; ||align=left| JRMI ''label'' ||align=left| Branch if minus (N=1)
|-
| 0 || 0 || 1 || 0 || 1 || 1 || 0 || 0 || soff8 || &mdash; ||align=left| JRNM ''label'' ||align=left| Branch if not interrupt mask (M=0)
|-
| 0 || 0 || 1 || 0 || 1 || 1 || 0 || 1 || soff8 || &mdash; ||align=left| JRM ''label'' ||align=left| Branch if interrupts masked (M=1)
|-
| 0 || 0 || 1 || 0 || 1 || 1 || 1 || 0 || soff8 || &mdash; ||align=left| JRIL ''label'' ||align=left| Branch if interrupt line is low
|-
| 0 || 0 || 1 || 0 || 1 || 1 || 1 || 1 || soff8 || &mdash; ||align=left| JRIH ''label'' ||align=left| Branch if interrupt line is high
|-
|colspan=12|
|-
! 0 ||colspan=3| mode ||colspan=4| opcode || ? || &mdash; ||colspan=2| One-operand instructions
|-
| 0 || 0 || 1 || 1 ||colspan=4| opcode || addr8 || &mdash; ||align=left| OP ''addr8'' ||align=left| 8-bit absolute address
|-
| 0 || 1 || 0 || 0 || colspan=4| opcode || &mdash; || &mdash; ||align=left| OP A ||align=left| Accumulator
|-
| 0 || 1 || 0 || 1 || colspan=4| opcode || &mdash; || &mdash; ||align=left| OP X ||align=left| X register (Y register with prefix)
|-
| 0 || 1 || 1 || 0 || colspan=4| opcode || addr8 || &mdash; ||align=left| OP (addr8,X) ||align=left| 8-bit address plus X
|-
| 0 || 1 || 1 || 1 || colspan=4| opcode || &mdash; || &mdash; ||align=left| OP (X) ||align=left| Indexed with no offset
|-
| 0 ||colspan=3| mode || 0 || 0 || 0 || 0 || ? || &mdash; ||align=left| NEG ''operand'' ||align=left| Two's-complement negate
|- style="background:lightgrey;"
| 0 ||colspan=3| mode || 0 || 0 || 0 || 1 || ? || &mdash; ||colspan=2 align=left| (reserved)
|- style="background:lightgrey;"
| 0 ||colspan=3| mode || 0 || 0 || 1 || 0 || ? || &mdash; ||colspan=2 align=left| (reserved)
|-
| 0 || 1 || 0 || 0 || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| MUL X,A ||align=left| X:A := X × A.  (MUL Y,A with prefix)
|-
| 0 ||colspan=3| mode || 0 || 0 || 1 || 1 || ? || &mdash; ||align=left| CPL ''operand'' ||align=left| Ones' complement, logical not
|-
| 0 ||colspan=3| mode || 0 || 1 || 0 || 0 || ? || &mdash; ||align=left| SRL ''operand'' ||align=left| Shift right logical.  Msbit cleared, lsbit to carry.
|- style="background:lightgrey;"
| 0 ||colspan=3| mode || 0 || 1 || 0 || 1 || ? || &mdash; ||colspan=2 align=left| (reserved)
|-
| 0 ||colspan=3| mode || 0 || 1 || 1 || 0 || ? || &mdash; ||align=left| RRC ''operand'' ||align=left| Rotate right through carry,  (operand:C) := (C:operand)
|-
| 0 ||colspan=3| mode || 0 || 1 || 1 || 1 || ? || &mdash; ||align=left| SRA ''operand'' ||align=left| Shift right arithmetic.  Msbit preserved, lebit to carry.
|-
| 0 ||colspan=3| mode || 1 || 0 || 0 || 0 || ? || &mdash; ||align=left| SLL ''operand'' ||align=left| Shift left.  Msbit to carry.
|-
| 0 ||colspan=3| mode || 1 || 0 || 0 || 1 || ? || &mdash; ||align=left| RLC ''operand'' ||align=left| Rotate left through carry.
|-
| 0 ||colspan=3| mode || 1 || 0 || 1 || 0 || ? || &mdash; ||align=left| DEC ''operand'' ||align=left| Decrement.  (N and Z set, carry unaffected)
|- style="background:lightgrey;"
| 0 ||colspan=3| mode || 1 || 0 || 1 || 1 || ? || &mdash; ||colspan=2 align=left| (reserved)
|-
| 0 ||colspan=3| mode || 1 || 1 || 0 || 0 || ? || &mdash; ||align=left| INC ''operand'' ||align=left| Increment.  (N and Z set, carry unaffected)
|-
| 0 ||colspan=3| mode || 1 || 1 || 0 || 1 || ? || &mdash; ||align=left| TNZ ''operand'' ||align=left| Test non-zero.  Set N and Z based on operand.
|-
| 0 ||colspan=3| mode || 1 || 1 || 1 || 0 || ? || &mdash; ||align=left| SWAP ''operand'' ||align=left| Swap halves of operand (4-bit rotate).
|-
| 0 ||colspan=3| mode || 1 || 1 || 1 || 1 || ? || &mdash; ||align=left| CLR ''operand'' ||align=left| Set operand to 0.  N and Z set to fixed values.operand.
|-
|colspan=12|
|-
! 1 || 0 || 0 ||colspan=5| opcode || &mdash; || &mdash; ||colspan=2| Miscellaneous instructions.  None implicitly set the condition codes.
|-
| 1 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| IRET ||align=left| Return from interrupt (pop CC, A, X, PC)
|-
| 1 || 0 || 0 || 0 || 0 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| RET ||align=left| Return from subroutine (pop PC)
|-
| 1 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| TRAP ||align=left| Force trap interrupt
|- style="background:lightgrey;"
| 1 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || &mdash; || &mdash; ||colspan=2 align=left| (reserved)
|-
| 1 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || &mdash; || &mdash; ||align=left| POP A ||align=left| Pop A from stack
|-
| 1 || 0 || 0 || 0 || 0 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| POP X ||align=left| Pop X from stack
|-
| 1 || 0 || 0 || 0 || 0 || 1 || 1 || 0 || &mdash; || &mdash; ||align=left| POP CC ||align=left| Pop condition codes from stack
|- style="background:lightgrey;"
| 1 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || &mdash; || &mdash; ||colspan=2 align=left| (reserved)
|-
| 1 || 0 || 0 || 0 || 1 || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| PUSH A ||align=left| Push A onto stack
|-
| 1 || 0 || 0 || 0 || 1 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| PUSH X ||align=left| Push X onto stack
|-
| 1 || 0 || 0 || 0 || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| PUSH CC ||align=left| Push condition codes onto stack
|- style="background:lightgrey;"
| 1 || 0 || 0 || 0 || 1 || 0 || 1 || 1 || &mdash; || &mdash; ||colspan=2 align=left| (reserved)
|- style="background:lightgrey;"
| 1 || 0 || 0 || 0 || 1 || 1 || 0 || &mdash; || &mdash; || &mdash; ||colspan=2 align=left| (reserved)
|-
| 1 || 0 || 0 || 0 || 1 || 1 || 1 || 0 || &mdash; || &mdash; ||align=left| HALT ||align=left| Halt processor and clocks
|-
| 1 || 0 || 0 || 0 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| WFI ||align=left| Wait for interrupt, halting processor but not clocks
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| PDY ||align=left| Instruction prefix; swap X and Y in next instruction
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| PIY ||align=left| Instruction prefix; PDY plus PIX
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| PIX ||align=left| Instruction prefix; use 8-bit memory indirect for operand
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| LD X,Y ||align=left| X := Y.  With PDY, does "LD Y,X".
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 0 || &mdash; || &mdash; ||align=left| LD S,X ||align=left| S := X.  Load stack pointer.
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| LD S,A ||align=left| S := A.  Load stack pointer.
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 1 || 0 || &mdash; || &mdash; ||align=left| LD X,S ||align=left| X := S.
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| LD X,A ||align=left| X := A.
|-
| 1 || 0 || 0 || 1 || 1 || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| RCF ||align=left| Reset (clear) carry flag
|-
| 1 || 0 || 0 || 1 || 1 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| SCF ||align=left| Set carry flag
|-
| 1 || 0 || 0 || 1 || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| RIM ||align=left| Reset interrupt mask (enable interrupts)
|-
| 1 || 0 || 0 || 1 || 1 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| SIM ||align=left| Set interrupt mask (disable interrupts)
|-
| 1 || 0 || 0 || 1 || 1 || 1 || 0 || 0 || &mdash; || &mdash; ||align=left| RSP ||align=left| Reset stack pointer (to top of RAM)
|-
| 1 || 0 || 0 || 1 || 1 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| NOP ||align=left| No operation.  (=LD A,A)
|-
| 1 || 0 || 0 || 1 || 1 || 1 || 1 || 0 || &mdash; || &mdash; ||align=left| LD A,S ||align=left| A := S
|-
| 1 || 0 || 0 || 1 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| LD A,X ||align=left| A := X.
|-
|colspan=12|
|-
! 1 ||colspan=3| mode ||colspan=4| opcode || value || ? ||colspan=2| Two-operand instructions A := A op operand
|-
| 1 || 0 || 1 || 0 ||colspan=4| opcode || imm8 || &mdash; ||align=left| OP #''imm8'' ||align=left| 8-bit immediate operand ''(forbidden as destination)''
|-
| 1 || 0 || 1 || 1 ||colspan=4| opcode || addr8 || &mdash; ||align=left| OP ''addr8'' ||align=left| 8-bit absolute address
|-
| 1 || 1 || 0 || 0 ||colspan=4| opcode || addrhi || addrlo ||align=left| OP ''addr16'' ||align=left| 16-bit absolute address
|-
| 1 || 1 || 0 || 1 ||colspan=4| opcode || addrhi || addrlo ||align=left| OP (''addr16'',X) ||align=left| Indexed with 16-bit offset
|-
| 1 || 1 || 1 || 0 ||colspan=4| opcode || addr8 || &mdash; ||align=left| OP (''addr8'',X) ||align=left| Indexed with 8-bit offset
|-
| 1 || 1 || 1 || 1 ||colspan=4| opcode || &mdash; || &mdash; ||align=left| OP (X) ||align=left| Indexed with no offset
|-
| 1 ||colspan=3| mode || 0 || 0 || 0 || 0 || value || ? ||align=left| SUB A,''operand'' ||align=left| A := A &minus; operand
|-
| 1 ||colspan=3| mode || 0 || 0 || 0 || 1 || value || ? ||align=left| CP A,''operand'' ||align=left| Compare A &minus; operand
|-
| 1 ||colspan=3| mode || 0 || 0 || 1 || 0 || value || ? ||align=left| SBC A,''operand'' ||align=left| Subtract with borrow A := A &minus; operand &minus; C
|-
| 1 ||colspan=3| mode || 0 || 0 || 1 || 1 || value || ? ||align=left| CP X,''operand'' ||align=left| Compare X &minus; operand
|-
| 1 ||colspan=3| mode || 0 || 1 || 0 || 0 || value || ? ||align=left| AND A,''operand'' ||align=left| A := A &amp; operand, bitwise and
|-
| 1 ||colspan=3| mode || 0 || 1 || 0 || 1 || value || ? ||align=left| BCP A,''operand'' ||align=left| Bitwise test A &amp; operand
|-
| 1 ||colspan=3| mode || 0 || 1 || 1 || 0 || value || ? ||align=left| LD A,''operand'' ||align=left| Load A := operand
|- style="background:lightgrey;"
| 1 || 0 || 1 || 0 || 0 || 1 || 1 || 1 || imm8 || &mdash; ||colspan=2 align=left| (reserved, =LD #imm8,A)
|-
| 1 ||colspan=3| mode || 0 || 1 || 1 || 1 || value || ? ||align=left| LD ''operand'',A ||align=left| Store operand := A
|-
| 1 ||colspan=3| mode || 1 || 0 || 0 || 0 || value || ? ||align=left| XOR A,''operand'' ||align=left| A := A ^ operand, exclusive-or
|-
| 1 ||colspan=3| mode || 1 || 0 || 0 || 1 || value || ? ||align=left| ADC A,''operand'' ||align=left| A := A + operand + C, add with carry
|-
| 1 ||colspan=3| mode || 1 || 0 || 1 || 0 || value || ? ||align=left| OR A,''operand'' ||align=left| A := A {{!}} operand, inclusive or
|-
| 1 ||colspan=3| mode || 1 || 0 || 1 || 1 || value || ? ||align=left| ADD X,''operand'' ||align=left| A := A + operand
|- style="background:lightgrey;"
| 1 || 0 || 1 || 0 || 1 || 1 || 0 || 0 || imm8 || x ||colspan=2 align=left| (reserved, =JP #imm8)
|-
| 1 ||colspan=3| mode || 1 || 1 || 0 || 0 || value || ? ||align=left| JP ''operand'' ||align=left| PC := operand, unconditional jump
|-
| 1 || 0 || 1 || 0 || 1 || 1 || 0 || 1 || soff8 || &mdash; ||align=left| CALLR ''label'' ||align=left| PUSH PC, PC := PC + operand
|-
| 1 ||colspan=3| mode || 1 || 1 || 0 || 1 || value || ? ||align=left| CALL ''operand'' ||align=left| Push PC, PC := operand
|-
| 1 ||colspan=3| mode || 1 || 1 || 1 || 0 || value || ? ||align=left| LD X,''operand'' ||align=left| Load X := operand
|- style="background:lightgrey;"
| 1 || 0 || 1 || 0 || 1 || 1 || 1 || 1 || imm8 || &mdash; ||colspan=2 align=left| (reserved, =LD #imm8,X)
|-
| 1 ||colspan=3| mode || 1 || 1 || 1 || 1 || value || ? ||align=left| LD ''operand'',X ||align=left| Store operand := X
|}

== References ==
<references />

{{DEFAULTSORT:ST6 ST7}}
[[Category:Microcontrollers]]
[[Category:Instruction set architectures]]

{{Sourceattribution|ST6 and ST7}}