View source for Engineering:Texas Instruments TMS9900

{{Infobox CPU architecture|name = Texas Instruments TMS9900
|designer = [[Company:Texas Instruments|Texas Instruments]]
|bits = 16-bit
|introduced = 1976
|version =
|design = CISC
|type =
|encoding =
|branching =
|endianness = Big
|extensions =
|open =
|registers = PC, WP, ST
|gpr = 2 internally located in processor (WP, ST) 16 × 16-bit stack located in external RAM
}}
Introduced in June 1976, the '''TMS9900''' was one of the first commercially available, single-chip [[16-bit|16-bit]] [[Engineering:Microprocessor|microprocessor]]s.  The TMS9900 found its most widespread use in the Texas Instruments TI-99/4 and TI-99/4A home computers.{{citation needed|date=July 2012}}

==History==
[[Image:KL TI TMS9900 Black Background.jpg|right|thumb|TMS9900JL in ceramic package with gold-plated [[Engineering:Lead (electronics)|pin]]s]]
The TMS9900 was designed as a single chip version of the [[Engineering:TI-990|TI 990]] [[Minicomputer|minicomputer]] series, much like the [[Engineering:Intersil 6100|Intersil 6100]] was a single chip [[Engineering:PDP-8|PDP-8]] (12 bit), and the [[Company:Fairchild Semiconductor|Fairchild]] 9440 and [[Company:Data General|Data General]] mN601 were both one-chip versions of [[Company:Data General|Data General]]'s [[Engineering:Data General Nova|Nova]].  Unlike other 16-bit microprocessors such as the [[Company:National Semiconductor|National Semiconductor]] [[Engineering:IMP-16|IMP-16]] or DEC LSI-11, some of which predated the TMS9900, the latter was a single-chip, self-contained 16-bit microprocessor.

The idea was that using the same architecture across TI's different divisions would create synergy effects for the TMS9900: "one company, one computer architecture". In late 1978, Walden C. Rhines gave a presentation of the TMS9900 to the IBM group developing the [[Engineering:IBM Personal Computer|IBM Personal Computer]]. According to Rhines, TI lost out on the opportunity to provide the chip for IBM's PC mainly because Intel already had production samples for the [[Engineering:Intel 8086|Intel 8086]] and these were needed for IBM's quality assurance program for the new product. After the failed attempt to get into the personal computer market with products such as TI-99/4A the company microprocessor division eventually switched focus to the [[Engineering:Texas Instruments TMS320|TMS320]] special-purpose processor series.<ref>{{cite web
 |url=https://spectrum.ieee.org/tech-history/heroic-failures/the-inside-story-of-texas-instruments-biggest-blunder-the-tms9900-microprocessor
 |title=The Inside Story of Texas Instruments' Biggest Blunder: The TMS9900 Microprocessor
 |last=Rhines
 |first=Walden C.
 |date=2017-06-22
 |website=
 |publisher=IEEE Spectrum
 |access-date=2019-01-20
 |quote= }}</ref>

==Architecture==
The TMS9900 has three internal 16-bit [[Processor register|register]]s — [[Program counter]] (PC), [[Status register]] (ST), and Workspace Pointer register (WP).<ref name="Microprocessor Data Manual p.3">{{cite book|title = TMS9900 Microprocessor Data Manual|publisher = Texas Instruments Inc. | year = 1976| page = 3| url = http://www.bitsavers.org/components/ti/TMS9900/TMS_9900_Microprocessor_Data_Manual_May76.pdf }}</ref>  The WP register [[Pointer (computer programming)|points]] to a base address in external RAM where the processor's 16 general purpose user registers (each 16&nbsp;bits wide) are kept.  This architecture allows for quick [[Context switch|context switch]]ing; e.g. when a [[Subroutine|subroutine]] is entered, only the single workspace register needs to be changed instead of requiring registers to be saved individually.

Addresses refer to bytes with [[Endianness|big endian]] ordering convention.  The TMS9900 is a classic 16 bit machine with an address space of 2<sup>16</sup> bytes (65,536 bytes or 32,768 words).

There is no concept of a stack and no stack pointer register.  Instead, branch instructions exist that save the program counter to a register and change the register context.  The 16 hardware and 16 software interrupt vectors each consist of a pair of PC and WP values, so the register context switch is automatically performed by an interrupt as well.

==Instruction set and addressing==
The TMS9900 has 69 instructions which are one, two or three words long and always word-aligned in memory.  The instruction set is fairly [[Orthogonal instruction set|orthogonal]], meaning that with few exceptions, instructions can use all methods of accessing [[Operand|operand]]s (addressing modes).

Addressing modes include Immediate (operand in instruction), Direct or "Symbolic" (operand address in instruction), Register (operand in workspace register), Register Indirect (operand address in workspace register) with or without auto-increment, Indexed (operand address in instruction indexed with workspace register content), and Program Counter Relative.

The most important dual-operand instructions (add, subtract, compare, move etc.) contain 2-bit addressing mode and 4-bit register selector fields for both source and destination operands.  In the opcode, "Symbolic" mode is represented as Indexed mode with the register field set to 0, therefore workspace register 0 (WR0) cannot be used in Indexed mode.  In less frequently used dual-operand instructions like XOR, the destination operand must be a workspace register (or workspace register pair in the case of multiply and divide instructions).

Flow control is facilitated through a group of one unconditional and twelve conditional Jump instructions.  Jump targets are relative to PC with an offset of -128 to +127 word addresses.

For subroutine calls, the Branch and Load Workspace Pointer (BLWP) instruction loads new WP and PC values, then saves the values of WP, PC and ST to the (new) registers 13, 14 and 15 respectively.  At the end of the subroutine, the Return Workspace Pointer (RTWP) restores these in reverse order.  Using BLWP/RTWP, it is possible to nest subroutine calls despite the absence of a stack, however, the programmer needs to assign the appropriate register workspace explicitly.

The instruction set also contains a Branch and Link (BL) opcode that only saves PC to register 11 without changing WP.  In this case, a branch instruction (B) using WR11 as the destination address can serve as the return opcode, but BL-type subroutines cannot be nested without the programmer taking actions to save the return address.

The TMS9900 has an uncommon, and rarely used, instruction called "X" (eXecute). This instruction is used to execute another instruction at an address pointed to by a [[Processor register|register]] without changing program flow, i.e. execution continues at the address following the X instruction.  This instruction can be used for debugging (as a [[Breakpoint|breakpoint]] instruction) and for creating indexed-opcode tables as used in byte-code interpreters.

The TMS9900 also supports the eXtended OPeration (XOP) instruction. XOP is given a number in the range 0-15 as well as a source address. When invoked, the instruction will perform a context switch through one of sixteen vectors at predefined locations in memory. This is similar to an interrupt, but the XOP instruction also stores the source address in register 11 of the new workspace. XOP is less flexible than a BLWP, as the transfer vectors have to be at fixed locations, but saves memory, since the source address can be used by the executed subroutine instead, when it's not defining the location of the vector.
XOP is used to implement instructions in software in lower end models, where higher end versions of the 990 minicomputer series may have dedicated hardware to execute them.

In typical comparisons with the [[Engineering:Intel 8086|Intel 8086]], the TMS9900 had smaller programs.{{citation needed|date=July 2012}} The only{{citation needed|date=January 2018}} disadvantages were the small address space and need for fast RAM.

==Implementation==
[[Image:TMS9900 Pinout.svg|right|thumb|215px|TMS9900 pin configuration (64-Pin [[Engineering:Dual in-line package|DIP]])]] 
The TMS9900 was implemented in an N-channel silicon gate MOS process,<ref name="Microprocessor Data Manual p.3" /> which required +5&#8239;V, −5&#8239;V and +12&#8239;V power supplies and a four-phase (non-overlapping) clock with a maximum frequency of 3&nbsp;MHz (333&#8239;ns cycle),<ref>{{cite book|title = TMS9900 Microprocessor Data Manual|publisher = Texas Instruments Inc. | year = 1976| page = 31| url = http://www.bitsavers.org/components/ti/TMS9900/TMS_9900_Microprocessor_Data_Manual_May76.pdf}}</ref> usually generated from a 48&nbsp;MHz crystal using a TIM9904 (aka 74LS362) clock generator chip.

The shortest instructions require eight clock cycles or 2.7&nbsp;μs to complete (assuming 0 external wait cycles), many others run between 10 and 14 cycles (3.3...4.7&nbsp;μs); the longest-running instruction (DIV) can take up to 124 cycles (41.3&nbsp;μs).<ref>{{cite book|title = TMS9900 Microprocessor Data Manual|publisher = Texas Instruments Inc. | year = 1976| page = 28| url = http://www.bitsavers.org/components/ti/TMS9900/TMS_9900_Microprocessor_Data_Manual_May76.pdf }}</ref>

The chip was packaged in a (then unusual) 64-pin, 0.9" wide [[Engineering:Dual in-line package|DIP]].  The comparatively large number of pins allowed for the 15-bit (word) [[Engineering:Address bus|address bus]] and 16-bit data bus to be brought out on dedicated pins without the use of multiplexing (unlike e.g. the [[Engineering:Intel 8086|Intel 8086]] CPU), keeping external memory connections simple.  Contrary to the convention used by many other manufacturers, TI labeled the most significant address and data lines "A0" and "D0", respectively.  All internal data paths and the [[Arithmetic logic unit|ALU]] are 16 bits wide.

The processor can be paused with the address bus tri-stated for external [[Direct memory access|direct memory access]] (DMA). 
Memory accesses are always 16 bits wide, with the CPU automatically performing read-before-write operations for byte-wide accesses.

The hardware interrupt system supports a 4-bit interrupt priority input, which needed to be higher than the priority level stored in the status register (bits 12−15) in order for the interrupt request to be served.  In addition, the ''/LOAD'' input provides a non-maskable interrupt facility with a dedicated vector.<ref>{{cite book|title = TMS9900 Microprocessor Data Manual|publisher = Texas Instruments Inc. | year = 1976| page = 6| url = http://www.bitsavers.org/components/ti/TMS9900/TMS_9900_Microprocessor_Data_Manual_May76.pdf }}</ref>

The TMS9900 CPU also contains a 16-bit [[Shift register|shift register]] ("CRU") designed for interfacing with external shift registers, with dedicated instructions supporting access to fields of 1−16 bit width out of a total of 4096 addressable bits.

Parallel peripherals can be attached in memory-mapped fashion to the regular address and data bus.

==Applications==
[[File:Tomy-Tutor-wControllers.jpg|link=File:Tomy-Tutor-wControllers.jpg|thumb|right|The Tomy Tutor, a 1983 home computer based on the TMS9995 processor]]
The TMS9900 was used in the TI-99/4 and TI-99/4A home computers. Unfortunately, to reduce the production costs, TI chose to use in these systems just 128 16-bit words of the fast kind of RAM that the TMS9900 could access directly. The rest of the memory was 16kB of [[8-bit|8-bit]] DRAM that was accessible only indirectly through the video display controller, which crippled the performance of the TI-99/4.

TI developed the TM990 series of computer modules, including CPU, memory, I/O, which when plugged into a card frame could form a 16-bit minicomputer. These were typically used for process control. <ref>{{cite web | url=http://www.stuartconner.me.uk/tm990/tm990.htm | title=Stuart's TM 990 Series 16-Bit Microcomputer Modules| accessdate=2014-03-25}}</ref> A microprocessor trainer was released in the form of the TM990/189.<ref>{{cite web | url=http://www.rskey.org/CMS/index.php/exhibit-hall/118-texas-instruments-tm-990189 | title=Programmable Calculators - Texas Instruments TM990/189| accessdate=2014-03-25}}</ref>

==TMS9900 Family Product Development==
The second generation of the TMS9900 family of microprocessors was the TMS9995 which provided "functional performance at speeds 3 times faster than any previous 9900 family processor",<ref>{{cite book|title = TMS9995 marketing brochure|publisher = Texas Instruments Inc. | year = 1981| page = 2| url = http://www.stuartconner.me.uk/tms9995_eval_module/downloads/tms9995_evaluation_module_brochure.pdf }}</ref> largely due to the inclusion of instruction prefetch technology. In the home computer arena, the TMS9995 only found use in the [[Engineering:Tomy Tutor|Tomy Tutor]], an esoteric TI99-4/A upgrade called the [[Engineering:Geneve 9640|Geneve 9640]], and a project printed in ''Electronics Today'': the Powertran Cortex.<ref>{{cite web | url=http://www.powertrancortex.com | title=Powertran Cortex.com | accessdate=2014-03-27}}</ref> It was planned to be used in the TI-99/2 & TI-99/8 computer systems, but neither advanced past the prototype stage.

[[Image:TI-TMS9900NL.jpg|right|thumb|TMS9900NL in plastic DIP package]]

TI later developed the more powerful TMS99000 family of microprocessors, which was used as the CPU in the [[Engineering:TI-990#TI-990 models|990/10A]] minicomputer as a cost reduction. Unfortunately, by the time the 990/10A made it to market, the end of the minicomputer era was already in sight.

The TMS99000 family includes two microprocessors,<ref>{{cite book|title = TMS99105A and TMS99110A 16-Bit Microprocessors Preliminary Data Manual|publisher = Texas Instruments Inc. | year = 1982| page = 1| url = http://bitsavers.org/components/ti/TMS9900/TMS99105A_and_TMS99110A_16-Bit_Microprocessors_Preliminary_Data_Manual_Nov82.pdf }}</ref> the TMS99105A and the TMS99110A, which are identical except for inclusion of on-chip macrostore ROM memory (macrostore memory contains added functions or instructions through emulation routines written in standard machine code). The on-chip ROM Macrostore in the TMS99110A microprocessor contains floating point instructions which are available as part of the machine language instruction set, while the TMS99105A does not include a ROM macrostore. A third member of the TMS99000 family, the TMS99120, was announced<ref>{{cite book|title = Microsystems Designers Handbook, 2nd Edition|publisher = Texas Instruments Limited | year = 1981 | pages = 3–25 onwards }}</ref> but may never have been commercially produced. The on-chip ROM Macrostore in the TMS99120 contains run-time support routines for the PASCAL high-level language.

The instruction set for the TMS99000 family is a superset of the TMS9995 and TMS9900, with object code compatibility. The additional instructions includes those for signed multiply and divide; long-word shift, add, and subtract; load status register, load workplace pointer, stack operations, multiprocessor support, bit manipulation. Members of the family can instantaneously access 256KiB of memory, and may use the TIM99610 memory mapper to address up to 16MiB. The architecture contains many other advances over the TMS9900 and TMS9995.

==Variants==
{| class="wikitable" 
! Model 
! Description
|-
| TI990/9  ||   Early multi-chip CPU for minicomputer systems, 1974
|-
| TI990/10 ||   Multi-chip implementation for minicomputer systems, 1975
|-
| TI990/12 ||   Multi-chip implementation, faster than 990/10.
|-
| TMS9900  ||   Single chip implementation, 1976. Used in the TI-99/4(A) computer.
|-
| TMS9940  ||   Microcontroller with 2KB ROM, 128B RAM, decrementer, CRU bus, 1979
|-
| TMS9980<br>TMS9981  ||   8-bit versions of TMS9900
|-
| TMS9985  ||  A TMS9940 with 8KB ROM, 256B RAM, and an 8-bit external bus, c. 1978 (never released)
|-
| TMS9989  ||  Improved 9980, used in military hardware.
|-
| TMS9995  ||  Improved TMS9985-like, no ROM. Used in the TI-99/2 & TI-99/8 prototypes, the [[Engineering:Tomy Tutor|Tomy Tutor]] and the Geneve computer.
|-
| TMS99105 ||  Baseline member of the TMS99000 microprocessor family.
|- 
| TMS99110 ||  TMS99000 family microprocessor with floating point instructions pre-programmed into the on-chip Macrostore ROM memory.
|-
| TMS99120 ||  TMS99000 family microprocessor with run-time support routines for the PASCAL high-level language pre-programmed into<br>the on-chip Macrostore ROM memory. (Microprocessor was announced but may never have been commercially produced.)
|-
|}

<gallery caption="Die photos" mode="packed" heights="200px">
Image:TI_TMS9900_die.JPG|TMS9900
Image:TI_TMS9981_die.jpg|TMS9981
Image:Rochester_Electronics_TMS9995_die.JPG|TMS9995
Image:TI_TMS99105A_die.JPG|TMS99105A
</gallery>

==References==
<references />

==External links==
*[http://www.bitsavers.org/components/ti/TMS9900 TMS9900 manuals and references] from Bitsavers



{{Sourceattribution|Texas Instruments TMS9900|1}}