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{{Short description|Power ISA-based processor}}
{{POWER, PowerPC, and Power ISA}}
The '''IBM A2''' is an [[Open source|open source]] massively [[Multi-core processor|multicore]] capable and [[Multithreading (computer architecture)|multithreaded]] 64-bit [[Power ISA]] processor core designed by [[Company:IBM|IBM]] using the [[Power ISA#Power ISA v.2.06|Power ISA v.2.06]] specification. Versions of processors based on the A2 core range from a 2.3 [[Hertz|GHz]] version with 16 cores consuming [[Watt|65&nbsp;W]] to a less powerful, four core version, consuming 20&nbsp;W at 1.4&nbsp;GHz.

== Design ==
The A2 core is a processor core designed for customization and embedded use in system on chip-devices, and was developed following IBM's [[Engineering:Video game console|game console]] processor designs, the [[Engineering:Xenon (processor)|Xbox 360-processor]] and [[Engineering:Cell (microprocessor)|Cell processor]] for the [[Engineering:PlayStation 3|PlayStation 3]].<ref name="github-a2i">{{cite web | title = a2i on GitHub | publisher = IBM | author = IBM | date = 2020-06-27 | url=https://github.com/OpenPOWERFoundation/a2i}}</ref>

=== A2I ===
'''A2I''' is a 4-way simultaneous multithreaded core which implements the 64-bit Power ISA v.2.06 Book III-E<ref>[https://www.youtube.com/watch?v=DshEFxTZd6I&t=116s A2I Explored - Bill Flynn, IBM]</ref> embedded platform specification with support for the [[Embedded hypervisor|embedded hypervisor]] features. It was designed for implementations with many cores and focusing on high throughput and many simultaneous threads. A2I was written in [[VHDL]].<ref>[https://github.com/OpenPOWERFoundation/a2i/tree/master/rel/src/vhdl/work A2I VHDL source code]</ref>

The core has 4×32 64-bit general purpose registers (GPR) with full support for both little and big endian byte ordering, 16&nbsp;KB+16&nbsp;KB instruction and data cache and is capable of four-way multithreading.

It has a fine grain [[Branch predictor|branch prediction unit]] (BPU) with eight 1024-entry branch history tables. The L1 caches is a 16&nbsp;KB 8-way set-associative data cache and a 4-way set-associative 16&nbsp;KB instruction cache. It executes a simple [[Out-of-order execution#In-order processors|in-order]] pipeline capable of issuing two instructions per cycle; one to the 6-stage arithmetic logic unit (ALU) and one to the optional auxiliary execution unit (AXU).

It includes a memory management unit but no floating point unit (FPU). Such facilities are handled by the AXU, which has support for any number of standardized or customized macros, such as floating point units, vector units, DSPs, media accelerators and other units with instruction sets and registers not part of the Power ISA. The core has a system interface unit used to connect to other on die cores, with a 256-bit interface for data writes and a 128-bit interface for instruction and data reads at full core speed.

=== A2O ===
The '''A2O''' is a slightly more modern version, written in [[Verilog]],<ref>[https://github.com/OpenPOWERFoundation/a2o/tree/master/rel/src/verilog/work A2O verilog source code]</ref> using the [[Power ISA#Power ISA v.2.07|Power ISA v.2.07]] Book III-E.<ref>[https://www.youtube.com/watch?v=2IshMgIGCR4&t=191s IBM open sources the A2O Core - Bill Flyn, IBM]</ref> It is optimized for single core performance and designed to reach 3 GHz at 45 nm process technology. The A2O differs from its sibling in that it is only two-way multithreaded, 32+32 kB data and instruction L1 caches, and is capable of [[Out-of-order execution#In-order processors|out-of-order]] execution.

When A2O was released, no actual products have used it.

== OpenSource ==
In the second half of 2020 IBM released the A2I and A2O cores under a [[Creative Commons license]], and published the VHDL and Verilog code on [[GitHub]].<ref name="github-a2i" /><ref>{{cite web | title = a2o on GitHub | publisher = IBM | author = IBM | date = 2020-09-15 | url=https://github.com/OpenPOWERFoundation/a2o}}</ref> The intention was to add them to the [[Organization:OpenPOWER Foundation|OpenPOWER Foundation]]'s offerings of free and open processor cores.<ref>{{cite web | title = A2I POWER Processor Core Contributed to OpenPOWER Community to Advance Open Hardware Collaboration | publisher = OpenPOWER Foundation | author = OpenPOWER Foundation | date = 2020-06-30 | url = https://openpowerfoundation.org/a2i-power-processor-core-contributed-to-openpower-community-to-advance-open-hardware-collaboration/ | access-date = 2020-06-30 | archive-date = 2020-06-30 | archive-url = https://web.archive.org/web/20200630183700/https://openpowerfoundation.org/a2i-power-processor-core-contributed-to-openpower-community-to-advance-open-hardware-collaboration/ | url-status = dead }}</ref><ref>{{cite web | title = OpenPOWER Foundation Unveils IBM Hardware/Software Contributions at OpenPOWER Summit| publisher = InsideHPC | author = InsideHPC | date=2020-09-15 | url = https://insidehpc.com/2020/09/openpower-foundation-unveils-ibm-hardware-software-contributions-at-openpower-summit}}</ref>
As A2 was designed in 2010, A2I and A2O are not compliant with the [[Power ISA#Power ISA v.3.0|Power ISA 3.0]] or 3.1 which is mandatory for OpenPOWER cores. It is IBM's wish for the cores to be updated so they comply with the newer version of the ISA.

== Products ==

=== PowerEN ===
The '''PowerEN''' (Power Edge of Network), or the "[[Wire speed|wire-speed]] processor", is designed as hybrid between regular [[Network processor|networking processors]], doing [[Packet switching|switching]] and [[Routing|routing]] and a typical server processor, that is manipulating and packaging data. It was revealed on February 8, 2010, at ISSCC 2010.

Each chip uses the A2I core and has 8&nbsp;MB of [[CPU cache|cache]] as well a multitude of task-specific engines besides the general-purpose processors, such as [[XML]], [[Cryptography|cryptography]], [[Data compression|compression]] and [[Regular expression|regular expression]] accelerators each with MMUs of their own, four [[10 Gigabit Ethernet|10 Gigabit Ethernet]] ports and two [[Engineering:PCI Express|PCIe lanes]]. Up to four chips can be linked in a [[Symmetric multiprocessing|SMP]] system without any additional support chips. The chips are said to be extremely complex according to Charlie Johnson, chief architect at IBM,<ref>[https://www.theregister.co.uk/2010/02/09/ibm_wire_speed_processor/ IBM gives birth to 'wire-speed' processor]</ref> and use 1.43 billion transistors on a [[Engineering:Die (integrated circuit)|die]] size of 428&nbsp;mm² [[Engineering:Semiconductor device fabrication|fabricated]] using a 45 nm process.

=== Blue Gene/Q ===
The [[Blue Gene|Blue Gene/Q]] processor is an 18 core chip using the A2I core running at 1.6&nbsp;GHz with special features for fast thread context switching, quad [[SIMD]] [[Floating-point unit|floating point unit]], 5D torus chip-to-chip network and 2 GB/s external I/O. The cores are linked by a [[Engineering:Crossbar switch|crossbar switch]] at half core speed to a 32&nbsp;MB [[EDRAM|eDRAM]] [[CPU cache|L2 cache]]. The L2 cache is multi-versioned and supports [[Transactional memory|transactional memory]] and [[Speculative multithreading|speculative execution]]. A Blue Gene/Q chip has two DDR3 memory controllers running at 1.33&nbsp;GHz, supporting up to 16 GB RAM.<ref>{{cite web | title = US commissions beefy IBM supercomputer | publisher = IDG News Service | author=Joab Jackson | date = 2011-02-08 | url=http://www.itworld.com/hardware/136215/us-commissions-beefy-ibm-supercomputer}}</ref><ref>{{cite web | title = IBM's BlueGene/Q Super Chip Grows 18th Core | author =  Timothy Prickett Morgan | publisher = insideHPC.com | date = 2011-08-26 | access-date = 2013-11-18 | url = http://insidehpc.com/2011/08/26/ibms-bluegeneq-super-chip-grows-18th-core/}}</ref>

It uses 16 cores for computing, and one core for operating system services. This 17th core will take care of [[Interrupt|interrupt]]s, asynchronous I/O, MPI [[Flow control (data)|flow control]], and RAS functionality. The 18th core is used as a spare in case one of the other cores are permanently damaged (for instance in manufacturing) but is shut down in functional operation. The Blue Gene/Q chip is manufactured on IBM's copper SOI process at 45&nbsp;nm, will deliver a peak performance of 204.8 [[FLOPS|GFLOPS]] at 1.6&nbsp;GHz and draws about 55 watts. The chip has a die size of 19×19&nbsp;mm (359.5&nbsp;mm²) and uses 1.47 billion transistors.

== See also ==
* [[Engineering:IBM Power microprocessors|IBM Power microprocessors]]
* [[Organization:OpenPOWER Foundation|OpenPOWER Foundation]]
* [[Engineering:POWER7|POWER7]]

== References ==
<references />
* [https://wiki.alcf.anl.gov/parts/images/c/cf/A2.pdf A2 Processor User’s Manual - IBM]
* [https://web.archive.org/web/20160304075552/https://www.power.org/wp-content/uploads/2010/11/Wire_Speed_Presentation_5.5_-_Final4.pdf A Wire-Speed Power Processor: 2.3GHz 45nm SOI with 16 Cores and 64 Threads – Presentation, IBM]
* [https://web.archive.org/web/20160306174127/https://www.power.org/wp-content/uploads/2010/11/ISSCC_WSP_Paper_5_05r2.pdf A Wire-Speed Power Processor: 2.3GHz 45nm SOI with 16 Cores and 64 Threads – White paper, IBM]
* [https://web.archive.org/web/20120929075724/http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=222700420&pgno=1 ISSCC: IBM back in network processor game - EE Times]

{{DEFAULTSORT:A2}}
[[Category:IBM microprocessors]]
[[Category:Power microprocessors]]
[[Category:Transactional memory]]
[[Category:Open microprocessors]]

{{Sourceattribution|IBM A2}}