View source for Memory cell (computing)

{{Short description|Part of computer memory}}
[[File:6T SRAM memory cell layout.jpg|thumb|260px|Layout for the silicon implementation of a six transistor SRAM memory cell.]]
{{Memory types}}
The '''memory cell''' is the fundamental building block of [[Computer memory|computer memory]]. The memory cell is an [[Physics:Electronic circuit|electronic circuit]] that stores one [[Bit|bit]] of binary information and it must be set to store a logic 1 ([[Physics:High voltage|high voltage]] level) and reset to store a logic 0 (low voltage level). Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.

Over the [[History of computing|history of computing]], different memory cell architectures have been used, including [[Magnetic-core memory|core memory]] and [[Bubble memory|bubble memory]]. Today{{As of?|date=September 2023}}, the most common memory cell architecture is [[Engineering:Semiconductor memory|MOS memory]], which consists of [[Engineering:MOSFET|metal–oxide–semiconductor]] (MOS) memory cells. Modern [[Random-access memory|random-access memory]] (RAM) uses [[Engineering:MOSFET|MOS field-effect transistors]] (MOSFETs) as flip-flops, along with [[Engineering:MOSFET#MOS capacitor|MOS capacitor]]s for certain types of RAM.

The SRAM ([[Static random-access memory|static RAM]]) memory cell is a type of [[Engineering:Flip-flop (electronics)|flip-flop]] circuit, typically implemented using MOSFETs. These require very low power to keep the stored value when not being accessed. A second type, DRAM ([[Dynamic random-access memory|dynamic RAM]]), is based around MOS capacitors. Charging and discharging a capacitor can store a '1' or a '0' in the cell. However, the charge in this capacitor will slowly leak away, and must be refreshed periodically. Because of this refresh process, DRAM uses more power. However, DRAM can achieve greater storage densities.

On the other hand, most [[Non-volatile memory|non-volatile memory]] (NVM) is based on [[Engineering:Floating-gate MOSFET|floating-gate]] memory cell architectures. Non-volatile memory technologies including [[Engineering:EPROM|EPROM]], [[EEPROM]] and [[Flash memory|flash memory]] use floating-gate memory cells, which are based around [[Engineering:Floating-gate MOSFET|floating-gate MOSFET]] transistors.

== Description ==
The memory cell is the fundamental building block of memory. It can be implemented using different technologies, such as [[Engineering:Bipolar junction transistor|bipolar]], [[Engineering:MOSFET|MOS]], and other [[Physics:Semiconductor device|semiconductor device]]s. It can also be built from [[Physics:Magnetism|magnetic]] material such as [[Physics:Ferrite (magnet)|ferrite]] cores or magnetic bubbles.<ref>{{cite book|last1=D. Tang|first1=Denny|last2=Lee|first2=Yuan-Jen|title=Magnetic memory: Fundamentals and technology|year=2010|publisher={{wipe|Cambridge University Press}}|isbn=978-1139484497|page=91|url=https://books.google.com/books?id=xsMMWOjFXzAC&q=ferrite%20core%20memory%20magnetic%20bubble&pg=PA91|access-date=13 December 2015}}</ref> Regardless of the implementation technology used, the purpose of the binary memory cell is always the same. It stores one bit of binary information that can be accessed by reading the cell and it must be set to store a 1 and reset to store a 0.<ref>{{cite book|last1=Fletcher|first1=William|title=An engineering approach to digital design|year=1980|publisher=Prentice-Hall|isbn=0-13-277699-5|page=[https://archive.org/details/engineeringappro00fle_wur/page/283 283]|url-access=registration|url=https://archive.org/details/engineeringappro00fle_wur/page/283}}</ref>

== Significance ==
[[File:Square array of mosfet cells read.png|thumb|Square array of DRAM memory cells being read]]
Logic circuits without memory cells are called [[Combinational logic|combinational]], meaning the output depends only on the present input.
But memory is a key element of [[Engineering:Digital electronics|digital systems]]. In computers, it allows to store both programs and data and memory cells are also used for temporary storage of the output of combinational circuits to be used later by digital systems.
Logic circuits that use memory cells are called [[Sequential logic|sequential circuits]], meaning the output depends not only on the present input, but also on the history of past inputs.
This dependence on the history of past inputs makes these circuits [[State (computer science)|stateful]] and it is the memory cells that store this state. 
These circuits require a timing generator or clock for their operation.<ref>{{cite book|title=Microelectronic circuits|url=https://archive.org/details/microelectronicc0000sedr|url-access=registration|year=1987|publisher=Holt, Rinehart and Winston, Inc.|isbn=0-03-007328-6|page=[https://archive.org/details/microelectronicc0000sedr/page/883 883]|edition=Second}}</ref>

Computer memory used in most contemporary [[Computer|computer systems]] is built mainly out of DRAM cells; since the layout is much smaller than SRAM, it can be more densely packed yielding cheaper memory with greater capacity. Since the DRAM memory cell stores its value as the charge of a capacitor, and there are current leakage issues, its value must be constantly rewritten. This is one of the reasons that make DRAM cells slower than the larger SRAM (static RAM) cells, which has its value always available. That is the reason why SRAM memory is used for on-[[Engineering:Integrated circuit|chip]] [[CPU cache|cache]] included in modern [[Engineering:Microprocessor|microprocessor]] chips.<ref>{{cite web|title=The technical question: the cache, how does it work?|url=http://www.pcworld.fr/materiel/actualites,lqt-cache-cpu-memoire-cache-sram,547751,1.htm|archive-url=https://web.archive.org/web/20140330034345/http://www.pcworld.fr/materiel/actualites,lqt-cache-cpu-memoire-cache-sram,547751,1.htm|url-status=dead|archive-date=30 March 2014|website=PC World Fr|language=fr}}</ref>

== History ==
{{See|Computer memory#History}}
[[File:KL CoreMemory.jpg|thumb|260px|32x32 [[Magnetic-core memory|core memory]] plane storing 1024{{nbsp}}[[Bit|bit]]s of data.]]

On December 11, 1946 Freddie Williams applied for a patent on his cathode-ray tube (CRT) storing device ([[Williams tube]]) with 128 40-[[Bit|bit]] words. It was operational in 1947 and is considered the first practical implementation of [[Random-access memory|random-access memory]] (RAM).<ref>{{cite book|last1=O’Regan|first1=Gerard|title=Giants of computing: A compendium of select, pivotal pioneers|year=2013|publisher=[[Company:Springer Science+Business Media|Springer]]|isbn=978-1447153405|page=267|url=https://books.google.com/books?id=oSq5BAAAQBAJ&q=williams%20tube%20first%20random%20access%20memory&pg=PA267|access-date=13 December 2015}}</ref> In that year, the first patent applications for [[Magnetic-core memory|magnetic-core memory]] were filed by Frederick Viehe.<ref>{{Cite book|url=https://archive.org/details/milestonesincomp0000reil|url-access=registration|title=Milestones in computer science and information technology|last=Reilly|first=Edwin D.|year=2003|publisher=Greenwood publishing group|isbn=9781573565219|page=[https://archive.org/details/milestonesincomp0000reil/page/164 164]}}</ref><ref>{{cite book|url=https://archive.org/details/ibms360early370s0000pugh|url-access=registration|title=IBM's 360 and early 370 systems|last1=W. Pugh|first1=Emerson|last2=R. Johnson|first2=Lyle|last3=H. Palmer|first3=John|year=1991|publisher=MIT Press|isbn=0262161230|page=[https://archive.org/details/ibms360early370s0000pugh/page/706 706]|access-date=9 December 2015}}</ref> Practical magnetic-core memory was developed by [[Biography:An Wang|An Wang]] in 1948, and improved by Jay Forrester and Jan A. Rajchman in the early 1950s, before being commercialised with the [[Engineering:Whirlwind I|Whirlwind]] computer in 1953.<ref>{{cite web|title=1953: Whirlwind computer debuts core memory|url=https://www.computerhistory.org/storageengine/whirlwind-computer-debuts-core-memory/|website=Computer History Museum|access-date=2 August 2019}}</ref> Ken Olsen also contributed to its development.<ref>{{Cite book|url=https://books.google.com/books?id=rfsvbXyn0ZEC&q=jay+forrester&pg=PA25|title=Computerworld: Mass. Town has become computer capital|last=Taylor|first=Alan|date=18 June 1979|publisher=IDG Enterprise|pages=25}}</ref>

[[Engineering:Semiconductor memory|Semiconductor memory]] began in the early 1960s with bipolar memory cells, made of [[Engineering:Bipolar junction transistor|bipolar transistors]]. While it improved performance, it could not compete with the lower price of magnetic-core memory.<ref name="computerhistory1966">{{cite web|title=1966: Semiconductor RAMs serve high-speed storage needs|url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/|website=Computer History Museum |access-date=19 June 2019}}</ref>

=== MOS memory cells ===
{{See|Semiconductor memory|Random-access memory#History}}
[[File:Intel C1103.jpg|thumb|260px|[[Intel 1103|Intel 1103]], a 1970 metal-oxide-semiconductor (MOS) [[Dynamic random-access memory|dynamic random-access memory]] (DRAM) chip.]]

The invention of the [[Engineering:MOSFET|MOSFET]] (metal–oxide–semiconductor field-effect transistor), also known as the MOS transistor, by Mohamed M. Atalla and [[Biography:Dawon Kahng|Dawon Kahng]] at [[Organization:Bell Labs|Bell Labs]] in 1959,<ref name="computerhistory">{{cite journal|url=https://www.computerhistory.org/siliconengine/metal-oxide-semiconductor-mos-transistor-demonstrated/|title=1960 - Metal oxide semiconductor (MOS) transistor demonstrated|journal=The Silicon Engine|publisher=Computer history museum}}</ref> enabled the practical use of [[Engineering:MOSFET|metal–oxide–semiconductor]] (MOS) transistors as memory cell storage elements, a function previously served by [[Magnetic-core memory|magnetic cores]].<ref name="sciencedirect">{{cite web|title=Transistors - an overview|url=https://www.sciencedirect.com/topics/computer-science/transistors|website=[[ScienceDirect]]|access-date=8 August 2019}}</ref> The first modern memory cells were introduced in 1964, when John Schmidt designed the first 64-bit p-channel MOS ([[PMOS logic|PMOS]]) [[Static random-access memory|static random-access memory]] (SRAM).<ref name="computerhistory1970"/><ref>{{Cite book|url=https://books.google.com/books?id=kG4rAQAAIAAJ&q=John+Schmidt|title=Solid state design - vol. 6|year=1965|publisher=Horizon house}}</ref>

SRAM typically has six-[[Engineering:Transistor|transistor]] cells, whereas [[Dynamic random-access memory|DRAM]] (dynamic random-access memory) typically has single-transistor cells.<ref name="shmj-mos">{{cite web|title=Late 1960s: Beginnings of MOS memory|url=http://www.shmj.or.jp/english/pdf/ic/exhibi718E.pdf|website=Semiconductor history museum of Japan|date=23 January 2019|access-date=27 June 2019}}</ref><ref name="computerhistory1970">{{cite web|title=1970: Semiconductors compete with magnetic cores|url=https://www.computerhistory.org/storageengine/semiconductors-compete-with-magnetic-cores/|website=Computer history museum|access-date=19 June 2019}}</ref> In 1965, [[Company:Toshiba|Toshiba]]'s Toscal BC-1411 [[Engineering:Calculator|electronic calculator]] used a form of capacitive bipolar DRAM, storing 180-bit data on discrete memory cells, consisting of [[Chemistry:Germanium|germanium]] bipolar transistors and capacitors.<ref name="bc-spec">{{cite web|url=http://www.oldcalculatormuseum.com/s-toshbc1411.html|title=Spec sheet for Toshiba "TOSCAL" BC-1411|website=Old calculator web museum|access-date=8 May 2018|url-status=live|archive-url=https://web.archive.org/web/20170703071307/http://www.oldcalculatormuseum.com/s-toshbc1411.html|archive-date=3 July 2017}}</ref><ref name="bc">{{Cite web|url=http://www.oldcalculatormuseum.com/toshbc1411.html|title=Toshiba "Toscal" BC-1411 desktop calculator|archive-url=https://web.archive.org/web/20070520202433/http://www.oldcalculatormuseum.com/toshbc1411.html|archive-date=20 May 2007}}</ref> MOS technology is the basis for modern DRAM. In 1966, Robert H. Dennard at the [[Organization:Thomas J. Watson Research Center|IBM Thomas J. Watson Research Center]] was working on MOS memory. While examining the characteristics of MOS technology, he found it was capable of building [[Engineering:Capacitor|capacitor]]s, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell.<ref name="ibm100">{{cite web|title=DRAM|url=https://www.ibm.com/ibm/history/ibm100/us/en/icons/dram|website=IBM100|publisher=[[Company:IBM|IBM]]|access-date=20 September 2019|date=9 August 2017}}</ref> In 1967, Dennard filed a patent for a single-transistor DRAM memory cell, based on MOS technology.<ref>{{cite web|title=Robert Dennard|url=https://www.britannica.com/biography/Robert-Dennard|website=[[Encyclopædia Britannica]]|access-date=8 July 2019}}</ref>

The first commercial bipolar 64-bit [[Static random-access memory|SRAM]] was released by [[Company:Intel|Intel]] in 1969 with the 3101 [[Engineering:Schottky transistor|Schottky]] [[Transistor–transistor logic|TTL]]. One year later, it released the first DRAM [[Engineering:Integrated circuit|integrated circuit]] chip, the [[Intel 1103]], based on MOS technology. By 1972, it beat previous records in [[Engineering:Semiconductor memory|semiconductor memory]] sales.<ref>{{Cite book|url=https://books.google.com/books?id=n76xqO7ZzsQC&pg=PA131|title=Encyclopedia of microcomputers: volume 9 - Icon programming language to knowledge-based systems: APL techniques|last1=Kent|first1=Allen|last2=Williams|first2=James G.|date=6 January 1992|publisher=CRC press|isbn=9780824727086|pages=131}}</ref> DRAM chips during the early 1970s had three-transistor cells, before single-transistor cells became standard since the mid-1970s.<ref name="shmj-mos"/><ref name="computerhistory1970"/>

[[Engineering:CMOS|CMOS]] memory was commercialized by [[Company:RCA|RCA]], which launched a 288-bit CMOS SRAM memory chip in 1968.<ref name="computerhistory1963">{{cite web|title=1963: Complementary MOS circuit configuration is invented|url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/|website=Computer history museum|access-date=6 July 2019}}</ref> CMOS memory was initially slower than [[NMOS logic|NMOS]] memory, which was more widely used by computers in the 1970s.<ref name="shmj"/> In 1978, [[Company:Hitachi|Hitachi]] introduced the twin-well CMOS process, with its HM6147 (4{{nbsp}}kb SRAM) memory chip, manufactured with a 3 µm process. The HM6147 chip was able to match the performance of the fastest NMOS memory chip at the time, while the HM6147 also consumed significantly less power. With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most common [[Engineering:Semiconductor device fabrication|semiconductor manufacturing process]] for computer memory in the 1980s.<ref name="shmj">{{cite web|title=1978: Double-well fast CMOS SRAM (Hitachi)|url=http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf|website=Semiconductor history museum of Japan|access-date=5 July 2019|archive-url=https://web.archive.org/web/20190705234921/http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf|archive-date=5 July 2019|url-status=live}}</ref>

The two most common types of DRAM memory cells since the 1980s have been trench-capacitor cells and stacked-capacitor cells.<ref name="stol"/> Trench-capacitor cells are where holes (trenches) are made in a silicon substrate, whose side walls are used as a memory cell, whereas 
stacked-capacitor cells are the earliest form of three-dimensional memory (3D memory), where memory cells are stacked vertically in a three-dimensional cell structure.<ref>{{cite web|title=1980s: DRAM capacity increases, the shift to CMOS advances, and Japan dominates the market|url=http://www.shmj.or.jp/english/pdf/ic/exhibi746E.pdf|website=Semiconductor history museum of Japan|access-date=19 July 2019}}</ref> Both debuted in 1984, when Hitachi introduced trench-capacitor memory and [[Company:Fujitsu|Fujitsu]] introduced stacked-capacitor memory.<ref name="stol"/>

=== Floating-gate MOS memory cells ===

The [[Engineering:Floating-gate MOSFET|floating-gate MOSFET]] (FGMOS) was invented by [[Biography:Dawon Kahng|Dawon Kahng]] and Simon Sze at [[Organization:Bell Labs|Bell Labs]] in 1967.<ref>{{cite journal |first1=D. |last1=Kahng |first2=S.M. |last2=Sze |title=A floating-gate and its application to memory devices |journal=The Bell System Technical Journal |volume=46 |issue=6 |year=1967 |pages=1288–95 |doi=10.1002/j.1538-7305.1967.tb01738.x}}</ref> They proposed the concept of floating-gate memory cells, using FGMOS transistors, which could be used to produce [[Engineering:EPROM|reprogrammable ROM]] (read-only memory).<ref name="computerhistory1971">{{cite web |title=1971: Reusable semiconductor ROM introduced |url=https://www.computerhistory.org/storageengine/reusable-semiconductor-rom-introduced/ |website=Computer history museum |access-date=19 June 2019}}</ref> Floating-gate memory cells later became the basis for [[Non-volatile memory|non-volatile memory]] (NVM) technologies including [[Engineering:EPROM|EPROM]] (erasable programmable ROM), [[EEPROM]] (electrically erasable programmable ROM) and [[Flash memory|flash memory]].<ref name="Bez">{{cite book|last1=Bez|first1=R.|last2=Pirovano|first2=A.|title=Advances in non-volatile memory and storage technology|year=2019|publisher=[[Company:Woodhead Publishing|Woodhead Publishing]]|isbn=9780081025857}}</ref>

Flash memory was invented by Fujio Masuoka at [[Company:Toshiba|Toshiba]] in 1980.<ref>{{cite web|last=Fulford|first=Benjamin|title=Unsung hero|work=Forbes|date=24 June 2002|access-date=18 March 2008|url=https://www.forbes.com/global/2002/0624/030.html|url-status=live|archive-url=https://web.archive.org/web/20080303205125/http://www.forbes.com/global/2002/0624/030.html|archive-date=3 March 2008|df=dmy-all}}</ref><ref>{{patent|US|4531203|Fujio Masuoka}}</ref> Masuoka and his colleagues presented the invention of NOR flash in 1984,<ref>{{cite web|title=Toshiba: Inventor of flash memory|url=http://www.flash25.toshiba.com|website=[[Company:Toshiba|Toshiba]]|access-date=20 June 2019|url-status=dead|archive-url=https://web.archive.org/web/20190620160642/http://www.flash25.toshiba.com/|archive-date=20 June 2019}}</ref> and then NAND flash in 1987.<ref>{{cite conference|title=New ultra high density EPROM and flash EEPROM with NAND structure cell|last1=Masuoka|first1=F.|last2=Momodomi|first2=M.|last3=Iwata|first3=Y.|last4=Shirota|first4=R.|year=1987|conference=IEDM 1987|book-title=Electron Devices Meeting, 1987 International|publisher=[[Organization:Institute of Electrical and Electronics Engineers|IEEE]]|df=dmy|doi=10.1109/IEDM.1987.191485}}</ref> [[Multi-level cell]] (MLC) flash memory was introduced by [[Company:NEC|NEC]], which demonstrated [[Multi-level cell#Quad-level cell|quad-level cell]]s in a 64{{nbsp}}[[Mebibit|Mb]] flash chip storing 2-bit per cell in 1996.<ref name="stol">{{cite web|title=Memory|url=http://maltiel-consulting.com/Semiconductor_technology_memory.html|website=Semiconductor technology online (STOL)|access-date=25 June 2019}}</ref> 3D V-NAND, where flash memory cells are stacked vertically using 3D [[Charge trap flash|charge trap flash]] (CTP) technology, was first announced by Toshiba in 2007,<ref>{{cite news|title=Toshiba announces new "3D" NAND flash technology|url=https://www.engadget.com/2007/06/12/toshiba-announces-new-3d-nand-flash-technology/|access-date=10 July 2019|work=[[Software:Engadget|Engadget]]|date=12 June 2007}}</ref> and first commercially manufactured by [[Company:Samsung Electronics|Samsung Electronics]] in 2013.<ref>{{Cite web|url=https://www.samsung.com/semiconductor/insights/news-events/samsung-introduces-worlds-first-3d-v-nand-based-ssd-for-enterprise-applications/|title=Samsung introduces world's first 3D V-NAND based SSD for enterprise applications|website=Samsung semiconductor global website|url-status=dead|archive-url=https://web.archive.org/web/20210415035436/https://www.samsung.com/semiconductor/newsroom/news-events/samsung-introduces-worlds-first-3d-v-nand-based-ssd-for-enterprise-applications/|archive-date=15 April 2021}}</ref><ref>{{Cite web|url=https://www.eetimes.com/samsung-confirms-24-layers-in-3d-nand/|title=Samsung confirms 24 layers in 3D NAND|first=Peter|last=Clarke|website=EE Times |date=2013}}</ref>

== Implementation ==
The following schematics detail the three most used implementations for memory cells: 
* The dynamic random access memory cell (DRAM);
* The static random access memory cell (SRAM);
* Flip-flops like the J/K shown below, using only [[Engineering:Logic gate|logic gate]]s.

{| style="text-align:center; margin: 1em auto 1em auto"
|[[File:DRAM Cell Structure (Model of Single Circuit Cell).PNG|thumb|DRAM cell (1 transistor and one capacitor).]]||thumb|SRAM cell (6 transistors).||[[File:FlipflopJKlogic.png|thumb|Clocked J/K flip-flop.]]
|}

==Operation==

===DRAM memory cell===
[[Image:MT4C1024-HD.jpg|thumb|right|upright=1.8|[[Engineering:Die (integrated circuit)|Die]] of the MT4C1024 (1994) integrating one-[[Mebibit|mebibit]] of [[Dynamic random-access memory|DRAM]] memory cells.]]

====Storage====
:The storage element of the [[Dynamic random-access memory|DRAM]] memory cell is the [[Engineering:Capacitor|capacitor]] labeled (4) in the diagram above. The charge stored in the capacitor degrades over time, so its value must be refreshed (read and rewritten) periodically. The [[Engineering:MOSFET|nMOS]] transistor (3) acts as a gate to allow reading or writing when open or storing when closed.<ref>{{Cite book|url=https://books.google.com/books?id=SrP3aWed-esC&pg=PA355|title=Memory systems: Cache, DRAM, disk|last1=Jacob|first1=Bruce|last2=Ng|first2=Spencer|last3=Wang|first3=David|date=28 July 2010|publisher=Morgan Kaufmann|isbn=9780080553849|pages=355}}</ref>

====Reading====

:For reading the Word line (2) drives a logic 1 (voltage high) into the gate of the [[Engineering:MOSFET|nMOS]] transistor (3) which makes it conductive and the charge stored at the capacitor (4) is then transferred to the bit line (1). The bit line will have a [[Engineering:Parasitic capacitance|parasitic capacitance]] (5) that will drain part of the charge and slow the reading process. The capacitance of the bit line will determine the needed size of the storage capacitor (4). It is a trade-off. If the storage capacitor is too small, the voltage of the bit line would take too much time to raise or not even rise above the threshold needed by the amplifiers at the end of the bit line. Since the reading process degrades the charge in the storage capacitor (4) its value is rewritten after each read.<ref name=":0">{{Cite book|url=https://books.google.com/books?id=z-WTTkQEVfwC&pg=PA10|title=Dynamic RAM: Technology advancements|last=Siddiqi|first=Muzaffer A.|date=19 December 2012|publisher=CRC Press|isbn=9781439893739|pages=10}}</ref>

====Writing====

:The writing process is the easiest, the desired value logic 1 (high voltage) or logic 0 (low voltage) is driven into the bit line. The word line activates the [[Engineering:MOSFET|nMOS]] transistor (3) connecting it to the storage capacitor (4). The only issue is to keep it open enough time to ensure that the capacitor is fully charged or discharged before turning off the nMOS transistor (3).<ref name=":0" />

===SRAM memory cell===
[[File:SRAM Cell Inverter Loop.png|thumb|260px|SRAM memory cell depicting Inverter Loop as gates]]
[[File:SRLatch-lowres.gif|thumb|260px|An animated SR latch. Black and white mean logical '1' and '0', respectively. <br />
(A) S = 1, R = 0: set <br />
(B) S = 0, R = 0: hold <br />
(C) S = 0, R = 1: reset <br />
(D) S = 1, R = 1: not allowed <br />
Transitioning from the restricted combination (D) to (A) leads to an unstable state.]]
====Storage====
:The working principle of [[Static random-access memory|SRAM]] memory cell can be easier to understand if the transistors M1 through M4 are drawn as [[Engineering:Logic gate|logic gate]]s. That way it is clear that at its heart, the cell storage is built by using two cross-coupled [[Engineering:Inverter (logic gate)|inverter]]s. This simple loop creates a bi-stable circuit. A logic 1 at the input of the first inverter turns into a 0 at its output, and it is fed into the second inverter which transforms that logic 0 back to a logic 1 feeding back the same value to the input of the first inverter. That creates a stable state that does not change over time. Similarly the other stable state of the circuit is to have a logic 0 at the input of the first inverter. After been inverted twice it will also feedback the same value.<ref name=":1">{{Cite book|url=https://books.google.com/books?id=8pfLBQAAQBAJ&pg=PA6|title=Nonvolatile memory design: Magnetic, resistive, and phase change|last1=Li|first1=Hai|last2=Chen|first2=Yiran|date=19 April 2016|publisher=CRC press|isbn=9781439807460|pages=6, 7}}</ref> 
: Therefore there are only two stable states that the circuit can be in:
:* <math>\scriptstyle Q</math> = 0 and &nbsp; <math>\scriptstyle \overline{Q}</math> = 1
:* <math>\scriptstyle Q</math> = 1 and &nbsp; <math>\scriptstyle \overline{Q}</math> = 0

====Reading====

:To read the contents of the memory cell stored in the loop, the transistors M5 and M6 must be turned on. when they receive voltage to their gates from the word line (<math>\scriptstyle WL</math>), they become conductive and so the <math>\scriptstyle Q</math> and &nbsp;<math>\scriptstyle \overline{Q}</math> &nbsp;values get transmitted to the bit line (<math>\scriptstyle BL</math>) and to its complement (<math>\scriptstyle \overline{BL}</math>).<ref name=":1"/> Finally this values get amplified at the end of the bit lines.<ref name=":1"/>

====Writing====

:The writing process is similar, the difference is that now the new value that will be stored in the memory cell is driven into the bit line (<math>\scriptstyle BL</math>) and the inverted one into its complement (<math>\scriptstyle \overline{BL}</math>). Next transistors M5 and M6 are open by driving a logic 1 (voltage high) into the word line (<math>\scriptstyle WL</math>). This effectively connects the bit lines to the by-stable inverter loop. There are two possible cases:
:# If the value of the loop is the same as the new value driven, there is no change;
:# if the value of the loop is different from the new value driven there are two conflicting values, in order for the voltage in the bit lines to overwrite the output of the inverters, the size of the M5 and M6 transistors must be larger than that of the M1-M4 transistors. This allows more current to flow through first ones and therefore tips the voltage in the direction of the new value, at some point the loop will then amplify this intermediate value to full rail.<ref name=":1"/>

===Flip-flop===
{{Main|Engineering:Flip-flop (electronics)}}

The [[Engineering:Flip-flop (electronics)|flip-flop]] has many different implementations, its storage element is usually a latch consisting of a [[Engineering:NAND gate|NAND gate]] loop or a [[Engineering:NOR gate|NOR gate]] loop with additional gates used to implement clocking. Its value is always available for reading as an output. The value remains stored until it is changed through the set or reset process. Flip-flops are typically implemented using [[Engineering:MOSFET|MOSFET]]s.

===Floating gate===
[[Image:Flash cell structure.svg|thumb|260px|right|A flash memory cell]]

[[Engineering:Floating-gate MOSFET|Floating-gate]] memory cells, based on [[Engineering:Floating-gate MOSFET|floating-gate MOSFET]]s, are used for most [[Non-volatile memory|non-volatile memory]] (NVM) technologies, including [[Engineering:EPROM|EPROM]], [[EEPROM]] and [[Flash memory|flash memory]].<ref name="Bez"/> According to R. Bez and A. Pirovano:

{{quote|A floating-gate memory cell is basically an [[Engineering:MOSFET|MOS]] transistor with a gate completely surrounded by dielectrics (Fig. 1.2), the floating-gate (FG), and electrically governed by a capacitive-coupled control-gate (CG). Being electrically isolated, the FG acts as the storing electrode for the cell device. Charge injected into the FG is maintained there, allowing modulation of the ‘apparent’ threshold voltage (i.e. VT seen from the CG) of the cell transistor.<ref name="Bez"/>}}

== See also ==
* [[Dynamic random-access memory]]
* [[Engineering:Flip-flop (electronics)|Flip-flop (electronics)]]
* [[Row hammer]]
* [[Static random-access memory]]

== References ==
{{reflist|2}}
{{Digital electronics}}
{{Electronic components}}
[[Category:Computer memory]]
[[Category:Digital electronics]]
[[Category:Digital systems]]
[[Category:Electronic engineering]]

{{Sourceattribution|Memory cell (computing)}}