View source for RISC-V assembly language

{{Infobox file format
| name = RISC-V assembly language
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| developer = RISC-V Foundation
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| type = [[Assembly language]]
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| url = {{URL|https://riscv.org/specifications/ratified/}}
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'''RISC-V assembly language''' is a [[Low-level programming language|low-level programming language]] that is used to produce [[Object code|object code]] for the [[Engineering:RISC-V|RISC-V]] class of processors. Assembly languages are closely tied to the architecture's machine code instructions, allowing for precise control over hardware.

Assemblers include [[Software:GNU Assembler|GNU Assembler]] and [[Software:LLVM|LLVM]].

== Keywords ==
Reserved keywords of RISC-V assembly language.
{{columns-list
| colwidth=5em;
| {{bulleted list
| {{Mono|add}}
| {{Mono|addi}}
| {{Mono|and}}
| {{Mono|andi}}
| {{Mono|beq}}
| {{Mono|bge}}
| {{Mono|bgeu}}
| {{Mono|blt}}
| {{Mono|bltu}}
| {{Mono|bne}}
| {{Mono|lb}}
| {{Mono|lbu}}
| {{Mono|lh}}
| {{Mono|lhu}}
| {{Mono|lw}}
| {{Mono|or}}
| {{Mono|ori}}
| {{Mono|sb}}
| {{Mono|sh}}
| {{Mono|sll}}
| {{Mono|slli}}
| {{Mono|slt}}
| {{Mono|slti}}
| {{Mono|sltiu}}
| {{Mono|sltu}}
| {{Mono|sra}}
| {{Mono|srai}}
| {{Mono|srl}}
| {{Mono|srli}}
| {{Mono|sub}}
| {{Mono|sw}}
| {{Mono|xor}}
| {{Mono|xori}}
}}
}}

== Mnemonics and opcodes ==
Each instruction in the RISC-V assembly language is represented by a [[Biology:Mnemonic|mnemonic]] which often combines with one or more operands to translate into one or more bytes known as an [[Opcode|opcode]].

== Registers ==
RISC-V processors feature a set of registers that serve as storage for binary data and addresses during program execution. These registers are categorized into integer registers and floating-point registers.

== Instruction types ==
RISC-V instructions use variable-length encoding.

Extensions:
* atomic instructions
* single-precision floating-point
* double-precision floating-point
* bit manipulation
* cryptography
* hypervisor
* supervisor
* packed-SIMD instructions
* vector

=== Floating-point instructions ===
RISC-V assembly language includes instructions for a [[Floating-point unit|floating-point unit]] (FPU).

=== SIMD instructions ===
These largely perform the same operation in parallel on many values.

== Program flow ==
The RISC-V assembly has conditional branch instructions based on comparison: {{Code|beq}} (equal), {{Code|bne}} (not equal), {{Code|blt}} (less than, signed), {{Code|bltu}} (less than, unsigned), {{Code|bge}} (greater than or equal, signed), and {{Code|bgeu}} (greater than or equal, unsigned).

== Examples ==
<syntaxhighlight lang="asm">
.section .text
.globl _start
_start:
	    lui  a1,      %hi(msg)       # load msg(hi)
	    addi a1, a1,  %lo(msg)       # load msg(lo)
	    jalr ra, puts
2:	    j    2b

.section .rodata
msg:
	    .string "Hello World\n"
</syntaxhighlight>

== See also ==
* [[Assembly language]]
* RISC-V instruction listings
* CPU design
* List of assemblers
* [[X86 assembly language|x86 assembly language]]

== External links ==
* [https://ripes.me/ Ripes]{{snd}} A graphical processor simulator and assembly editor
* [https://venus.kvakil.me/ venus]{{snd}} A instruction set simulator ({{GitHub|kvakil/venus}})
* {{GitHub|TheThirdOne/rars}}

{{RISC-V}}

[[Category:Assembly languages]]

{{Sourceattribution|RISC-V assembly language}}