View source for Serial Peripheral Interface

{{Short description|Synchronous serial communication interface}}
{{recentism|date=December 2023}}
{{Infobox connector <!-- NOTE: Not a perfect template match, but good enough for now -->
| name = Serial Peripheral Interface (SPI)
| type = [[Serial communication]] [[Engineering:Bus (computing)|bus]]
| designer = [[Company:Motorola|Motorola]]
| data_style = Full-duplex [[Serial communication|serial]]
| daisy_chain = Depends on devices
| manufacturer = various
| data_devices = Multidrop limited by chip selects. Daisy chaining unlimited.
| data_bit_width = 1 bit (bidirectional)
| high_freq = yes
| pin_custom1_name = MOSI
| pin_name_custom1 = Main Out Sub In
| pin_name_custom2 = Main In Sub Out
| pin_custom2_name = MISO
| pin_custom3_name = SCLK
| pin_custom4_name = {{Overline|CS}}
| pin_name_custom3 = Serial Clock
| pin_name_custom4 = Chip Select (one or more)
| pinout_notes = (pins may have alternative names)
| maximum_voltage = Unspecified
| maximum_current = Unspecified
| physical_connector = Unspecified
| design_date = Around early 1980s{{NoteTag|The earliest definitive mention of a "Serial Peripheral Interface" in bitsavers archives of Motorola manuals is from 1983 (see {{slink||Original definition}}). While some sources on the web allege that Motorola introduced SPI when 68000 was introduced in 1979, however many of those appear to be citogenesis or speculation, and Motorola's 1983 68000 manual has no mention of "Serial Peripheral Interface", so the alleged 1979 date doesn't seem to be reliable information. Please only add a specific design_date if you have a definitive source from Motorola around then.}}
}}

'''Serial Peripheral Interface''' ('''SPI''') is a [[Engineering:De facto standard|''de facto'' standard]] (with many variants) for [[Comparison of synchronous and asynchronous signalling|synchronous]] [[Serial communication|serial communication]], used primarily in embedded systems for short-distance wired communication between integrated circuits.

SPI uses a [[Engineering:Master–slave (technology)|master–slave architecture]], described here with the terms "main" and "sub",{{NoteTag|The {{slink||Alternative terminology}} section gives more details on proposed alternative terminology. See the talk page for an ongoing discussion.}} <ref name=":0">{{Cite web |last=Dhaker |first=Piyu |date=2018 |title=Introduction to SPI Interface |url=https://www.analog.com/en/analog-dialogue/articles/introduction-to-spi-interface.html |url-status=live |archive-url=https://web.archive.org/web/20230525152752/https://www.analog.com/en/analog-dialogue/articles/introduction-to-spi-interface.html |archive-date=2023-05-25 |access-date=2023-07-21 |website=Analog Dialogue}}</ref> where one{{NoteTag|For any given transaction, only one device is the main. However, some devices support changing main and sub roles on the fly. Most microcontrollers can easily reconfigure their SPI's role, and some Atmel and Silabs devices can change roles depending on an external pin.}} main device [[Engineering:Signaling (telecommunications)|orchestrates communication]] with some number of peripheral (sub) devices by driving the [[Clock signal|clock signal]] and [[Engineering:Chip select|chip select]] signal(s).

[[Company:Motorola|Motorola]]'s original specification uses four [[Engineering:Wire|wires]] to perform full duplex communication. It is sometimes called a ''four-wire'' [[Serial bus|serial bus]] to contrast with [[Serial Peripheral Interface#Three-wire|three-wire]] variants which are half duplex, and with the ''two-wire'' [[I²C]] and [[1-Wire|1-Wire]] serial buses.

Typical applications include interfacing microcontrollers with peripheral chips for [[Secure Digital]] cards, liquid crystal displays, analog-to-digital and digital-to-analog converters, [[Flash memory#Serial flash|flash]] and [[EEPROM#Serial bus devices|EEPROM]] memory, and various communication chips.

SPI may be accurately described as a synchronous serial interface,<ref>{{cite web |url= https://digital.ni.com/public.nsf/allkb/862567530005F09C862566BE004E469D |title= What is Serial Synchronous Interface (SSI)? |access-date= 2015-01-28 }}</ref> but it is different from the [[Synchronous Serial Interface]] (SSI) protocol.{{NoteTag|While [[Synchronous Serial Interface]] (SSI) is also a four-wire synchronous serial communication protocol, the SSI protocol employs [[Engineering:Differential signaling|differential signaling]] and provides only a single [[Engineering:Simplex communication|simplex communication]] channel.}}

==Operation==
''<small>(Note: Variations section describes operation of non-standard variants.)</small>''
[[File:SPI basic operation, single Main & Sub.svg|thumb|368x368px|Figure 1: Basic SPI configuration using a single main and a single sub. Each device internally uses a [[Shift register|shift register]] for serial communication, which together forms an inter-chip [[Circular buffer|circular buffer]].]]
SPI has four logic signals (which may have alternative names):
* SCLK : Serial Clock ([[Clock signal|clock signal]] from main)
* MOSI : Main Out Sub In (data output from main)
* MISO : Main In Sub Out (data output from sub)
* {{Overline|CS}} : {{Overline|Chip Select}} ([[Engineering:Logic level|active low]] signal from main to address subs and initiate transmission)

MOSI on a main outputs to MOSI on a sub. MISO on a sub outputs to MISO on a main.

SPI operates with a single device acting as main and with one or more sub devices.

Sub devices should use tri-state outputs so their MISO signal becomes [[Engineering:High impedance|high impedance]] (''electrically disconnected'') when the device is not selected. Subs without tri-state outputs cannot share a MISO wire with other subs without using an external tri-state buffer.

===Data transmission===
To begin communication, the SPI main first selects a sub device by pulling its {{Overline|CS}} low. (Note: the bar above {{Overline|CS}} indicates it is an active low signal, so a low voltage means "selected", while a high voltage means "not selected")

If a waiting period is required, such as for an analog-to-digital conversion, the main must wait for at least that period of time before issuing clock cycles.{{NoteTag|Some subs require a falling edge of the {{Overline|Chip Select}} signal to initiate an action. An example is the Maxim MAX1242 ADC, which starts conversion on a high→low transition.}}

During each SPI clock cycle, full-duplex transmission of a single bit occurs. The main sends a bit on the MOSI line while the sub sends a bit on the MISO line, and then each reads their corresponding incoming bit. This sequence is maintained even when only one-directional data transfer is intended.

Transmission using a single sub (Figure 1) involves one shift register in the main and one shift register in the sub, both of some given word size (e.g. 8 bits),{{NoteTag|Transmissions often consist of eight-bit words. However, other word-sizes are also common, for example, sixteen-bit words for touch-screen controllers or audio codecs, such as the TSC2101 by Texas Instruments, or twelve-bit words for many digital-to-analog or analog-to-digital converters.}} connected in a virtual ring topology. Data is usually shifted out with the most-significant bit (MSB) first.{{NoteTag|The original specification has a LSBFE ("LSB-First Enable") to control whether data is transferred least (LSB) or most significant bit (MSB) first.}} On the clock edge, both main and sub shift out a bit to its counterpart. On the next clock edge, each receiver samples the transmitted bit and stores it in the shift register as the new least-significant bit. After all bits have been shifted out and in, the main and sub have exchanged register values. If more data needs to be exchanged, the shift registers are reloaded and the process repeats. Transmission may continue for any number of clock cycles. When complete, the main stops toggling the clock signal, and typically deselects the sub.

If a single sub device is used, its {{Overline|CS}} pin ''may'' be fixed to [[Engineering:Logic level|logic low]] if the sub permits it. With multiple sub devices, a multidrop configuration requires an independent {{Overline|CS}} signal from the main for each sub device, while a daisy-chain configuration only requires one {{Overline|CS}} signal.

Every sub on the bus that has not been selected should disregard the input clock and MOSI signals. And to prevent [[Engineering:Bus contention|contention]] on MISO, non-selected subs must use [[Three-state logic|tristate]] output. Subs that aren't already tristate will need external tristate buffers to ensure this.<ref name="Better SPI Bus Design in 3 Steps" />

===Clock polarity and phase===
In addition to setting the clock frequency, the main must also configure the clock polarity and phase with respect to the data. Motorola<ref>[https://web.archive.org/web/20150413003534/http://www.ee.nmt.edu/~teare/ee308l/datasheets/S12SPIV3.pdf SPI Block Guide v3.06; Motorola/Freescale/NXP; 2003.]</ref><ref name=":4" /> named these two options as CPOL and CPHA (for '''c'''lock '''pol'''arity and '''c'''lock '''pha'''se) respectively, a convention most vendors have also adopted.

[[File:SPI timing diagram CS.svg|thumb|338x338px|SPI [[Digital timing diagram|timing diagram]] for both clock polarities and phases. Data bits output on blue lines if CPHA=0, or on red lines if CPHA=1, and sample on opposite-colored lines. Numbers identify data bits. Z indicates high impedance.]]

The SPI [[Digital timing diagram|timing diagram]] shown is further described below:
* CPOL represents the polarity of the clock. Polarities can be converted with a simple [[Engineering:Inverter (logic gate)|inverter]].
** SCLK{{Subscript|1=CPOL=0}} is a clock which idles at the logical low voltage.
** SCLK{{Subscript|1=CPOL=1}} is a clock which idles at the logical high voltage.
* CPHA represents the [[Physics:Phase (waves)|phase]] of each data bit's transmission cycle relative to SCLK.
** For CPHA=0:
*** The first data bit is outputted ''immediately'' when {{Overline|CS}} activates.
*** Subsequent bits are outputted when SCLK transitions ''to'' its idle voltage level.
*** Sampling occurs when SCLK transitions ''from'' its idle voltage level.
** For CPHA=1:
*** The first data bit is outputted on SCLK's first clock edge ''after'' {{Overline|CS}} activates.
*** Subsequent bits are outputted when SCLK transitions ''from'' its idle voltage level.
*** Sampling occurs when SCLK transitions ''to'' its idle voltage level.
** Conversion between these two phases is non-trivial.
** Note: MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next bit's transmission cycle starts, so SPI main and sub devices may sample data at different points in that half cycle, for flexibility, despite the original specification.

===Mode numbers ===
The combinations of polarity and phases are referred to by these "SPI mode" numbers with CPOL as the high order bit and CPHA as the low order bit:
{| class="wikitable"
|-
! SPI mode
! Clock polarity<br>(CPOL)
! Clock phase<br>(CPHA)
!Data is shifted out on
! Data is sampled on
|-
| 0 || 0 || 0 
|falling SCLK, and when {{Overline|CS}} activates || rising SCLK
|-
| 1 || 0 || 1 
| rising SCLK || falling SCLK
|-
| 2 || 1 || 0 
| rising SCLK, and when {{Overline|CS}} activates || falling SCLK
|-
| 3 || 1 || 1 
|falling SCLK|| rising SCLK
|}

Notes:

* Another commonly used notation represents the mode as a (CPOL, CPHA) tuple; e.g., the value '(0, 1)' would indicate CPOL=0 and CPHA=1.
* In Full Duplex operation, the main device could transmit and receive with different modes. For instance, it could transmit in Mode 0 and be receiving in Mode 1 at the same time.
* Different vendors may use different naming schemes, like CKE for clock edge or NCPHA for the inversion of CPHA.

=== Valid communications ===
Some sub devices are designed to ignore any SPI communications in which the number of clock pulses is greater than specified. Others do not care, ignoring extra inputs and continuing to shift the same output bit. It is common for different devices to use SPI communications with different lengths, as, for example, when SPI is used to access an IC's scan chain by issuing a command word of one size (perhaps 32 bits) and then getting a response of a different size (perhaps 153 bits, one for each pin in that scan chain).

===Interrupts===
Interrupts are outside the scope of SPI; their usage is neither forbidden nor specified, and so may optionally be implemented.

==== From main to sub ====
Microcontrollers configured as sub devices may have hardware support for generating interrupt signals to themselves when data words are received or overflow occurs in a receive [[FIFO (computing and electronics)|FIFO]] buffer,<ref>{{Cite web |date=2002 |title=TMS320x281x Serial Peripheral Interface Reference Guide |url=https://www.ti.com/lit/pdf/spru059 |website=[[Company:Texas Instruments|Texas Instruments]] |pages=16–17}}</ref> and may also set up an interrupt routine when their chip select input line is pulled low or high.

==== From sub to main ====
SPI subs sometimes use an out-of-band signal (another wire) to send an interrupt signal to a main. Examples include pen-down interrupts from [[Engineering:Touchscreen|touchscreen]] sensors, thermal limit alerts from [[Physics:List of temperature sensors|temperature sensors]], alarms issued by [[Engineering:Real-time clock|real-time clock]] chips, [[Secure Digital#SDIO|SDIO]]{{NoteTag|Not to be confused with the SDIO (Serial Data I/O) line of the half-duplex implementation of SPI sometimes also called "3-wire" SPI. Here e.g. MOSI (via a resistor) and MISO (no resistor) of a main is connected to the SDIO line of a sub.|name=3wireSDI}} and audio jack insertions for an [[Audio codec|audio codec]]. Interrupts to main may also be faked by using [[Polling (computer science)|polling]] (similarly to USB 1.1 and 2.0).

===Software design===
SPI lends itself to a "bus driver" software design. Software for attached devices is written to call a "bus driver" that handles the actual low-level SPI hardware. This permits the driver code for attached devices to port easily to other hardware or a bit-banging software implementation.

===Bit-banging the protocol===
The [[Pseudocode|pseudocode]] below outlines a software-implementation ("bit-banging") of SPI's protocol as a main with simultaneous output and input. This pseudocode is for CPHA=0 and CPOL=0, thus SCLK is pulled low before {{Overline|CS}} is activated and bits are inputted on SCLK's rising edge while bits are outputted on SCLK's falling edge.

* Initialize SCLK as low and {{Overline|CS}} as high
* Pull {{Overline|CS}} low to select the sub
* Loop for however many number of bytes to transfer:{{NoteTag|Peripherals may allow or require a particular number (or any number) of transfer bytes while selected, as specified in their datasheet.}}
** Initialize{{Code|byte_out|C}}with the next output byte to transmit
** Loop 8 times:
*** Left-Shift{{NoteTag|Left-shifts are used because SPI normally transmits the most-significant bit first. Right-shifts could instead be used to transfer least-significant bit first.}} the next output bit from{{Code|byte_out|C}}to MOSI
*** [[NOP (code)|NOP]] for the sub's setup time
*** Pull SCLK high
*** Left-Shift the next input bit from MISO into{{Code|byte_in|C}}
*** NOP for the sub's hold time
*** Pull SCLK low
** {{Code|byte_in|C}}now contains that recently-received byte and can be used as desired
* Pull {{Overline|CS}} high to unselect the sub
Bit-banging a sub's protocol is similar but different from above. An implementation might involve [[Busy waiting|busy waiting]] for {{Overline|CS}} to fall or triggering an [[Interrupt handler|interrupt routine]] when {{Overline|CS}} falls, and then shifting in and out bits when the received SCLK changes appropriately for however long the transfer size is.

== Bus topologies ==
Though the previous operation section focused on a basic interface with a single sub, SPI can instead communicate with multiple subs using multidrop, daisy chain, or expander configurations.

===Multidrop configuration===
[[File:SPI main sub multidrop.svg|thumb|216x216px|Multidrop SPI bus]]
In the [[Engineering:Multidrop bus|multidrop bus]] configuration, each sub has its own {{Overline|CS}}, and the main selects only one at a time. MISO, SCLK, and MOSI are each shared by all devices. This is the way SPI is normally used.

Since the MISO pins of the subs are connected together, they are required to be tri-state pins (high, low or high-impedance), where the high-impedance output must be applied when the sub is not selected. Sub devices not supporting tri-state may be used in multidrop configuration by adding a tri-state buffer chip controlled by its {{Overline|CS}} signal.<ref name="Better SPI Bus Design in 3 Steps">[https://www.pjrc.com/better-spi-bus-design-in-3-steps/ Better SPI Bus Design in 3 Steps]</ref> (Since only a single signal line needs to be tristated per sub, one typical standard logic chip that contains four tristate buffers with independent gate inputs can be used to interface up to four sub devices to an SPI bus)<blockquote>Caveat: All {{Overline|CS}} signals should start high (to indicate no chips are selected) before sending initialization messages to any sub, so other uninitialized subs ignore messages not addressed to them. This is a concern if the main uses general-purpose input/output (GPIO) pins (which may default to an undefined state) for {{Overline|CS}} and if the main uses separate software libraries to initialize each device. One solution is to configure all GPIOs used for {{Overline|CS}} to output a high voltage for ''all'' subs ''before'' running initialization code from any of those software libraries. Another solution is to add a [[Engineering:Pull-up resistor|pull-up resistor]] on each {{Overline|CS}}, to ensure that all {{Overline|CS}} signals are initially high.<ref name="Better SPI Bus Design in 3 Steps" /></blockquote>

===Daisy chain configuration===
[[File:SPI main sub daisychain.svg|thumb|229x229px|Daisy-chained SPI]]
Some products that implement SPI may be connected in a [[Daisy chain (electrical engineering)|daisy chain]] configuration, where the first sub's output is connected to the second sub's input, and so on with subsequent subs, until the final sub, whose output is connected back to the main's input. This effectively merges the individual communication shift registers of each sub to form a single larger combined [[Shift register|shift register]] that shifts data through the chain. This configuration only requires a single {{Overline|CS}} line from the main, rather than a separate {{Overline|CS}} line for each sub.<ref>[https://www.maximintegrated.com/en/app-notes/index.mvp/id/3947 Maxim-IC application note 3947: "Daisy-Chaining SPI Devices"]</ref>

In addition to using SPI-specific subs, daisy-chained SPI can include discrete shift registers for [[Shift register#More I/O pins|more pins]] of inputs (e.g. using the [[Shift register#Parallel-in serial-out (PISO)|parallel-in serial-out]] [[Engineering:List of 7400-series integrated circuits|74]]<nowiki/>xx165)<ref name=":3">{{Cite web |last=Gammon |first=Nick |date=2013-03-23 |title=Gammon Forum : Electronics : Microprocessors : Using a 74HC165 input shift register |url=https://www.gammon.com.au/forum/?id=11979 |url-status=live |archive-url=https://web.archive.org/web/20230729042912/http://www.gammon.com.au/forum/?id=11979 |archive-date=2023-07-29 |access-date=2023-08-03 |website=Gammon Forum}}</ref> or outputs (e.g. using the [[Shift register#Serial-in parallel-out (SIPO)|serial-in parallel-out]] [[Engineering:List of 7400-series integrated circuits|74]]<nowiki/>xx595)<ref name=":2">{{Cite web |last=Gammon |first=Nick |date=2012-01-31 |title=Gammon Forum : Electronics : Microprocessors : Using a 74HC595 output shift register as a port-expander |url=https://www.gammon.com.au/forum/?id=11518 |url-status=live |archive-url=https://web.archive.org/web/20230714101259/http://www.gammon.com.au/forum/?id=11518 |archive-date=2023-07-14 |access-date=2023-08-03 |website=Gammon Forum}}</ref> chained indefinitely. Other applications that can potentially interoperate with daisy-chained SPI include [[SGPIO]], [[JTAG]],<ref>{{citation |title= Interfaces |year = 1977|url= https://books.google.com/books?id=8od7phxJHGkC |pages= 80, 84}}</ref> and I<sup>2</sup>C.

===Expander configurations===
Expander configurations use SPI-controlled addressing units (e.g. [[Engineering:Binary decoder|binary decoders]], demultiplexers, or shift registers) to add chip selects.

For example, one {{Overline|CS}} can be used for transmitting to a SPI-controlled demultiplexer an index number controlling its select signals, while another {{Overline|CS}} is routed through that demultiplexer according to that index to select the desired sub.<ref>{{cite web |date=2001-07-01 |title=Serial-Control Multiplexer Expands SPI Chip Selects |url=http://www.farnell.com/datasheets/312519.pdf |archive-url=https://web.archive.org/web/20190819062018/http://www.farnell.com/datasheets/312519.pdf |archive-date=2019-08-19 |access-date= |website=Premier Farnell}}</ref>

==Pros and cons==

===Advantages===
* Full duplex communication in the default version of this protocol
* Push-pull drivers (as opposed to [[Engineering:Open drain|open drain]]) provide relatively good signal integrity and high speed
* Higher [[Throughput|throughput]] than [[I²C]] or [[System Management Bus|SMBus]]
** SPI's protocol has no maximum clock speed, however:
*** Individual devices specify acceptable clock frequencies
*** Wiring and electronics limit frequency
* Complete protocol flexibility for the bits transferred
** Not limited to 8-bit symbols
** Arbitrary choice of message size, content, and purpose
* Simple hardware and interfacing
** Hardware implementation for subs only requires a selectable shift register
*** Subs use the main's clock and hence do not need precision oscillators
*** Subs do not need a unique [[Address space|address]]{{snd}} unlike [[I²C]] or GPIB or [[Engineering:SCSI|SCSI]]
*** Mains only additionally require generation of clock and {{Overline|CS}} signals
*** Results in simple bit-banged software implementation
** Uses only four pins on IC packages, and wires in board layouts or connectors, much fewer than [[Parallel communication|parallel interfaces]]
*** At most one unique signal per device ({{Overline|CS}}); all others are shared
**** Note: the daisy-chain configuration doesn't need more than one shared {{Overline|CS}}
** Typically lower power requirements than [[I²C]] or SMBus due to less circuitry (including pull up resistors)
** Single main means no bus arbitration (and associated failure modes) - unlike CAN-bus
** Transceivers are not needed - unlike CAN-bus
** Signals are unidirectional, allowing for easy [[Engineering:Galvanic isolation|galvanic isolation]]

===Disadvantages===
* Requires more pins on IC packages than [[I²C]], even in [[Serial Peripheral Interface#Three-wire|three-wire]] variants
* Only handles short distances compared to [[RS-232]], [[RS-485]], or CAN-bus (though distance can be extended with the use of transceivers like [[RS-422]])
* Extensibility severely reduced when multiple subs using different SPI Modes are required
** Access is slowed down when main frequently needs to reinitialize in different modes
* No formal standard
** So validating conformance is not possible
** Many existing variations complicate support
* No built-in protocol support for some conveniences:
** No hardware [[Flow control (data)|flow control]] by the sub (but the main can delay the next clock edge to slow the transfer rate)
** No hardware sub acknowledgment (the main could be transmitting to nowhere and not know it)
** No error-checking protocol
** No [[Hot swapping|hot swapping]] (dynamically adding nodes)
** Interrupts are outside the scope of SPI (see {{Slink|2=Interrupts|nopage=y}})

==Applications==
{{Multiple image
| image1            = ATI Radeon X1300 256MB - Atmel 25F512AN-5397.jpg
| caption1          = SPI Memory by Atmel
| image2            = ADSV-931 Mini Docking Station - LAN module - Fairchild 93C46-93553.jpg
| caption2          = [[Company:Fairchild Semiconductor|Fairchild]] EEPROM using Microwire
| image3            = Sumup AIR1 E205 - board - Microchip 26F032B-1521.jpg
| caption3          = [[Company:Microchip Technology|Microchip]] 32-Mbit SQI Flash Memory
| direction         = horizontal
| total_width       = 400
}}
SPI is used to talk to a variety of peripherals, such as
* Sensors: [[Physics:Temperature|temperature]], [[Physics:Pressure|pressure]], [[Analog-to-digital converter|ADC]], touchscreens, video game controllers
* Control devices: [[Audio codec|audio codec]]s, digital potentiometers, [[Digital-to-analog converter|DACs]]
* Camera lenses: Canon EF lens mount
* Communications: [[Ethernet]], [[Engineering:USB|USB]], USART, [[CAN bus|CAN]], [[IEEE 802.15.4]], [[IEEE 802.11]]
* Memory: [[Flash memory#Serial flash|flash]] and [[EEPROM#Serial bus devices|EEPROMs]]
* [[Engineering:Real-time clock|Real-time clocks]]
* LCDs, sometimes even for managing image data
* Any MMC or [[Secure Digital|SD]] card (including [[Secure Digital#SDIO|SDIO]] variant{{NoteTag|Not to be confused with the SDIO (Serial Data I/O) line of the half-duplex implementation of SPI sometimes also called "3-wire" SPI. Here e.g. MOSI (via a resistor) and MISO (no resistor) of a main is connected to the SDIO line of a sub.|name=3wireSDI}})
* Shift registers for additional I/O<ref name=":3" /><ref name=":2" />
[[Engineering:Printed circuit board|Board]] real estate and wiring savings compared to a [[Parallel communication|parallel]] bus are significant, and have earned SPI a solid role in embedded systems. That is true for most system-on-a-chip processors, both with higher-end 32-bit processors such as those using [[ARM architecture|ARM]], [[MIPS architecture|MIPS]], or [[PowerPC]] and with lower-end microcontrollers such as the AVR, PIC, and MSP430. These chips usually include SPI controllers capable of running in either main or sub mode. [[Engineering:In-system programming|In-system programmable]] AVR controllers (including blank ones) can be programmed using SPI.<ref>{{cite web |url=http://www.atmel.com/dyn/resources/prod_documents/DOC0943.PDF |title=AVR910 - In-system programming |archive-url=https://web.archive.org/web/20110302123348/http://www.atmel.com/dyn/resources/prod_documents/DOC0943.PDF |archive-date=2011-03-02}}</ref>

Chip or FPGA based designs sometimes use SPI to communicate between internal components; on-chip real estate can be as costly as its on-board cousin. And for high-performance systems, FPGAs sometimes use SPI to interface as a sub to a host, as a main to sensors, or for flash memory used to bootstrap if they are SRAM-based.

The full-duplex capability makes SPI very simple and efficient for single main/single sub applications. Some devices use the full-duplex mode to implement an efficient, swift data stream for applications such as [[Digital audio|digital audio]], [[Digital signal processing|digital signal processing]], or telecommunications channels, but most off-the-shelf chips stick to half-duplex request/response protocols.

==Variations==
SPI is a [[Engineering:De facto standard|''de facto'' standard]]. However, the lack of a formal standard is reflected in a wide variety of protocol options. Some devices are transmit-only; others are receive-only. Chip selects are sometimes active-high rather than active-low. Some devices send the least-significant bit first. Signal levels depend entirely on the chips involved. And while the baseline SPI protocol has no command codes, every device may define its own protocol of command codes. Some variations are minor or informal, while others have an official defining document and may be considered to be separate but related protocols. 

=== Original definition ===
[[Company:Motorola|Motorola]] in 1983 listed<ref>{{Cite book |url=http://archive.org/details/bitsavers_motorolada8BitMicroprocessorandPeripheralData_34048525 |title=components :: motorola :: dataBooks :: 1983 Motorola 8-Bit Microprocessor and Peripheral Data}}</ref> three 6805 8-bit [[Microcomputer|microcomputers]]  that have an integrated "Serial Peripheral Interface", whose functionality is described in a 1984 manual.<ref>{{Cite book |url=http://archive.org/details/bitsavers_motoroladaSingleChipMicrocomputerData_68061538 |title=motorola :: dataBooks :: 1984 Motorola Single-Chip Microcomputer Data}}</ref>

==== AN991 ====
Motorola's 1987 Application Node AN991 "Using the Serial Peripheral Interface to Communicate Between Multiple Microcomputers"<ref>{{Cite web |title=Using the Serial Peripheral Interface to Communicate Between Multiple Microcomputers |url=http://www.bitsavers.org/components/motorola/_appNotes/AN-0991_Using_the_Serial_Peripheral_Interface_to_Communicate_between_Multiple_Microcomputers.pdf |website=Bitsavers}}</ref> (now under NXP, last revised 2002<ref name=":4">{{cite web |date=2004 |orig-date=1994 |title=AN991/D: Using the Serial Peripheral Interface to Communicate Between Multiple Microcomputers |url=https://www.nxp.com/docs/en/application-note/AN991.pdf |url-status=live |archive-url=https://web.archive.org/web/20230404200636/https://www.nxp.com/docs/en/application-note/AN991.pdf |archive-date=2023-04-04 |access-date=2021-10-14 |website=NXP}}</ref>) informally serves as the "official" defining document for SPI.

===Timing variations===
Some devices have timing variations from Motorola's CPOL/CPHA modes. Sending data from sub to main may use the opposite clock edge as main to sub. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response.

Some devices have two clocks, one to read data, and another to transmit it into the device. Many of the read clocks run from the chip select line.

=== Transmission size ===
Different transmission word sizes are common. Many SPI chips only support messages that are multiples of 8 bits. Such chips can not interoperate with the [[JTAG]] or [[SGPIO]] protocols, or any other protocol that requires messages that are not multiples of 8 bits.

=== No chip select ===
Some devices don't use chip select, and instead manage protocol state machine entry/exit using other methods.

=== Connectors ===
Anyone needing an external connector for SPI defines their own or uses another standard connection such as: [[Engineering:UEXT|UEXT]], [[Engineering:Pmod Interface|Pmod]], various JTAG connectors, [[Secure Digital]] card socket, etc.

=== Flow control ===
Some devices require an additional [[Flow control (data)|flow control]] signal from sub to main, indicating when data is ready. This leads to a 5-wire protocol instead of the usual 4. Such a ''ready'' or ''enable'' signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have dummy bytes inserted, to accommodate the worst case for the sub response time. Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response. (Many SPI mains do not support that signal directly, and instead rely on fixed delays.)

=== SafeSPI ===
SafeSPI<ref>[http://SafeSPI.org SafeSPI.org]</ref> is an industry standard for SPI in automotive applications. Its main focus is the transmission of sensor data between different devices.

=== High reliability modifications ===
In electrically noisy environments, since SPI has few signals, it can be economical to reduce the effects of common mode noise by adapting SPI to use [[Engineering:Low-voltage differential signaling|low-voltage differential signaling]].<ref>{{cite web |title=Transmitting SPI over LVDS Interfaces |url=https://www.ti.com/lit/ug/tidued8/tidued8.pdf?ts=1613343608107&ref_url=https%253A%252F%252Fwww.google.com%252F |access-date=14 February 2021 |website=Texas Instruments}}</ref> Another advantage is that the controlled devices can be designed to loop-back to test signal integrity.<ref>{{cite web |title=SPI Master Loopback Example |url=https://developer.nordicsemi.com/nRF5_SDK/nRF51_SDK_v4.x.x/doc/html/group__spi__master__example.html |access-date=14 February 2021 |website=Nordic Semiconductor}}</ref>

=== Intelligent SPI controllers ===
A '''Queued Serial Peripheral Interface''' ('''QSPI'''; different to but has same abbreviation as ''Quad SPI'' described in {{Slink|2=Quad SPI|nopage=y}}) is a type of SPI controller that uses a data queue to transfer data across an SPI bus.<ref>{{Cite web |date=1996 |orig-date=1991 |title=Freescale Semiconductor, Inc. - QSM - Queued Serial Module - Reference Manual |url=https://www.nxp.com/docs/en/reference-manual/QSMRM.pdf |url-status=dead |archive-url=https://web.archive.org/web/20190824080750/https://www.nxp.com/docs/en/reference-manual/QSMRM.pdf |archive-date=2019-08-24 |website=NXP}}</ref> It has a [[Circular buffer|wrap-around]] mode allowing continuous transfers to and from the queue with only intermittent attention from the CPU. Consequently, the peripherals appear to the CPU as [[Virtual memory|memory-mapped]] parallel devices. This feature is useful in applications such as control of an [[Analog-to-digital converter|A/D converter]]. Other programmable features in Queued SPI are chip selects and transfer length/delay.

SPI controllers from different vendors support different feature sets; such [[Direct memory access|direct memory access]] (DMA) queues are not uncommon, although they may be associated with separate DMA engines rather than the SPI controller itself, such as used by '''Multichannel Buffered Serial Port''' ('''MCBSP''').{{NoteTag|Such as with the MultiChannel Serial Port Interface, or McSPI, used in Texas Instruments OMAP chips. (https://www.ti.com/product/OMAP3530)}} Most SPI main controllers integrate support for up to four chip selects,{{NoteTag|Such as the SPI controller on Atmel AT91 chips like the at91sam9G20, which is much simpler than TI's McSPI.}} although some require chip selects to be managed separately through GPIO lines.

Note that ''Queued SPI'' is different from ''Quad SPI'', and some processors even confusingly allow a single "QSPI" interface to operate in either quad or queued mode!<ref>{{Cite web |date=2023-01-11 |title=Quad-SPI Brings Fast Parallel Data Transmission |url=https://resources.pcb.cadence.com/blog/quad-spi-brings-fast-parallel-data-transmission |url-status=live |archive-url=https://web.archive.org/web/20230601194620/https://resources.pcb.cadence.com/blog/quad-spi-brings-fast-parallel-data-transmission |archive-date=2023-06-01 |access-date=2023-06-30 |website=Cadence Design Systems |language=en-US}}</ref>

=== Microwire ===
Microwire,<ref>[https://www.ti.com/lit/an/snoa743/snoa743.pdf MICROWIRE Serial Interface] National Semiconductor Application Note AN-452</ref> often spelled '''μWire''', is essentially a predecessor of SPI and a trademark of [[Company:National Semiconductor|National Semiconductor]]. It's a strict subset of SPI: half-duplex, and using SPI mode 0. Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2&nbsp;MHz vs. 20&nbsp;MHz. Some Microwire chips also support a [[Serial Peripheral Interface#Three-wire|three-wire]] mode.

=== Microwire/Plus ===
Microwire/Plus<ref>[https://www.ti.com/lit/an/snoa093/snoa093.pdf MICROWIRE/PLUS Serial Interface for COP800 Family] National Semiconductor Application Note AN-579</ref> is an enhancement of Microwire and features full-duplex communication and support for SPI modes 0 and 1. There was no specified improvement in serial clock speed.

=== Three-wire ===
Three-wire variants of SPI restricted to a half-duplex mode use a single bidirectional data line called SISO (sub out/sub in) or MOMI (main out/main in) instead of SPI's two unidirectional lines (MOSI and MISO). Three-wire tends to be used for lower-performance parts, such as small EEPROMs used only during system startup, certain sensors, and [[Serial Peripheral Interface#Microwire|Microwire]]. Few SPI controllers support this mode, although it can be easily bit-banged in software.

=== Dual SPI ===
For instances where the full-duplex nature of SPI is not used, an extension uses both data pins in a half-duplex configuration to send two bits per clock cycle. Typically a command byte is sent requesting a response in dual mode, after which the MOSI line becomes SIO0 (serial I/O 0) and carries even bits, while the MISO line becomes SIO1 and carries odd bits. Data is still transmitted most-significant bit first, but SIO1 carries bits 7, 5, 3 and 1 of each byte, while SIO0 carries bits 6, 4, 2 and 0.

This is particularly popular among SPI ROMs, which have to send a large amount of data, and comes in two variants:<ref name="W25Q16JV">{{cite web |title=W25Q16JV 3V 16M-bit serial flash memory with Dual/Quad SPI |date=12 August 2016 |version=Revision D |publisher=[[Company:Winbond|Winbond]] |type=data sheet |url=https://www.winbond.com/resource-files/w25q16jv%20spi%20revd%2008122016.pdf |access-date=2017-02-10}}</ref><ref name="D25LQ64">{{cite web |title=D25LQ64 1.8V Uniform Sector Dual and Quad SPI Flash |type=data sheet |date=11 February 2011 |version=version 0.1 |publisher=GigaDevice |url=https://www.sst-ic.com/File/DataSheet/KC909742-1112151725544ed0c4ce-8225-4c46-8d18-b81422086247.pdf |archive-url=https://web.archive.org/web/20170212090900/http://www.sst-ic.com/File/DataSheet/KC909742-1112151725544ed0c4ce-8225-4c46-8d18-b81422086247.pdf |url-status=dead |archive-date=12 February 2017 |access-date=2017-02-10}}</ref>

* Dual read commands  the send and address from the main in single mode, and return the data in dual mode.
* Dual I/O commands send the command in single mode, then send the address and return data in dual mode.

=== Quad SPI ===
'''Quad SPI''' ('''QSPI'''; different to but has same abbreviation as ''Queued-SPI'' described in {{Slink|2=Intelligent SPI controllers|nopage=y}}) goes beyond dual SPI, adding two more I/O lines (SIO2 and SIO3) and sends 4 data bits per clock cycle. Again, it is requested by special commands, which enable quad mode after the command itself is sent in single mode.{{r|W25Q16JV|D25LQ64}}

; SQI Type 1: Commands sent on single line but addresses and data sent on four lines
; SQI Type 2: Commands and addresses sent on a single line but data sent/received on four lines

=== QPI/SQI ===
Further extending quad SPI, some devices support a "quad everything" mode where ''all'' communication takes place over 4 data lines, including commands.<ref>{{cite web |url=https://community.nxp.com/thread/336422 |title=QuadSPI flash: Quad SPI mode vs. QPI mode |date=December 2014 |website=NXP community forums |access-date=2016-02-10}}</ref>   This is variously called "QPI"{{r|D25LQ64}} (not to be confused with [[Intel QuickPath Interconnect]]) or "serial quad I/O" (SQI)<ref name="SST26VF032B">{{cite web |title=SST26VF032B / SST26VF032BA 2.5V/3.0V 32 Mbit Serial Quad I/O (SQI) Flash Memory |type=Data sheet |publisher=Microchip, Inc. |date=2017 |version=version E |url=http://ww1.microchip.com/downloads/en/DeviceDoc/20005218E.pdf |access-date=2017-02-10}}</ref>

This requires programming a configuration bit in the device and requires care after reset to establish communication.

=== Double data rate ===
In addition to using multiple lines for I/O, some devices increase the transfer rate by using [[Engineering:Double data rate|double data rate]] transmission.<ref>{{Cite web |first=David |last=Patterson |url=https://www.nxp.com/files/32bit/doc/app_note/AN4512.pdf |title=Quad Serial Peripheral Interface (QuadSPI) Module Updates |type=Application note |date=May 2012 |access-date=September 21, 2016 |publisher=[[Company:Freescale Semiconductor|Freescale Semiconductor]]}}</ref><ref>{{cite news |title=Improving performance using SPI-DDR NOR flash memory |first=Rich |last=Pell |date=13 October 2011 |journal=EDN |url=https://www.edn.com/design/systems-design/4368499/Improving-performance-using-SPI-DDR-NOR-flash-memory-4368499}}</ref>

=== JTAG ===
{{Main articles|JTAG}}
Although there are some similarities between SPI and the [[JTAG]] (IEEE 1149.1-2013) protocol, they are not interchangeable. JTAG is specifically intended to provide reliable [[Engineering:Boundary scan|test access to the I/O pins]] from an off-board controller with less precise signal delay and skew parameters, while SPI has many varied applications. While not strictly a level sensitive interface, the JTAG protocol supports the recovery of both setup and hold violations between JTAG devices by reducing the clock rate or changing the clock's duty cycles. Consequently, the JTAG interface is not intended to support extremely high data rates.<ref>IEEE 1149.1-2013</ref>

=== SGPIO ===
{{Main articles|SGPIO}}
[[SGPIO]] is essentially another (incompatible) application stack for SPI designed for particular backplane management activities.{{citation needed|date=July 2010}} SGPIO uses 3-bit messages.

===Intel's Enhanced Serial Peripheral Interface===
[[Company:Intel|Intel]] has developed a successor to its [[Engineering:Low Pin Count|Low Pin Count]] (LPC) bus that it calls the '''Enhanced Serial Peripheral Interface (eSPI)''' bus. Intel aims to reduce the number of pins required on motherboards and increase throughput compared to LPC, reduce the working voltage to 1.8 volts to facilitate smaller chip manufacturing processes, allow eSPI peripherals to share SPI flash devices with the host (the LPC bus did not allow firmware hubs to be used by LPC peripherals), tunnel previous out-of-band pins through eSPI, and allow system designers to trade off cost and performance.<ref name="eSPI">{{cite report |title=Enhanced Serial Peripheral Interface (eSPI) Interface Base Specification (for Client and Server Platforms) |date=January 2016 |version=Revision 1.0 |url=https://www-ssl.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_base_specification_rev1.0_cb.pdf |publisher=Intel |access-date=2017-02-05 |id=Document number 327432-004}}</ref><ref>{{cite report |id=Document Number 327432-001EN |title=Enhanced Serial Peripheral Interface (eSPI) Interface Specification (for Client Platforms) |date=May 2012 |version=Revision 0.6 |url=https://downloadmirror.intel.com/21353/eng/eSPI%20Specification%20rev0.6%20(client).pdf |publisher=Intel |access-date=2017-02-05}}</ref>

An eSPI bus can either be shared with SPI devices to save pins or be separate from an SPI bus to allow more performance, especially when eSPI devices need to use SPI flash devices.<ref name="eSPI" />

This standard defines an Alert# signal that is used by an eSPI sub to request service from the main. In a performance-oriented design or a design with only one eSPI sub, each eSPI sub will have its Alert# pin connected to an Alert# pin on the eSPI main that is dedicated to each sub, allowing the eSPI main to grant low-latency service, because the eSPI main will know which eSPI sub needs service and will not need to poll all of the subs to determine which device needs service. In a budget design with more than one eSPI sub, all of the Alert# pins of the subs are connected to one Alert# pin on the eSPI main in a wired-OR connection, which requires the main to poll all the subs to determine which ones need service when the Alert# signal is pulled low by one or more peripherals that need service. Only after all of the devices are serviced will the Alert# signal be pulled high due to none of the eSPI subs needing service and therefore pulling the Alert# signal low.<ref name="eSPI" />

This standard allows designers to use 1-bit, 2-bit, or 4-bit communications at speeds from 20 to 66&nbsp;MHz to further allow designers to trade off performance and cost.<ref name="eSPI" />

All communications that were out-of-band of LPC like general-purpose input/output (GPIO) and [[System Management Bus]] (SMBus) are tunneled through eSPI via virtual wire cycles and out-of-band message cycles respectively in order to remove those pins from motherboard designs using eSPI.<ref name="eSPI" />

This standard supports standard memory cycles with lengths of 1 byte to 4 kilobytes of data, short memory cycles with lengths of 1, 2, or 4 bytes that have much less overhead compared to standard memory cycles, and I/O cycles with lengths of 1, 2, or 4 bytes of data which are low overhead as well. This significantly reduces overhead compared to the LPC bus, where all cycles except for the 128-byte firmware hub read cycle spends more than one-half of all of the bus's throughput and time in overhead. The standard memory cycle allows a length of anywhere from 1 byte to 4 kilobytes in order to allow its larger overhead to be amortised over a large transaction. eSPI subs are allowed to initiate bus master versions of all of the memory cycles. Bus master I/O cycles, which were introduced by the LPC bus specification, and ISA-style DMA including the 32-bit variant introduced by the LPC bus specification, are not present in eSPI. Therefore, bus master memory cycles are the only allowed DMA in this standard.<ref name="eSPI" />

eSPI subs are allowed to use the eSPI main as a proxy to perform flash operations on a standard SPI flash memory sub on behalf of the requesting eSPI sub.<ref name="eSPI" />

64-bit memory addressing is also added, but is only permitted when there is no equivalent 32-bit address.<ref name="eSPI" />

The Intel Z170 chipset can be configured to implement either this bus or a variant of the LPC bus that is missing its ISA-style DMA capability and is underclocked to 24&nbsp;MHz instead of the standard 33&nbsp;MHz.<ref>{{Cite web | url = https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/100-series-chipset-datasheet-vol-1.pdf | title = Intel® 100 Series Chipset Family PCH Datasheet, Vol. 1 | access-date = April 15, 2015}}</ref>

==Development tools==

=== Single-board computers ===
Single-board computers may provide [[Engineering:Lead (electronics)|pin]] access to SPI hardware units. For instance, the [[Engineering:Raspberry Pi#J8 header and general purpose input-output (GPIO)|Raspberry Pi's J8 header]] exposes at least two SPI units that can be used via [[Software:Linux|Linux]] [[Device driver|drivers]] or [[Python (programming language)|python]].

=== USB to SPI adapters ===
There are a number of [[Engineering:USB|USB]] adapters that allow a desktop [[Engineering:Personal computer|PC]] or [[Engineering:Smartphone|smartphone]] with [[Engineering:USB|USB]] to communicate with SPI chips (e.g. FT221xs<ref>{{cite web |title=USB to SPI converter |url=https://ftdichip.com/products/ft221xs/ |access-date=14 February 2021 |website=FTDI|date=2 August 2020 }}</ref>). They are used for embedded systems, chips (FPGA, [[Engineering:Application-specific integrated circuit|ASIC]], and [[System on a chip|SoC]]) and peripheral testing, programming and debugging. Many of them also provide scripting or programming capabilities (e.g. [[Visual Basic]], [[C (programming language)|C]]/[[C++]], [[VHDL]]).

The key SPI parameters are: the maximum supported frequency for the serial interface, command-to-command latency, and the maximum length for SPI commands. It is possible to find SPI adapters on the market today that support up to 100&nbsp;MHz serial interfaces, with virtually unlimited access length.

SPI protocol being a de facto standard, some SPI host adapters also have the ability of supporting other protocols beyond the traditional 4-wire SPI (for example, support of quad-SPI protocol or other custom serial protocol that derive from SPI<ref>[https://www.byteparadigm.com/product-spi-storm-39.html SPI Storm – Serial Protocol Host Adapter] with support of custom serial protocols, Byte Paradigm.</ref>).

===Protocol analyzers===
{{Main articles|Logic analyzer}}
Logic analyzers are tools which collect, [[Physics:Timestamp|timestamp]], analyze, decode, store, and view the high-speed waveforms, to help [[Debugging|debug]] and develop. Most logic analyzers have the capability to decode SPI bus signals into high-level protocol data with human-readable labels.

==== Oscilloscopes ====
SPI waveforms can be seen on [[Engineering:Analog signal|analog]] channels (and/or via digital channels in [[Engineering:Oscilloscope#Mixed-signal oscilloscope|mixed-signal oscilloscopes]]).<ref>{{cite web |title=N5391B I²C and SPI Protocol Triggering and Decode for Infiniium scopes |url=https://www.keysight.com/en/pd-1646694-pn-N5391B/ic-and-spi-protocol-triggering-and-decode?cc=US&lc=eng}}</ref> Most [[Engineering:Oscilloscope|oscilloscope]] vendors offer optional support for SPI protocol analysis (both 2-, [[Serial Peripheral Interface#Three-wire|3-]], and 4-wire SPI) with triggering.

==Alternative terminology==
The term "master" is commonly used to identify the main device and "slave" for peripheral (sub) devices. These terms reflect how the main device is responsible for driving the serial clock and initiating communication: peripheral devices are only able to communicate when the main device is driving the clock.

Various more contemporary alternative names for each of the four signals have been proposed:
* SCK : Serial Clock. Alternatives:
** SCK, SCLK, CLK, SCL
* MOSI : "Master" Out → "Slave" In. Now can be read as "Main" Out "Sub" In, or can use these alternatives:
** SIMO, MTSR, SPID - correspond to MOSI on both main and sub devices, connects to each other
** SDI, DI, DIN, SI, SDA - on sub-only devices; Various abbreviations for "Serial" "Data" "In". Connects to MOSI (or alternative names) on main
** SDO, DO, DOUT, SO - on main-only devices; Various abbreviations for "Serial" "Data" "Out". connects to MOSI (or alternative names) on sub
** COPI, PICO for "peripheral and controller",<ref name="OSHWA">[https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/ SPI; OSHWA.]</ref><ref name=":5">https://www.ti.com/lit/an/scea091a/scea091a.pdf</ref> or COTI for "controller" and "target"<ref name=":1">{{Cite web |title=Serial Peripheral Interface (SPI) Devices |url=https://www.nxp.com/products/interfaces/ic-spi-i3c-interface-devices/www.nxp.com/pages/:SPI |url-status=live |archive-url=https://web.archive.org/web/20230601020101/https://www.nxp.com/products/interfaces/ic-spi-i3c-interface-devices/spi-interface-devices:SPI |archive-date=2023-06-01 |access-date=2023-07-22 |website=NXP}}</ref>
* MISO : "Master" In ← "Slave" Out. Now can be read as "Main" In "Sub" Out, or can use these alternatives:
** SOMI, MRST, SPIQ - correspond to MISO on both main and sub devices, connects to each other
** SDO, DO, DOUT, SO - on sub-only devices; connects to MISO (or alternative names) on main
** SDI, DI, DIN, SI - on main-only devices; connects to MISO (or alternative names) on sub
** CIPO, POCI,<ref name="OSHWA" /><ref name=":5" /> or CITO<ref name=":1" />
* {{Overline|SS}} : "Slave" Select (same functionality as [[Engineering:Chip select|{{Overline|Chip Select}}]]). Alternatives:
** SS, {{Overline|SS}}, SSEL, NSS, /SS, SS# (sub select)
** CS, {{Overline|CS}} (chip select)
** CE (chip enable)
[[Company:Microchip Technology|Microchip]] uses "Host" and "Client" though keeps the abbreviation MOSI and MISO.<ref>{{Cite web |last=Stoicescu |first=Alin |title=Getting Started with Serial Peripheral Interface (SPI) |url=https://onlinedocs.microchip.com/pr/GUID-EF58F3A9-B49B-4C31-A7EC-B71EBB831870-en-US-5/index.html |url-status=live |archive-url=https://web.archive.org/web/20231221205244/https://onlinedocs.microchip.com/pr/GUID-EF58F3A9-B49B-4C31-A7EC-B71EBB831870-en-US-5/index.html |archive-date=2023-12-21 |access-date=2023-12-21 |website=[[Company:Microchip Technology|Microchip Technology]]}}</ref>

==See also==
* [[List of network buses]]

==Notes==
{{NoteFoot}}

==References==
{{reflist|30em}}

==External links==
*[https://www.intel.com/content/www/us/en/support/software/chipset-software/000020952.html Intel eSPI (Enhanced Serial Peripheral Interface)]
*[https://www.corelis.com/education/SPI_Tutorial.htm SPI Tutorial]

{{Computer bus}}

[[Category:Computer buses]]
[[Category:Computer hardware standards]]
[[Category:Serial buses]]

{{Sourceattribution|Serial Peripheral Interface}}