View source for Template:AMD APU features

{{Use dmy dates|date=July 2019}}
The following table shows features of [[Company:Advanced Micro Devices|AMD]]'s [[Accelerated processing unit|APU]]s (see also: [[Engineering:List of AMD accelerated processing units|List of AMD accelerated processing units]]).
{{navbar-table|AMD APU features}}
{| class="wikitable" style="font-size: 87.5%; text-align: center"
! {{rh}} rowspan="10" | Codename || {{rh}} rowspan="2" | Server
! {{rh}} | Basic 
! colspan=4 | 
! [[Engineering:List of AMD accelerated processing units#Opteron X3000-series "Toronto" (2017)|Toronto]]
! colspan=4 |
! style="background: #ececec;" rowspan="74" |
! colspan=6 | 
|-
! {{rh}} | Micro
! colspan=9 | 
! 
! [[Engineering:List of AMD accelerated processing units#Opteron X2100-series "Kyoto" (2013)|Kyoto]]
! colspan=4 |
|-
! {{rh}} rowspan=3 | Desktop || {{rh}} | Mainstream
! colspan=4 | 
! rowspan=2 | [[Engineering:List of AMD accelerated processing units#"Carrizo" (2016)|Carrizo]]
! [[Engineering:List of AMD accelerated processing unit microprocessors#"Bristol Ridge" (2016)|Bristol Ridge]]
! [[Engineering:List of AMD accelerated processing units#"Raven Ridge" (2018)|Raven Ridge]]
! [[Engineering:List of AMD accelerated processing units#"Picasso" (2019)|Picasso]]
! 
! rowspan=2 colspan=6 | 
|-
! {{rh}} | Entry
! [[Engineering:List of AMD accelerated processing unit microprocessors#Lynx: "Llano" (2011)|Llano]]
! [[Engineering:List of AMD accelerated processing units#Virgo: "Trinity" (2012)|Trinity]]
! [[Engineering:List of AMD accelerated processing units#"Richland" (2013)|Richland]]
! [[Engineering:List of AMD accelerated processing unit microprocessors#"Kaveri" (2014)|Kaveri]]
! colspan=4 | 
|-
! {{rh}} | Basic
! colspan=9 | 
! 
! [[Engineering:List of AMD accelerated processing units#"Kabini" (2013, SoC)|Kabini]]
! colspan=4 | 
|-
! {{rh}} rowspan=4 | Mobile || {{rh}} | Performance
! colspan=8 | 
! rowspan=2 | [[Engineering:List of AMD accelerated processing units#"Renoir" (2020)|Renoir]]
! rowspan=2 colspan=6 | 
|-
! {{rh}} | Mainstream
! rowspan=2 | [[Engineering:List of AMD accelerated processing units#Sabine: "Llano" (2011)|Llano]]
! rowspan=2 | [[Engineering:List of AMD accelerated processing units#Comal: "Trinity" (2012)|Trinity]]
! rowspan=2 | [[Engineering:List of AMD accelerated processing units#"Richland" (2013) 2|Richland]]
! rowspan=2 | [[Engineering:List of AMD accelerated processing units#"Kaveri" (2014) 2|Kaveri]]
! rowspan=2 | [[Engineering:List of AMD accelerated processing units#"Carrizo" (2015)|Carrizo]]
! rowspan=2 | [[Engineering:List of AMD accelerated processing units#"Bristol Ridge" (2016) 2|Bristol Ridge]]
! rowspan=2 | [[Engineering:List of AMD accelerated processing units#"Raven Ridge" (2017)|Raven Ridge]]
! [[Engineering:List of AMD accelerated processing units#"Picasso" (2019) 2|Picasso]]
|-
! {{rh}} | Entry
! colspan=2 |
! colspan=5 |
! rowspan=2 | [[Engineering:List of AMD accelerated processing units#"Dalí" (2020)|Dalí]]
|-
! {{rh}} | Basic
! colspan=9 |
! [[Engineering:List of AMD accelerated processing units#Brazos: "Desna", "Ontario", "Zacate" (2011)|Desna, Ontario, Zacate]]
! [[Engineering:List of AMD accelerated processing units#"Kabini", "Temash" (2013)|Kabini, Temash]]
! [[Engineering:List of AMD accelerated processing units#"Beema", "Mullins" (2014)|Beema, Mullins]]
! [[Engineering:List of AMD accelerated processing units#"Carrizo-L" (2015)|Carrizo-L]]
! [[Engineering:List of AMD accelerated processing unit microprocessors#"Stoney Ridge" (2016)|Stoney Ridge]]
|-
! {{rh}} colspan=2 | Embedded
!
! [[Engineering:List of AMD accelerated processing units#Comal: "Trinity" (2012) 2|Trinity]]
! 
! [[Engineering:List of AMD accelerated processing units#"Bald Eagle" (2014)|Bald Eagle]]
! [[Engineering:List of AMD accelerated processing units#"Merlin Falcon" (2015%2C SoC)|Merlin Falcon]],<br />[[Engineering:List of AMD accelerated processing units#I-Family: "Brown Falcon" (2016, SoC)|Brown Falcon]]
! 
! [[Engineering:List of AMD accelerated processing units#V1000-Family: "Great Horned Owl" (2018, SoC)|Great Horned Owl]]
! colspan=2 |
! [[Engineering:List of AMD accelerated processing units#Brazos: "Ontario" and "Zacate" (2011)|Ontario, Zacate]]
! [[Engineering:List of AMD accelerated processing units#"Kabini" (2013, SoC) 2|Kabini]]
! [[Engineering:List of AMD accelerated processing units#"Steppe Eagle" (2014, SoC)|Steppe Eagle]], [[Engineering:List of AMD accelerated processing units#"Crowned Eagle" (2014, SoC)|Crowned Eagle]],<br /> [[Engineering:List of AMD accelerated processing units#LX-Family (2016, SoC)|LX-Family]]
! 
! [[Engineering:List of AMD accelerated processing units#J-Family: "Prairie Falcon" (2016, SoC)|Prairie Falcon]]
! [[Engineering:List of AMD accelerated processing units#R1000-Family: "Banded Kestrel" (2019, SoC)|Banded Kestrel]]
|-
| {{rh}} colspan="3" | Platform || colspan="9" | High, standard and low power || colspan="6" | Low and ultra-low power
|-
| {{rh}} colspan="3" | Released || Aug 2011 || Oct 2012 || Jun 2013 || Jan 2014 || Jun 2015 || Jun 2016 || Oct 2017 || Jan 2019 || Mar 2020 || Jan 2011 || May 2013 || Apr 2014 || May 2015 || Feb 2016 || Apr 2019 
|-
| {{rh}} colspan="3" | CPU [[Microarchitecture|microarchitecture]] || [[Engineering:AMD 10h|K10]] || colspan="2" | [[Engineering:Piledriver (microarchitecture)|Piledriver]] || [[Engineering:Steamroller (microarchitecture)|Steamroller]] || [[Engineering:Excavator (microarchitecture)|Excavator]] || "[[Engineering:Excavator (microarchitecture)|Excavator+]]"<ref>{{cite news |url=https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks |title=AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks|date=31 May 2016 |accessdate=3 January 2020}}</ref>   || [[Engineering:Zen (microarchitecture)|Zen]] || [[Engineering:Zen+|Zen+]] || [[Engineering:Zen 2|Zen 2]] || [[Engineering:Bobcat (microarchitecture)|Bobcat]] || [[Engineering:Jaguar (microarchitecture)|Jaguar]] || [[Engineering:Puma (microarchitecture)|Puma]] || [[Engineering:Puma (microarchitecture)#Puma+|Puma+]]<ref>{{cite press |url=https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx |title=AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015 |date=20 November 2014 |accessdate=16 February 2015}}</ref> || "[[Engineering:Excavator (microarchitecture)|Excavator+]]" || [[Engineering:Zen (microarchitecture)|Zen]]
|-
| {{rh}} colspan="3" | [[Instruction set architecture|ISA]] || colspan="9" | [[X86-64|x86-64]] || colspan="6" | x86-64
|- style="border-top:0.2em solid grey"
| {{rh}} rowspan="5" | [[Template:AMD CPU sockets|Socket]] || {{rh}} rowspan="4" | Desktop || {{rh}} | High-end || colspan="9" {{n/a}} || rowspan=3 colspan="6" {{n/a}} 
|-
| {{rh}} | Mainstream || colspan="4" {{n/a}} || colspan="5" | [[Engineering:Socket AM4|AM4]] 
|-
| {{rh}} | Entry || [[Engineering:Socket FM1|FM1]] || colspan="2" | [[Engineering:Socket FM2|FM2]] || colspan="2" | [[Engineering:Socket FM2+|FM2+]]{{efn|APU models: A8-7680, A6-7480. CPU only: Athlon X4 845.}} || colspan="4" {{n/a}} 
|-
| {{rh}} | Basic || colspan="9" {{n/a}} || {{n/a}} || [[Engineering:Socket AM1|AM1]] || colspan=4 {{n/a}}
|-
| {{rh}} colspan=2 | Other || [[Socket FS1|FS1]] || colspan="2" | [[Socket FS1r2|FS1+]], [[Socket FP2|FP2]] || [[Socket FP3|FP3]] || colspan="2" | [[Socket FP4|FP4]] || colspan="2" | [[Socket FP5|FP5]] || [[Socket FP6|FP6]] || [[Engineering:Socket FT1|FT1]] || [[Socket FT3|FT3]] || colspan="2" |  [[Socket FT3b|FT3b]] || [[Socket FP4|FP4]] || [[Socket FP5|FP5]]
|-
| {{rh}} colspan="3" | [[Engineering:PCI Express|PCI Express]] version || colspan="3" | 2.0 || colspan="6" | 3.0 || colspan="4" | 2.0 || colspan=2 | 3.0 
|- style="border-top:0.2em solid grey"
| {{rh}} colspan="3" | [[Engineering:Semiconductor device fabricat[[Physics:Ion|Fab. (Na]]nometre|nm]]) || colspan="3" | [[Company:GlobalFoundries|GF]] [[32 nanometer|32SHP]]<br />([[HKMG]] [[Physics:Silicon on insulator|SOI]]) || colspan="3" | GF [[28 nanometer|28SHP]]<br />(HKMG bulk) || GF [[14 nanometer|14LPP]]<br />([[Engineering:FinFET|FinFET]] bulk) || GF [[12 nanometer|12LP]]<br />(FinFET bulk) || [[Company:TSMC|TSMC]] [[7 nanometer|N7]]<br />(FinFET bulk) || TSMC [[40 nanometer|N40]]<br />(bulk) || TSMC [[28 nanometer|N28]]<br />(HKMG bulk) || colspan="3" | GF 28SHP<br />(HKMG bulk) || GF [[14 nanometer|14LPP]]<br />([[Engineering:FinFET|FinFET]] bulk) 
|-
| {{rh}} colspan="3" | [[Engineering:Die (integrated circuit)|Die]] area (mm<sup>2</sup>) || 228 || colspan="2" | 246 || 245 || 245 || 250 || colspan=2 | 210<ref>{{cite web|title=The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List|url=https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/ |accessdate=13 December 2017|publisher=TechARP.com}}</ref> || 156 || 75 (+ 28 [[Engineering:List of AMD chipsets#Fusion controller hubs (FCH)|FCH]]) || colspan="2" | 107 || {{dunno}} || 125 || 
|-
| {{rh}} colspan="3" | Min [[Thermal Design Power|TDP]] (W) || 35 || colspan="3" | 17 || colspan="4" | 12 || 10 || 4.5 || 4 || 3.95 || 10 || colspan=2 | 6
|-
| {{rh}} colspan="3" | Max APU [[Thermal Design Power|TDP]] (W) || colspan="3" | 100 || 95 || colspan="4" | 65 || 54 || 18 || colspan="5" | 25 
|-
| {{rh}} colspan="3" | Max stock APU base clock (GHz) || 3 || 3.8 || colspan="2" | 4.1 || 3.7 || 3.8 || 3.6 || 3.7 || 3.3 || 1.75 || 2.2 || 2 || 2.2 || 3.2 || 3.3 
|-
| {{rh}} colspan="3" | Max APUs per node{{efn|name=nodedef|A PC would be one node.}} || colspan="9" | 1 || colspan="6" | 1 
|-
| {{rh}} colspan="3" | Max [[Central processing unit|CPU]]{{efn|name=apudef|An APU combines a CPU and a GPU. Both have cores.}} [[Multi-core processor|cores]] per APU || colspan="8" | 4 || 8 || 2 || colspan="3" | 4 || colspan=2 | 2
|-
| {{rh}} colspan="3" | Max [[Thread (computing)|threads]] per CPU core || colspan="6" | 1 || colspan="3" | 2 || colspan="5" | 1 || 2 
|-
| {{rh}} colspan="3" | Integer structure || 3+3 || colspan="5" | 2+2 || colspan="2" | 4+2 || 4+2+1 || colspan="4" | 1+1+1+1 || 2+2 || 4+2
|-
| {{rh}} colspan="3" | i386, i486, i586, CMOV, NOPL, i686, [[Physical Address Extension|PAE]], [[NX bit]], CMPXCHG16B, [[AMD-V]], [[Second Level Address Translation#RVI|RVI]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], and 64-bit LAHF/SAHF || colspan="9" {{ya}} || rowspan=2 colspan="6" {{ya}}
|-
| {{rh}} colspan="3" | [[IOMMU]]{{efn|name=iommubios|Requires firmware support.}} || rowspan=2 {{n/a}} || rowspan=2 colspan="8" {{ya}} 
|-
| {{rh}} colspan="3" | [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[AES instruction set|AES-NI]], [[CLMUL]], and [[F16C]] || rowspan=2 {{n/a}} || colspan="5" rowspan=2 {{ya}}
|-
| {{rh}} colspan="3" | MOVBE ||  colspan="4" rowspan=2 {{n/a}} || rowspan=2 colspan="5" {{ya}} 
|-
| {{rh}} colspan="3" | [[X86 virtualization#Interrupt virtualization (AMD AVIC and Intel APICv)|AVIC]], [[Bit Manipulation Instruction Sets#BMI2 (Bit Manipulation Instruction Set 2))|BMI2]] and [[RDRAND]] || colspan="4" {{n/a}} || colspan="2" {{ya}}
|-
| {{rh}} colspan="3" | [[Intel ADX|ADX]], [[Intel SHA extensions|SHA]], [[RDSEED]], [[Supervisor Mode Access Prevention|SMAP]], [[Control register#SMEP|SMEP]], XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO || colspan="6" {{n/a}} || colspan="3" {{ya}} || rowspan=2 colspan="5" {{n/a}} || {{ya}}
|-
| {{rh}} colspan="3" | WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT || colspan="8" {{n/a}} || colspan="1" {{ya}} || colspan="6" {{n/a}} 
|- style="border-top:0.2em solid grey"
| {{rh}} colspan="3" | [[Floating-point unit|FPUs]] per [[Multi-core processor|core]] || 1 || colspan="5" | 0.5 || colspan="3" | 1 || colspan="4" | 1 || 0.5 || 1 
|-
| {{rh}} colspan="3" | Pipes per FPU || colspan="9" | 2 || colspan="6" | 2
|-
| {{rh}} colspan="3" | FPU pipe width || colspan="8" | 128-bit || 256-bit || 80-bit || colspan="5" | 128-bit 
|-
| {{rh}} colspan="3" | CPU [[Instruction set|instruction set]] [[SIMD]] level || [[SSE4a]]{{efn|name="sse4a"|No SSE4. No SSSE3.}} || colspan="3" | [[Advanced Vector Extensions|AVX]] || colspan="5" | [[Advanced Vector Extensions#Advanced Vector Extensions 2|AVX2]] || [[SSSE3]] || colspan="3" | [[Advanced Vector Extensions|AVX]] || colspan=2 | [[Advanced Vector Extensions#Advanced Vector Extensions 2|AVX2]]
|-
| {{rh}} colspan="3" | [[Engineering:3DNow!|3DNow!]] || [[Engineering:3DNow!#3DNow extensions|3DNow!+]] || colspan="8" {{n/a}} || colspan="6" {{n/a}}
|-
| {{rh}} colspan="3" | [[PREFETCHW|PREFETCH/PREFETCHW]] || colspan="9" {{ya}} || colspan="6" {{ya}}
|-
| {{rh}} colspan="3" | [[FMA4]], LWP, [[Bit Manipulation Instruction Sets#TBM|TBM]], and [[XOP instruction set|XOP]] || rowspan=2 {{n/a}} || colspan="5" {{ya}} || colspan="3" {{n/a}} || rowspan=2 colspan="4" {{n/a}} || {{ya}} || {{n/a}}
|-
| {{rh}} colspan="3" | [[FMA3]] || colspan="8" {{ya}} || colspan=2 {{ya}}
|- style="border-top:0.2em solid grey"
| {{rh}} colspan="3" | [[L1 cache|L1]] data cache per core (KiB) || 64 || colspan="3" | 16 || colspan="5" | 32 || colspan="6" | 32
|-
| {{rh}} colspan="3" | L1 data cache [[Cache placement policies#Set-associative cache|associativity]] (ways) || 2 || colspan="3" | 4 || colspan="5" | 8 || colspan="6" | 8 
|- style="border-top:0.2em solid grey"
| {{rh}} colspan="3" | L1 instruction caches per [[Multi-core processor|core]] || 1 || colspan="5" | 0.5 || colspan="3" | 1 || colspan="4" | 1 || 0.5 || 1 
|-
| {{rh}} colspan="3" | Max APU total L1 instruction cache (KiB) || 256 || colspan="2" | 128 || colspan="3" | 192 || colspan="3" | 256 || 64 || colspan="3" | 128 || 96 || 128 
|-
| {{rh}} colspan="3" | L1 instruction cache [[Cache placement policies#Set-associative cache|associativity]] (ways) || colspan="3" | 2 || colspan="3" | 3 || colspan="2" | 4 || 8 || colspan="4" | 2 || 3 || 4 
|- style="border-top:0.2em solid grey"
| {{rh}} colspan="3" | [[L2 cache|L2 caches]] per [[Multi-core processor|core]] || 1 || colspan="5" | 0.5 || colspan="3" | 1 || colspan="4" | 1 || 0.5 || 1 
|-
| {{rh}} colspan="3" | Max APU total L2 cache (MiB) || colspan="4" | 4 || colspan="4" | 2 || 4 || 1 || colspan="3" | 2 || colspan=2 | 1 
|-
| {{rh}} colspan="3" | L2 cache [[Cache placement policies#Set-associative cache|associativity]] (ways) || colspan="6" | 16 || colspan="3" | 8 || colspan="5" | 16 || 8 
|- style="border-top:0.2em solid grey"
| {{rh}} colspan="3" | APU total [[L3 cache]] (MiB) || colspan="6" rowspan=2 {{n/a}} || colspan="2" | 4 || 8 || colspan="5" rowspan=3 {{n/a}} || 4 
|-
| {{rh}} colspan="3" | APU L3 cache [[Cache placement policies#Set-associative cache|associativity]] (ways) || colspan="3" | 16 || 16 
|-
| {{rh}} colspan="3" | L3 cache scheme || colspan="3" | [[Victim cache|Victim]] || colspan="3"  {{n/a}} || colspan="3" | Victim || Victim
|- style="border-top:0.2em solid grey"
| {{rh}} colspan="3" | Max stock [[Dynamic random-access memory|DRAM]] support || colspan="2" | [[DDR3 SDRAM|DDR3-1866]] || colspan="2" | [[DDR3 SDRAM|DDR3-2133]] || [[DDR3 SDRAM|DDR3-2133]], [[DDR4 SDRAM|DDR4-2400]] || [[DDR4 SDRAM|DDR4-2400]] || colspan="2" | [[DDR4 SDRAM|DDR4-2933]] || colspan="1" | [[DDR4 SDRAM|DDR4-3200]], [[LPDDR#LP-DDR4|LPDDR4-4266]] || [[DDR3L|DDR3L-1333]] || [[DDR3L|DDR3L-1600]] || colspan="2" | [[DDR3L|DDR3L-1866]]|| [[DDR3 SDRAM|DDR3-1866]], [[DDR4 SDRAM|DDR4-2400]] || [[DDR4 SDRAM|DDR4-2400]]
|-
| {{rh}} colspan="3" | Max [[Dynamic random-access memory|DRAM]] channels per APU || colspan="9" | 2 || colspan="5" | 1 || 2
|-
| {{rh}} colspan="3" | Max stock [[Dynamic random-access memory|DRAM]] [[Bandwidth (computing)|bandwidth]] (GB/s) per APU || colspan="2" | 29.866 || colspan="2" | 34.132 || colspan="2" | 38.400 || colspan="2" | 46.932 || 68.256 || 10.666 || 12.800 || colspan="2" | 14.933 || 19.200 || 38.400
|- style="border-top:0.2em solid grey"
| {{rh}} colspan="3" | GPU [[Microarchitecture|microarchitecture]] || [[TeraScale (microarchitecture)#TeraScale 2 "Evergreen"-family|TeraScale 2 (VLIW5)]] || colspan="2" | [[TeraScale (microarchitecture)#TeraScale 3 "Northern Islands"-family|TeraScale 3 (VLIW4)]] || [[Graphics Core Next#GCN 2nd generation|GCN 2nd gen]] || colspan="2" | [[Graphics Core Next#GCN 3rd generation|GCN 3rd gen]] || colspan="3" | [[Graphics Core Next#GCN 5th generation|GCN 5th gen]]<ref name="Vega codenames">{{cite web |url=http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/ |title=AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver |publisher=VideoCardz.com |accessdate=6 June 2017}}</ref> || [[TeraScale (microarchitecture)#TeraScale 2 "Evergreen"-family|TeraScale 2 (VLIW5)]] || colspan="3" | [[Graphics Core Next#GCN 2nd generation|GCN 2nd gen]]  || [[Graphics Core Next#GCN 3rd generation|GCN 3rd gen]]<ref name="Vega codenames" /> || [[Graphics Core Next#GCN 5th generation|GCN 5th gen]]
|-
| {{rh}} colspan="3" | GPU [[Instruction set|instruction set]] || colspan="3" | [[TeraScale (microarchitecture)|TeraScale]] instruction set || colspan="6" | [[Graphics Core Next#Instruction set|GCN instruction set]] || [[TeraScale (microarchitecture)|TeraScale]] instruction set || colspan="5" | [[Graphics Core Next#Instruction set|GCN instruction set]]
|-
| {{rh}} colspan="3" | Max stock GPU base clock (MHz) || 600 || 800 || 844 || 866 || colspan="2" | 1108 || 1250 || 1400 || 1750 || 538 || 600 || {{dunno}} || 847 || 900 || 1200 
|-
| {{rh}} colspan="3" | Max stock GPU base [[GFLOPS]]{{efn|name="SFLOPS"}} || 480 || 614.4 || 648.1 || 886.7 || colspan="2" | 1134.5 || 1760 || 1971.2 || 1792 || 86 || {{dunno}} || {{dunno}} || {{dunno}} || 345.6 || 460.8 
|- style="border-top:0.2em solid grey"
| rowspan="2" {{rh}} colspan="3" | 3D engine{{efn|[[Unified shader model|Unified shaders]] : [[Texture mapping unit|texture mapping unit]]s : [[Render output unit|render output unit]]s}} || Up to 400:20:8 || colspan="2" | Up to 384:24:6 || colspan="3" | Up to 512:32:8 || colspan="2" | Up to 704:44:16<ref>{{cite news|last1=Cutress|first1=Ian|title=Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm|url=https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3|accessdate=7 February 2018|publisher=Anandtech|date=1 February 2018}}</ref> || Up to 512:?:? || 80:8:4 || colspan="3" | 128:8:4 || Up to 192:?:? ||  Up to 192:?:? 
|-
| colspan="3" | IOMMUv1 || colspan="5" | [[Heterogeneous Memory Management|IOMMUv2]] || || colspan="3" | IOMMUv1 || colspan="2" {{dunno}} || IOMMUv2
|- style="border-top:0.2em solid grey"
| {{rh}} colspan="3" | Video decoder || colspan="3" | [[Unified Video Decoder#UVD 3|UVD 3.0]] || [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || colspan="2" | [[Unified Video Decoder#UVD 6|UVD 6.0]] || rowspan="2" colspan="2" | [[Unified Video Decoder#VCN 1|VCN 1.0]]<ref>{{cite news|last1=Larabel|first1=Michael|title=Radeon VCN Encode Support Lands in Mesa 17.4 Git|url=https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands|accessdate=20 November 2017|publisher=Phoronix|date=17 November 2017}}</ref> || || [[Unified Video Decoder#UVD 3|UVD 3.0]] || [[Unified Video Decoder#UVD 4|UVD 4.0]] || [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || [[Unified Video Decoder#UVD 6|UVD 6.0]] || [[Unified Video Decoder#UVD 6|UVD 6.3]] || rowspan=2 | [[Unified Video Decoder#VCN 1|VCN 1.0]]
|-
| {{rh}} colspan="3" | Video encoder || {{N/A}} || colspan="2" | [[Video Coding Engine#VCE 1.0|VCE 1.0]] || [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan="2" | [[Video Coding Engine#VCE 3.0|VCE 3.1]] || || {{N/A}} || colspan="2" | [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan="2" | [[Video Coding Engine#VCE 3.0|VCE 3.1]]
|-
| {{rh}} colspan="3" | GPU power saving || [[Engineering:AMD PowerPlay|PowerPlay]] || colspan="7" | [[Engineering:AMD PowerTune|PowerTune]] || || [[Engineering:AMD PowerPlay|PowerPlay]] || colspan="5" | [[Engineering:AMD PowerTune|PowerTune]]<ref>{{citation |url=http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf |title=AMD's Graphics Core Next (GCN) Architecture |author=Tony Chen |author2=Jason Greaves |work=AMD |accessdate=13 August 2016}}</ref>
|- 
| {{rh}} colspan="3" | [[AMD TrueAudio|TrueAudio]] || colspan="3" rowspan="2" {{N/A}} || colspan="6" {{ya}}<ref>{{cite web |url=http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/ |title=A technical look at AMD's Kaveri architecture |publisher=Semi Accurate |accessdate=6 July 2014}}</ref> || rowspan="2" {{N/A}} || colspan="5" {{ya}}
|- 
| {{rh}} colspan="3" | [[Software:FreeSync|FreeSync]] || colspan="6" style="background:#DFD;" | 1<br />2 || colspan="5" style="background:#DFD;" | 1<br />2
|-
| {{rh}} colspan="3" | [[HDCP]]{{efn|name="DRM"}} || colspan="3" {{dunno}} || colspan="3" | 1.4 || colspan="3" | 1.4<br />2.2 || {{dunno}} || colspan="4" | 1.4 || 1.4<br />2.2
|-
| {{rh}} colspan="3" | [[PlayReady]]{{efn|name="DRM"}} || colspan="6" {{n/a}} || colspan="2" | 3.0 not yet || || colspan="5" {{n/a}} || 3.0 not yet
|-
| {{rh}} colspan="3" | [[AMD Eyefinity|Supported displays]]{{efn|To feed more than two displays, the additional panels must have native [[Engineering:DisplayPort|DisplayPort]] support.<ref>{{cite web | url=http://support.amd.com/en-us/search/faq/154 | title=How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card? | publisher=AMD | accessdate=8 December 2014}}</ref> Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.}} || 2–3 || colspan="3" | 2–4 || colspan="2" | 3 || colspan="2" | 3 (desktop)<br >4 (mobile, embedded) || 4 || colspan="4" | 2 || 3 || 4
|- style="border-top:0.2em solid grey"
| {{rh}} colspan="3" | <code>/drm/radeon</code>{{efn|name="drm"}}<ref>{{cite web |url=http://airlied.livejournal.com/68805.html |title=DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33 |date=26 November 2009 |accessdate=16 January 2016 |last1=Airlie |first1=David}}</ref><ref name="Radeon Feature Matrix">{{cite web |url=http://xorg.freedesktop.org/wiki/RadeonFeature/ |title=Radeon feature matrix |work=[[Organization:Freedesktop.org|freedesktop.org]] |accessdate=10 January 2016}}</ref> || colspan="5" {{ya}} || colspan="4" {{N/A}} || colspan="4" {{ya}} || colspan=2 {{N/A}}
|-
| {{rh}} colspan="3" | <code>/drm/amdgpu</code>{{efn|name="drm"}}<ref>{{cite web |url=http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf |title=XDC2015: AMDGPU |date=16 September 2015 |last1=Deucher |first1=Alexander |accessdate=16 January 2016}}</ref> || colspan="3" {{N/A}} || {{ya}}<ref name="amdgpu_1.2">{{cite web |url=https://lists.x.org/archives/xorg-announce/2016-November/002741.html |title=[ANNOUNCE] xf86-video-amdgpu 1.2.0 |author=Michel Dänzer |work=lists.x.org |date=17 November 2016}}</ref> || colspan="5" {{ya}} || {{N/A}} || colspan="3" {{ya}}<ref name="amdgpu_1.2"/> || colspan=2 {{ya}}
|}
{{noteslist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a [[Fused multiply–add|FMA]] operation.}}
{{efn|name="drm"|DRM ([[Software:Direct Rendering Manager|Direct Rendering Manager]]) is a component of the Linux kernel. Support in this table refers to the most current version.}}
{{efn|name="DRM"|To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.}}
}}<noinclude>{{documentation|content=
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== See also ==
* [[Template:AMD x86 CPU features]]
* [[Template:AMD GPU features]]


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