Engineering:Multi-cycle processor: Difference between revisions
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Latest revision as of 20:41, 11 November 2023
A multi-cycle processor is a processor that carries out one instruction over multiple clock cycles, often without starting up a new instruction in that time (as opposed to a pipelined processor).[1][2][3][4]
See also
- Single-cycle processor, a processor executing (and finishing) one instruction per clock cycle
References
- ↑ Harris (2016). Digital Design and Computer Architecture ARM Edition. Elsevier. sec. 7.3-7.5. ISBN 978-0-12-800056-4.
- ↑ "Multi-cycle MIPS Processor". Zürich, Switzerland: ETH Zurich. https://syssec.ethz.ch/content/dam/ethz/special-interest/infk/inst-infsec/system-security-group-dam/education/Digitaltechnik_14/21_Architecture_MultiCycle.pdf.
- ↑ "Lecture 9: Processor design – multi cycle". Edinburgh , Scotland: University of Edinburgh. https://www.inf.ed.ac.uk/teaching/courses/inf2c-cs/13-14/lectures/lec09-slides.pdf.
- ↑ "ESE 545: Computer Architecture: Designing a Multicycle Processor". Stony Brook, New York: Stony Brook University. http://www.ece.sunysb.edu/~midor/ESE545/CA_Multicycle%20processor%20design.pdf.
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