Alewife (multiprocessor): Difference between revisions

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'''Alewife''' was a cache coherent multiprocessor developed in the early 1990s by a group led by Anant Agarwal at the [[Organization:Massachusetts Institute of Technology|Massachusetts Institute of Technology]].<ref>{{citation|title=The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor|last1=Agarwal|first1=A.|first2=D.|last2=Chaiken |first3=K.|last3=Johnson | first4=D.|last4=Kranz |first5=J.|last5=Kubiatowicz |first6=K.|last6=Kurihara |first7=B. H.|last7=Lim |first8=G.|last8=Maa |first9=D.|last9=Nussbaum|display-authors=8|publisher=Massachusetts Institute of Technology|series=Tech. Report TM-454|year=1991|url=http://portal.acm.org/citation.cfm?id=889587}}.</ref><ref>{{citation|title=The MIT Alewife Machine|last1=Agarwal|first1= A. |last2=Bianchini|first2= R.|last3= Chaiken|first3= D.|last4=Chong|first4=F. T.|last5= Johnson|first5= K. L.|last6= Kranz|first6= D.|last7= Kubiatowicz|first7= J. D.|first8= Beng-Hong |last8=Lim |last9= Mackenzie|first9= K.|display-authors=8|journal=Proceedings of the IEEE|volume=87|issue=3|year=1999|doi=10.1109/5.747864|pages=430–444}}.</ref> It was based on a network of up to 512 processing nodes, each of which used the '''[[Engineering:Sparcle|Sparcle]]''' computer architecture,<ref>{{citation|title=Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors |journal=IEEE Micro|volume=13|issue=3|year=1993|pages=48–61|first1=Anant|last1=Agarwal|first2=John|last2=Kubiatowicz |first3=David|last3=Kranz|first4=Beng-Hong|last4=Lim|first5=Donald|last5=Yeung|first6=Godfrey|last6=D'Souza|first7=Mike|last7=Parkin |doi=10.1109/40.216748|s2cid=14678370 }}.</ref> which was formed by modifying a [[Company:Sun Microsystems|Sun Microsystems]] [[SPARC]] CPU to include the APRIL techniques for fast [[Context switch|context switch]]es.<ref>{{citation|last1=Agarwal|first1=A.|last2=Lim|first2=B.-H.|last3=Kranz|first3=D.|last4=Kubiatowicz|first4=J.|year=1990| doi=10.1109/ISCA.1990.134498|contribution=APRIL: a processor architecture for multiprocessing|pages=104–114|title=Proc. 17th Annual International Symposium on Computer Architecture (ISCA 1990)}}.</ref>   
{{Short description|Computer system developed at the Massachusetts Institute of Technology}}
'''Alewife''' was a cache coherent multiprocessor developed in the early 1990s by a group led by Anant Agarwal at the [[Organization:Massachusetts Institute of Technology|Massachusetts Institute of Technology]].<ref>{{citation|title=The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor|last1=Agarwal|first1=A.|first2=D.|last2=Chaiken |first3=K.|last3=Johnson | first4=D.|last4=Kranz |first5=J.|last5=Kubiatowicz |first6=K.|last6=Kurihara |first7=B. H.|last7=Lim |first8=G.|last8=Maa |first9=D.|last9=Nussbaum|display-authors=8|publisher=Massachusetts Institute of Technology|series=Tech. Report TM-454|year=1991|url=http://portal.acm.org/citation.cfm?id=889587}}.</ref><ref>{{citation|title=The MIT Alewife Machine|last1=Agarwal|first1= A. |last2=Bianchini|first2= R.|last3= Chaiken|first3= D.|last4=Chong|first4=F. T.|last5= Johnson|first5= K. L.|last6= Kranz|first6= D.|last7= Kubiatowicz|first7= J. D.|first8= Beng-Hong |last8=Lim |last9= Mackenzie|first9= K.|display-authors=8|journal=Proceedings of the IEEE|volume=87|issue=3|year=1999|doi=10.1109/5.747864|pages=430–444}}.</ref> It was based on a network of up to 512 processing nodes, each of which used the '''[[Engineering:Sparcle|Sparcle]]''' computer architecture,<ref>{{citation|title=Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors |journal=IEEE Micro|volume=13|issue=3|year=1993|pages=48–61|first1=Anant|last1=Agarwal|first2=John|last2=Kubiatowicz |first3=David|last3=Kranz|first4=Beng-Hong|last4=Lim|first5=Donald|last5=Yeung|first6=Godfrey|last6=D'Souza|first7=Mike|last7=Parkin |doi=10.1109/40.216748|s2cid=14678370 }}.</ref> which was formed by modifying a [[Company:Sun Microsystems|Sun Microsystems]] [[SPARC]] CPU to include the APRIL techniques for fast [[Context switch|context switch]]es.<ref>{{citation|last1=Agarwal|first1=A.|last2=Lim|first2=B.-H.|last3=Kranz|first3=D.|last4=Kubiatowicz|first4=J.|year=1990| doi=10.1109/ISCA.1990.134498|contribution=APRIL: a processor architecture for multiprocessing|pages=104–114|title=Proc. 17th Annual International Symposium on Computer Architecture (ISCA 1990)|hdl=1721.1/149177|hdl-access=free}}.</ref>   
 
The Alewife project was one of two predecessors cited by the creators of the popular Beowulf cluster multiprocessor.<ref>{{citation|contribution=Beowulf: A parallel workstation for scientific computing|first1=Thomas|last1=Sterling|first2=Donald J.|last2=Becker|first3=Daniel|last3=Savarese|first4=John E.|last4=Dorband|first5=Udaya A.|last5=Ranawake|first6=Charles V.|last6=Packer|title=Proc. 24th Int. Conf. Parallel Processing|volume=I|pages=11–14|year=1995|url=http://citeseer.ist.psu.edu/sterling95beowulf.html}}.</ref>
The Alewife project was one of two predecessors cited by the creators of the popular Beowulf cluster multiprocessor.<ref>{{citation|contribution=Beowulf: A parallel workstation for scientific computing|first1=Thomas|last1=Sterling|first2=Donald J.|last2=Becker|first3=Daniel|last3=Savarese|first4=John E.|last4=Dorband|first5=Udaya A.|last5=Ranawake|first6=Charles V.|last6=Packer|title=Proc. 24th Int. Conf. Parallel Processing|volume=I|pages=11–14|year=1995|url=http://citeseer.ist.psu.edu/sterling95beowulf.html}}.</ref>


Latest revision as of 17:24, 24 June 2025

Short description: Computer system developed at the Massachusetts Institute of Technology

Alewife was a cache coherent multiprocessor developed in the early 1990s by a group led by Anant Agarwal at the Massachusetts Institute of Technology.[1][2] It was based on a network of up to 512 processing nodes, each of which used the Sparcle computer architecture,[3] which was formed by modifying a Sun Microsystems SPARC CPU to include the APRIL techniques for fast context switches.[4]

The Alewife project was one of two predecessors cited by the creators of the popular Beowulf cluster multiprocessor.[5]

References

  1. ↑ Agarwal, A.; Chaiken, D.; Johnson, K.; Kranz, D.; Kubiatowicz, J.; Kurihara, K.; Lim, B. H.; Maa, G. et al. (1991), The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor, Tech. Report TM-454, Massachusetts Institute of Technology, http://portal.acm.org/citation.cfm?id=889587 .
  2. ↑ Agarwal, A.; Bianchini, R.; Chaiken, D.; Chong, F. T.; Johnson, K. L.; Kranz, D.; Kubiatowicz, J. D.; Lim, Beng-Hong et al. (1999), "The MIT Alewife Machine", Proceedings of the IEEE 87 (3): 430–444, doi:10.1109/5.747864 .
  3. ↑ Agarwal, Anant; Kubiatowicz, John; Kranz, David; Lim, Beng-Hong; Yeung, Donald; D'Souza, Godfrey; Parkin, Mike (1993), "Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors", IEEE Micro 13 (3): 48–61, doi:10.1109/40.216748 .
  4. ↑ Agarwal, A.; Lim, B.-H.; Kranz, D.; Kubiatowicz, J. (1990), "APRIL: a processor architecture for multiprocessing", Proc. 17th Annual International Symposium on Computer Architecture (ISCA 1990), pp. 104–114, doi:10.1109/ISCA.1990.134498 .
  5. ↑ Sterling, Thomas; Becker, Donald J.; Savarese, Daniel; Dorband, John E.; Ranawake, Udaya A.; Packer, Charles V. (1995), "Beowulf: A parallel workstation for scientific computing", Proc. 24th Int. Conf. Parallel Processing, I, pp. 11–14, http://citeseer.ist.psu.edu/sterling95beowulf.html .

External links




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