Engineering:MCST-R500S
From HandWiki
Revision as of 04:11, 5 November 2021 by imported>JOpenQuest (simplify)
General Info | |
---|---|
Launched | 2007 |
Designed by | Moscow Center of SPARC Technologies (MCST) |
Common manufacturer(s) | |
Performance | |
Max. CPU clock rate | 500 MHz |
Architecture and classification | |
Instruction set | SPARC V8 |
Physical specifications | |
Cores |
|
History |
The MCST R500S (Russian: МЦСТ R500S) is a 32-bit system-on-a-chip, developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.
MCST R500S Highlights
- implements the SPARC V8 instruction set architecture (ISA)
- dual-core
- the two cores can work in redundancy to increase reliability of the system.
- core specifications:
- in-order, single-issue
- 5-stage integer pipeline
- 7-stage floating-point pipeline
- 16 KB L1 instruction cache
- 32 KB L1 data cache
- shared 512KB L2 cache
- integrated controllers:
- 500 МHz clock rate
- 130 nm process
- die size 100 mm2
- ~45 million transistors
- power consumption 5W
References
Original source: https://en.wikipedia.org/wiki/MCST-R500S.
Read more |