Engineering:XCore XS1-L1
 An XMOS Xcore-L processor, 48 TQFP package, 7×7 mm. | |
| General Info | |
|---|---|
| Launched | 2009 |
| Max. CPU clock rate | to 500 MHz |
| Architecture and classification | |
| Instruction set | XCore XS1 |
| Physical specifications | |
| Cores |
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| Package(s) |
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| History | |
The XS1-L1[1] is a 32-bit processor designed by XMOS, featuring support for up to 8 concurrent threads. It was available as of June 2009 running at 400 MHz. As of April 2010 500 MHz versions are available. Each thread can run at up to 125 MHz; four threads follow each other through the pipeline, resulting in a top speed of 500 MIPS if at least four threads are active. The 500 MIPS of each core is equally distributed over all active threads. This allows the use of extra threads in order to hide latency.
Description
An XS1-L node comprises a single core processor and a switch. The execution core has a data path, a memory, and register banks for eight threads. The switches of two or more XS1-L nodes can be connected using a link, whereupon threads on all of the cores can communicate with each other by exchanging messages through the switches. The switching mechanism is abstracted by means of a channel, a virtual connection between two threads. The switch has eight external links, permitting a maximum throughput of 3.2 GBits/s to other cores.
An XS1-L1 device comprises a single XS1-L node; an XS1-L2 device comprises two XS1-L nodes connected by means of 4 links.[1][2]
Instruction set architecture
Each thread has access to 12 general purpose registers, and a standard 3-operand instruction set is used for programming the thread.[3] The instruction set is encoded densely, encoding most instructions in 16 bits, where 11 bits are used for specifying 3 operands, and 5 bits are used to encode the opcode. Less frequently used instructions are encoded in 32 bits. The instruction set is a load-store instruction set. All instructions execute in a single cycle. If an instruction does not need data from memory (for example, arithmetic operations), the instruction will prefetch a word of instructions. This acts like a very small instruction cache, but its behaviour can be predicted at compile time, making timing behaviour as predictable as functional behaviour.
The XS1 is an event driven processor which enables the processor to stop a thread and restart it when an event is ready. In addition, a thread may be interrupted in order to deal with some external events.
Concurrency
The core runs eight threads concurrently. These threads can communicate and synchronise using memory, registers, channels, locks, or synchronisers.
- Each thread has single-cycle access to memory; and as such the single core can be viewed as an 8-processor SMP.
- Threads can use locks in order to guarantee mutual access. Access to locks is via single instructions.
- Threads can also use Channels to communicate and synchronise allowing a CSP style of programming. Channels can be operated on using single cycle instructions.
- Finally a Barrier can be used; a barrier is entered using a single instruction, and when all threads that want to synchronise have reached the barrier they are all released within a single thread-cycle.
Switch
The XS1-L has a XSwitch that enables the core to communicate with other cores. The switch has four internal links into the core, and eight external links, four of whom are available on I/O pins.
References
- ↑ 1.0 1.1 "XS1-L01A-TQ128 Datasheet". Xmos Ltd.. 2012-10-15. https://www.xmos.com/published/xs1-l01a-tq128-datasheet?version=latest. Retrieved 2018-04-06.
- ↑ "XS1-L02A-QF124 Datasheet". Xmos Ltd.. 2012-03-26. https://www.xmos.com/published/xs1-l02a-qf124-datasheet?version=latest.
- ↑ "XMOS XS1 Instruction Set Architecture". Xmos Ltd.. 2009-01-19. https://www.xmos.com/download/public/XM-000324-RF-1.pdf.
External links
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