Engineering:Subthreshold slope
The subthreshold slope is a feature of a MOSFET's current–voltage characteristic.
In the subthreshold region, the drain current behaviour—though being controlled by the gate terminal—is similar to the exponentially decreasing current of a forward biased diode. Therefore, a plot of drain current versus gate voltage with drain, source, and bulk voltages fixed will exhibit approximately log-linear behaviour in this MOSFET operating regime. Its slope is the subthreshold slope.
The subthreshold slope is also the reciprocal value of the subthreshold swing Ss-th which is usually given as:[1]
[math]\displaystyle{ S_{s-th} = \ln(10) {kT \over q}\left(1+{C_d \over C_{ox}}\right) }[/math]
[math]\displaystyle{ C_d }[/math] = depletion layer capacitance
[math]\displaystyle{ C_{ox} }[/math] = gate-oxide capacitance
[math]\displaystyle{ {kT \over q} }[/math] = thermal voltage
The minimum subthreshold swing of a conventional device can be found by letting [math]\displaystyle{ \textstyle {C_{d}} \rightarrow 0 }[/math] and/or [math]\displaystyle{ \textstyle {C_{ox}} \rightarrow \infty }[/math], which yield [math]\displaystyle{ S_{s-th, \min} = \ln(10) {kT \over q} }[/math](known as thermionic limit) and 60 mV/dec at room temperature (300 K). A typical experimental subthreshold swing for a scaled MOSFET at room temperature is ~70 mV/dec, slightly degraded due to short-channel MOSFET parasitics.[2]
A dec (decade) corresponds to a 10 times increase of the drain current ID.
A device characterized by steep subthreshold slope exhibits a faster transition between off (low current) and on (high current) states.
References
- ↑ Physics of Semiconductor Devices, S. M. Sze. New York: Wiley, 3rd ed., with Kwok K. Ng, 2007, chapter 6.2.4, p. 315, ISBN:978-0-471-14323-9.
- ↑ Auth, C.; Allen, C.; Blattner, A.; Bergstrom, D.; Brazier, M.; Bost, M.; Buehler, M.; Chikarmane, V. et al. (2012). "A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors". 2012 Symposium on VLSI Technology (VLSIT). pp. 131. doi:10.1109/VLSIT.2012.6242496. ISBN 978-1-4673-0847-2.
External links
- Optimization of Ultra-Low-Power CMOS Transistors; Michael Stockinger, 2000
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