Chipkill
Chipkill is IBM's trademark for a form of advanced error checking and correcting (ECC) computer memory technology that protects computer memory systems from any single memory chip failure as well as multi-bit errors from any portion of a single memory chip.[1][2] One simple scheme to perform this function scatters the bits of a Hamming code ECC word across multiple memory chips, such that the failure of any single memory chip will affect only one ECC bit per word. This allows memory contents to be reconstructed despite the complete failure of one chip. Typical implementations use more advanced codes, such as a BCH code, that can correct multiple bits with less overhead.
Chipkill is frequently combined with dynamic bit-steering, so that if a chip fails (or has exceeded a threshold of bit errors), another, spare, memory chip is used to replace the failed chip. The concept is similar to that of RAID, which protects against disk failure, except that now the concept is applied to individual memory chips. The technology was developed by the IBM Corporation in the early and middle 1990s. An important RAS feature, Chipkill technology is deployed primarily on SSDs, mainframes and midrange servers.
An equivalent system from Sun Microsystems is called Extended ECC, while equivalent systems from HP are called Advanced ECC[3] and Chipspare. A similar system from Intel, called Lockstep memory, provides double-device data correction (DDDC) functionality.[4] Similar systems from Micron, called redundant array of independent NAND (RAIN), and from SandForce, called RAISE level 2, protect data stored on SSDs from any single NAND flash chip going bad.[5][6]
A 2009 paper using data from Google's datacentres[7] provided evidence demonstrating that in observed Google systems, DRAM errors were recurrent at the same location, and that 8% of DIMMs were affected each year. Specifically, "In more than 85% of the cases a correctable error is followed by at least one more correctable error in the same month". DIMMs with chipkill error correction showed a lower fraction of DIMMs reporting uncorrectable errors compared to DIMMs with error correcting codes that can only correct single-bit errors. A 2010 paper from University of Rochester also showed that Chipkill memory gave substantially lower memory errors, using both real world memory traces and simulations.[8]
See also
- ECC memory
- Lockstep (computing)
- Memory ProteXion
- Redundant array of independent memory
- Single-error correction and double-error detection (SECDED)
References
- ↑ Timothy J. Dell (1997-11-19). "A White Paper on the Benefits of Chipkill-Correct ECC for PC Server Main Memory". IBM. http://www.ece.umd.edu/courses/enee759h.S2003/references/ibm_chipkill.pdf. Retrieved 2015-02-02.
- ↑ "Enhancing IBM Netfinity Server Reliability: IBM Chipkill Memory". IBM. 2000. http://www.ece.umd.edu/courses/enee759h.S2003/references/chipkill_white_paper.pdf. Retrieved 2015-02-02.
- ↑ "Best Practice Guidelines for ProLiant Servers with the Intel Xeon 5500 processor series Engineering Whitepaper, 1st Edition". HP. May 2009. p. 8. http://ftp.hp.com/pub/c-products/servers/options/Memory-Config-Recommendations-for-Intel-Xeon-5500-Series-Servers-Rev1.pdf. Retrieved 2014-09-09.
- ↑ Thomas Willhalm (2014-07-11). "Independent Channel vs. Lockstep Mode – Drive your Memory Faster or Safer". Intel. https://software.intel.com/en-us/blogs/2014/07/11/independent-channel-vs-lockstep-mode-drive-you-memory-faster-or-safer. Retrieved 2015-02-02.
- ↑ Lee Hutchinson. "Solid-state revolution: in-depth on how SSDs really work". 2012.
- ↑ Eric Slack. "How to Make Reliable SSDs - Reliable NAND Flash".
- ↑ Schroeder, Bianca; Pinheiro, Eduardo; Weber, Wolf-Dietrich (2009). "DRAM errors in the wild: A large-scale field study". Proceedings of the eleventh international joint conference on Measurement and modeling of computer systems. SIGMETRICS '09. ACM. pp. 193–204. doi:10.1145/1555349.1555372. ISBN 9781605585116. http://www.cs.toronto.edu/~bianca/papers/sigmetrics09.pdf. Retrieved 7 September 2011.
- ↑ ""A Realistic Evaluation of Memory Hardware Errors and Software System Susceptibility". Usenix Annual Tech Conference 2010". 2010. https://www.usenix.org/legacy/events/atc10/tech/full_papers/Li.pdf.
External links
- Intel E7500 Chipset MCH Intelx4 Single Device Data Correction (x4 SDDC) Implementation and Validation, Intel Application note AP-726, August 2002.
- DRAM study turns assumptions about errors upside down, Ars Technica, October 7, 2009
- Enabling Memory Reliability, Availability, and Serviceability Features on Dell PowerEdge Servers, 2005
- Chipkill correct memory architecture, August 2000, by David Locklear
- The Mathematics of Chipkill ECC, October 2015, by Bob Day
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