Biography:Priyadarsan Patra

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Priyadarsan Patra
File:Dr. Priyadarshan Patra - Nov 2023.jpg
Priyadarsan Patra, Vice-Chancellor of NIST University
Born1961
Brahmapur, Odisha, India
CitizenshipAmerican
Alma materRavenshaw University; Indian Institute of Science; University of Massachusetts Amherst; The University of Texas at Austin
OccupationAcademic administrator; computer scientist; semiconductor architect
Known forLow-power circuit design; system-on-chip (SoC) validation; VLSI algorithms; academic leadership; nonprofit founder
AwardsIntel Hero Recognition (finalist)[1][2]; Distinguished Young Leader Award (OSA)[1]; Fellow, IEI; Fellow, IETE; Senior Member, IEEE and ACM[3]

Priyadarsan Patra (born 1961) is a computer scientist, semiconductor researcher, academic administrator, and nonprofit founder. He is the founding Vice Chancellor of NIST University, Odisha, and formerly served as Chief Architect and Principal Scientist at Intel Corporation in the United States.[4][1] He is the founding chair of the global IEEE System Validation and Debug Technology Committee (SVDTC).[5]

Early life and education

Patra was born in Brahmapur, Odisha. He earned a Bachelor of Engineering in Electronics and Telecommunication from the Indian Institute of Science, Bangalore.[3] He received an M.S. in Computer Science from the University of Massachusetts Amherst and a Ph.D. from The University of Texas at Austin.[3] His dissertation examined extremely low-power computation and adiabatic circuit architectures.[6]

Industry career

Patra worked at Intel Corporation for 22 years, specializing in systems-on-chip (SoC) and server architecture.[1] He served as Chief Architect and Principal Scientist in Intel's Data Center Group (2016–2018). As the founding chair of the IEEE SVDTC, he contributed to global white papers on post-silicon validation and silicon debug.[5] He serves on the advisory boards of semiconductor companies including Silizium Circuits and Cirkitex.[7]

Academic and administrative career

From 2021 to 2024, Patra was Pro Vice-Chancellor and Distinguished Professor at DIT University, Dehradun.[8] He previously served as Dean of Research at Xavier University.[9] While in Uttarakhand, Patra advocated for the use of technology-driven interventions, such as IoT and remote sensing, to improve regional disaster management and infrastructure resilience.[10] In 2024, he was appointed founding Vice-Chancellor of NIST University.[4] In 2025, he presented the annual report at the 2nd Convocation alongside the Governor of Odisha.[11] In January 2026, he presided over NIST's 29th Foundation Day.[12] He also serves as an Advisor to the IEEE Bhubaneswar Section.[3]

He has delivered keynote addresses at international forums including the 2025 Conference on Cyber-Physical Systems, Power Electronics and Electric Vehicles (ICPEEV) at Mahindra University,[13] and served as the Chief Guest at the 13th IEEE International Conference on Intelligent Systems and Embedded Design (ISED-2025) at NIT Raipur.[14] Patra authored the foreword for the Springer Nature publication Proceedings of the 3rd International Conference on Opportunities and Challenges for a Resilient Future (2025).[15]

Research and publications

Patra has authored six books and more than 70 peer-reviewed papers in low-power VLSI design and system validation.[3]

Selected Books:

  • Low-power High-level Synthesis for Nanoscale CMOS Circuits. Springer. 2008. ISBN 978-0-387-76474-0. 
  • Eco-Friendly Computing and Communication Systems (Springer, 2012)[16]
  • Artificial Intelligence-Driven Circuits and Systems (Springer Nature, 2022)[1]
  • The Internet of Medical Things (IET, 2022)[17]

Selected Articles:

  • Patra, Priyadarsan (2007). "On the cusp of a validation wall". IEEE Design & Test of Computers (IEEE) 24 (2): 193–196. doi:10.1109/MDT.2007.23. 
  • Mandal, M., Sahoo, S.K., Patra, P., et al. (2020). "In silico ranking of phenolics for therapeutic effectiveness on cancer stem cells." BMC Bioinformatics, 21, 499.[18]
  • Patra, P. et al. (2018). "Debug infrastructure for system-on-chips." IEEE SVDTC White Paper.[5]
  • Chen, K., Malik, S., & Patra, P. (2008). "Runtime validation of memory ordering using constraint graph checking." HPCA-14.[19]

Patents

Patra holds over 10 patents in the United States and internationally, primarily assigned to Intel Corporation, related to semiconductor architecture, circuit synthesis, and system-on-chip validation. Notable patents include:

  • "Power consumption reduction for domino circuits" US patent 6529861, published 2003-03-04, assigned to Intel Corporation
  • "Method and device for dynamically verifying a processor architecture" US patent 8055697, published 2011-11-08, assigned to Intel Corporation
  • "Test, validation, and debug architecture" US patent 10198333, published 2019-02-05, assigned to Intel Corporation
  • "Phase optimization for low power domino circuits" US patent 6556962, published 2003-04-29, assigned to Intel Corporation

Social entrepreneurship

In 1993, Patra founded the Sustainable Economic and Educational Development Society (SEEDS), a nonprofit organization focused on sustainable development.[2] SEEDS is a US-registered 501(c)(3) public charity that has engaged in over 50 projects in areas including education, rural economic development, disaster relief, women’s empowerment, and appropriate technology.

He served as General Secretary of the Odisha Society of the Americas (OSA) from 2007 to 2009.[20] In 2025, he organized a social security awareness event at NIST in collaboration with the EPFO.[21] Patra has contributed expert analysis to Eurasia Review on topics concerning the societal impact of technology and global development.[22]

Honours and affiliations

  • Intel Hero Recognition (finalist).[1]
  • Distinguished Young Leader Award (OSA).[1]
  • Fellow, Institution of Engineers (India)[23]
  • Fellow, IETE[24]
  • Senior Member, IEEE[25]
  • Senior Member, ACM[26]

References

  1. ↑ 1.0 1.1 1.2 1.3 1.4 1.5 1.6 "Prof. Priyadarsan Patra Speaker Profile". https://ardorcomm-media.com/speaker/prof-priyadarsan-patra/. 
  2. ↑ 2.0 2.1 "Leadership: Priyadarsan Patra". 2019-04-05. https://us.seedsnet.org/about-us/leadership-page/. 
  3. ↑ 3.0 3.1 3.2 3.3 3.4 "Priyadarsan Patra Author Details". https://ieeexplore.ieee.org/author/37088427551. 
  4. ↑ 4.0 4.1 "Leadership - Vice Chancellor". http://www.nist.edu/about/leadership.php. 
  5. ↑ 5.0 5.1 5.2 "SVDTC Technical Committee". https://ieee-ceda.org/activities/technical-committees/svdtc. 
  6. ↑ Priyadarsan Patra (1995). Approaches to the design of circuits for low-power computation (Thesis). University of Texas at Austin.
  7. ↑ "Prof. Priyadarsan Patra on Board". 2024. https://siliziumcircuits.com/281/prof-priyadarsan-patra-on-board. 
  8. ↑ "Research Advisory Board". https://www.dituniversity.edu.in/about-us/research-advisory-board. 
  9. ↑ "Officers of the University". https://xavieruniversity.org/about/officers-of-the-university.html. 
  10. ↑ Singh, Arun Pratap (September 14, 2023). "Uttarakhand needs to focus on technology intervention for disaster management: Dr Patra". Garhwal Post. https://garhwalpost.in/ukhand-needs-to-focus-on-technology-intervention-for-disaster-management-dr-patra/. 
  11. ↑ "Navigate life with purpose, Guv exhorts youth". The Hans India. December 21, 2025. https://www.thehansindia.com/news/national/navigate-life-with-purpose-guv-exhorts-youth-1032636. 
  12. ↑ "NIST celebrates 29th foundation day". The New Indian Express. January 21, 2026. https://www.newindianexpress.com/states/odisha/2026/Jan/21/nist-celebrates-29th-foundation-day. 
  13. ↑ "Keynote Speakers: ICPEEV 2025". https://www.mahindrauniversity.edu.in/icpeev-2025/. 
  14. ↑ "NIT Raipur Inaugurates 13th IEEE International Conference on Intelligent Systems and Embedded Design". Press Information Bureau. December 17, 2025. https://www.pib.gov.in/PressReleasePage.aspx?PRID=2205438. 
  15. ↑ Sharma, Anjali Krishan; Joshi, Ashutosh, eds (2025). Proceedings of the 3rd International Conference on Opportunities and Challenges for a Resilient Future. Springer Nature. p. Foreword. ISBN 978-981-96-0930-7. 
  16. ↑ Eco-Friendly Computing and Communication Systems. Springer. 2012. ISBN 9783642321115. 
  17. ↑ The Internet of Medical Things. IET. 2022. 
  18. ↑ Mandal, Monalisa; Sahoo, Sanjeeb Kumar; Patra, Priyadarsan; Mallik, Saurav; Zhao, Zhongming (2020). "In silico ranking of phenolics for therapeutic effectiveness on cancer stem cells". BMC Bioinformatics 21 (Suppl 21). doi:10.1186/s12859-020-03849-z. PMID 33371879. 
  19. ↑ "Runtime validation of memory ordering using constraint graph checking". 14th International Conference on High-Performance Computer Architecture. IEEE. 2008. pp. 415–426. doi:10.1109/HPCA.2008.4658640. 
  20. ↑ "Past Leadership". 2023-01-19. https://www.odishasociety.org/past-leadership/. 
  21. ↑ "Social Security Awareness Event at NIST". The Daily Pioneer: p. 6. October 30, 2025. 
  22. ↑ "Analysis by Dr. Priyadarsan Patra". https://www.eurasiareview.com/author/dr-priyadarsan-patra/. 
  23. ↑ "IEI Professional Portal". https://www.ieindia.org/AdminUI/IEI-PPCEApplication.aspx. "Fellow Member Number: F-1276820" 
  24. ↑ "IETE Membership Directory". http://iete-elan.ac.in/elan/membership/membership.jsp. "Member Number: 503342" 
  25. ↑ "Author Profile". https://ieeexplore.ieee.org/author/37088427551. 
  26. ↑ "Award Recipients: Priyadarsan Patra". https://awards.acm.org/award-recipients/patra_4558664. 




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