CAST-32A
| Year started | 2014 |
|---|---|
| Latest version | A November 2016 |
| Organization | FAA |
| Domain | Aviation |
| Abbreviation | CAST-32A |
| Website | faa.gov |
CAST-32A, Multi-core Processors is a position paper,[1] by the Certification Authorities Software Team (CAST). It is not official guidance, but is considered informational by certification authorities such as the FAA and EASA. A key point is that Multi-core processor "interference can affect execution timing behavior, including worst case execution time (WCET)."[2]
The original document was published in 2014 by an "international group of certification and regulatory authority representatives."[3] The current revision A was released in 2016. "The Federal Aviation Administration (FAA) and European Aviation Safety Agency (EASA) worked with industry to quantify a set of requirements and guidance that should be met to certify and use multi-core processors in civil aviation, described e.g. in the FAA CAST-32A Position Paper and the EASA Use of MULticore proCessORs in airborne Systems (MULCORS) research report."[4] For applicants certifying under EASA, AMC 20-193 has now superseded CAST-32A since its release on 21 January 2022. It is expected that the FAA will release its Advisory Circular AC 20-193 guidance in 2023, which is expected to be almost identical to AMC 20-193. [5][6]
One of the first mixed-criticality multicore avionics systems is expected to be certified sometime in 2020.[7] The objectives of the standard are applicable to software on multicore processors, including the operating system.[8][9] However, the nature of the underlying processor hardware must be examined in detail to identify potential interference channels due to inter-core contention for shared resources.[10] Verification that multicore interference channels have been mitigated can be accomplished through the use of interference generators i.e. software tuned to create a heavy usage pattern on a shared resource.[11]
Objectives
The paper presents ten objectives that must be met for Design Assurance Level (DAL) A or B. Six of the objectives apply for DAL C. The paper does not apply for DAL D or E. [1]
| Objective | Applicable Design Assurance Levels |
|---|---|
| MCP Planning 1 | A, B, C |
| MCP Resource Usage 1 | A, B, C |
| MCP Resource Usage 2 | A, B |
| MCP Planning 2 | A, B, C |
| MCP Resource Usage 3 | A, B |
| MCP Resource Usage 4 | A, B |
| MCP Software 1 | A, B, C |
| MCP Software 2 | A, B, C |
| MCP Error Handling 1 | A, B |
| MCP Accomplishment Summary 1 | A, B, C |
References
- ↑ 1.0 1.1 "Multi-core Processors". Federal Aviation Administration. 2016-11-01. https://www.faa.gov/sites/faa.gov/files/aircraft/air_cert/design_approvals/air_software/cast-32A.pdf. Retrieved 2020-03-23.
- ↑ VanderLeest, Steven H.; Evripidou, Christos (2020-03-10). "An Approach to Verification of Interference Concerns for Multicore Systems (CAST-32A)". SAE Technical Paper Series. 1. SAE International. 1174–1181. doi:10.4271/2020-01-0016. https://www.sae.org/publications/technical-papers/content/2020-01-0016/. Retrieved 2020-03-11.
- ↑ Kühlert, Oliver (2020-02-11). "Multi-Core Ready to Become Airborne". Embedded Computing Design. https://www.embedded-computing.com/guest-blogs/multi-core-ready-to-become-airborne.
- ↑ Athavale, Jyotika; Mariani, Riccardo; Paulitsch, Michael (2019-03-19). "Flight Safety Certification Implications for Complex Multi-Core Processor Based Avionics Systems". 2019 IEEE International Reliability Physics Symposium (IRPS). IEEE. pp. 1–6. doi:10.1109/IRPS.2019.8720422. ISBN 978-1-5386-9504-3.
- ↑ Wolfe, Frank (2020-02-28). "EASA and FAA to Issue Further Guidance on Multicore Certification This Year". Avionics International. https://www.aviationtoday.com/2020/02/28/easa-and-faa-to-issue-further-guidance-on-multicore-certification-this-year/. Retrieved 2020-03-09.
- ↑ "Certification Authorities Software Team (CAST)". https://www.faa.gov/aircraft/air_cert/design_approvals/air_software/cast/.
- ↑ Radack, David; Tiedeman, Jr., Harold G.; Parkinson, Paul (2018). "Civil Certification of Multi-core Processing Systems in Commercial Avionics". Rockwell Collins. https://www.collinsaerospace.com/-/media/Project/CollinsAerospace/CollinsAerospace-Website/product-assets/marketing/M/Multicore%20processing%20systems/multi-core-certification-white-paper. Retrieved 2020-03-23.
- ↑ "DDC-I and Rapita Systems Simplify Verification and Certification of Multicore Avionics Applications". 2020-04-21. https://www.ddci.com/tag/cast-32a/. Retrieved 2020-03-23.
- ↑ Brown, Mark (2018-11-15). "CAST=32A: Significance and Implications". https://www.lynx.com/embedded-systems-learning-center/cast-32a-significance-and-implications. Retrieved 2020-12-11.
- ↑ Agirre, Irune; Abella, Jaume; Azkarate-askasua, Mikel; Cazorla, Francisco (2017-06-14). "On the Tailoring of CAST-32A CertificationGuidance to Real COTS Multicore Architectures". IEEE. https://core.ac.uk/reader/157811610. Retrieved 2020-03-23.
- ↑ VanderLeest, Steven H.; Evripidou, Christos (2020-03-10). "An Approach to Verification of Interference Concerns for Multicore Systems". SAE International Journal of Advances and Current Practices in Mobility (SAE) 2 (3): 1174–1181. doi:10.4271/2020-01-0016. https://www.sae.org/publications/technical-papers/content/2020-01-0016/. Retrieved 2020-03-23.
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