Company:CEVA, Inc.

CEVA, Inc.

Type	Public
Traded as	NASDAQ: CEVA S&P 600 Component
Industry	Semiconductor IP
Founded	2002
Headquarters	Mountain View, California , United States
Products	Signal processing platforms and AI processors
Revenue	US$87.51 million (2017)
Operating income	US$15.87 million (2017)
Net income	US$17.03 million (2017)
Total assets	US$276.82 million (2017)
Total equity	US$244.67 million (2017)
Number of employees	313 (2017)
Website	www.ceva-dsp.com

CEVA is a publicly listed semiconductor intellectual property (IP) company, headquartered in Mountain View, California and specializes in digital signal processor (DSP) technology. The company's main development facility is located in Herzliya, Israel and Sophia Antipolis, France. CEVA was recently named in the Israeli 100 companies list of technologies that changed the world.

History

CEVA was created in November 2002, through the combination of the DSP IP licensing division of DSP Group and Parthus Technologies plc (an Irish company that was founded in 1993).

The company develops semiconductor intellectual property core technologies for multimedia and wireless communications technology. CEVA claimed the largest number of baseband processors in 2010, and a 90% DSP IP market share in 2011. In July 2014 it acquired RivieraWaves SAS, a private company based in France.

Technologies and products

Imaging and Computer Vision

EVA develops solutions for low-cost, low-power computational photography and computer vision for a variety of markets including mobile, Automotive industry , surveillance, drones, AR/VR, wearables, action cameras and photography gear. The company provides vision DSP cores, deep neural network toolkits, real-time software libraries, hardware accelerators, and algorithm developer ecosystems. The goal of these solutions to deliver human-like visual perception to mass-market embedded devices, by offering a far more efficient solution that existing vision engines typically powered by GPUs.

CEVA-XM is a family of DSP IP cores dedicated to imaging and computer vision. The latest core is the fifth generation CEVA-XM6, designed to bring deep learning and artificial intelligence capabilities to low-power embedded systems, targeting mass-market intelligent vision applications. The CEVA-XM6 is designed for high-performance, deep-layered CNN implementations. It is based on a vector processor unit (VPU) architecture and includes optional 32-way SIMD vector floating-point unit, enhanced 3D data processing scheme for accelerated CNN performance, and a control code scalar unit.

Deep Learning and Neural Networks

The award-winning CEVA Deep Neural Network (CDNN) toolkit is part of an integrated hardware and software IP platform centered on the CEVA-XM computer vision and NeuPro AI cores. The CDNN toolkit’s aim is to simplify the development and deployment of deep learning systems on embedded devices and facilitate real-time execution in time-critical use cases, such as autonomous driving, sense-and-avoid drones, virtual and augmented reality, smart surveillance, smartphones, robotics, and other systems that utilize artificial intelligence for imaging and vision. NeuPro is CEVA’s newest family of dedicated low-power AI processors for deep learning at the edge. NeuPro processors are self-contained, specialized AI processors, scaling in performance for a broad range of end markets including IoT, smartphones, surveillance, automotive, robotics, medical and industrial. This group of products offers high-performance configurations ranging from 2 Tera Ops Per Second (TOPS) for the entry-level processor and 12.5 TOPS for the most advanced configuration.

Wireless Communication

CEVA designs a range DSP-based IP platforms targeting the entire scope of wireless communications, including terminals (smartphones, tablets, etc.), base stations, cellular IoT (NB-IoT and Cat-M1), remote radio heads and backhaul, wireline modems, and home networking. The company’s CEVA-X and CEVA-XC product lines facilitate these use cases. The CEVA-X1 IoT processor handles cellular IoT protocol stack and baseband PHY control, including LTE Cat-NB1, Cat-NB2, Cat-M1, Sigfox, LoRa, Wi-Fi 802.11n, 802.11ah, Bluetooth, BLE, and Zigbee/Thread. It also supports positioning and motion-sensing functions, including GNSS (GPS, Beidou, GLONASS, Galileo), fusion of multiple indoor positioning and activity sensors, voice activation, and sound processing. The CEVA-XC5 DSP vector processor is designed for LPWAN (LTE Cat-1 or Cat-M1) standards and can also concurrently support  the processing loads of other wireless standards including Wi-Fi 802.11n, PLC, 802.15.4g, ZigBee/Thread, GNSS, or any IoT communications standard.

The CEVA-XC12 is a scalable DSP architecture designed for multi-gigabit class modems. This includes 5G use cases, LTE-Advanced Pro Evolution, enhanced Mobile Broadband (eMBB), Licensed Assisted Access (LAA), MulteFire carrier aggregation, LTE/Wi-Fi Aggregation(LWA), cellular V2X, Wi-Fi 802.11ax, WiGig 802.11ad, Fixed Wireless Access (FWA), and Virtual Reality (VR) systems. It can be scaled to address applications such as smartphones and other terminals, advanced and centralized access points, small cells, macro cells and cloud RAN (C-RAN).

Audio, Voice and Speech

CEVA develops application specific audio platforms, incorporating the DSP core and various sotware for voice activation, speech recognition, audio processing, and sound-sensing. The company also offers an ecosystem of software modules and development platforms to speed application development and prototyping. Target markets for CEVA’s audio DSP portfolio include mobile voice, voice assistants, wireless audio, smart home, and audio infotainment. CEVA-TeakLite-4 is the fourth-generation DSP architecture based on the TeakLite family of DSP cores. Fully compatible with CEVA-TeakLite, CEVA-Teaklite-II and CEVA-TeakLite-III DSPs, The CEVA-TeakLite-4 is a low-power, 32-bit, variable 10-stage pipeline, fixed-point arithmetic architecture specifically targeted for advanced audio and voice applications, for high definition audio applications requiring standards such as Dolby TrueHD, DTS-HD, SILK and other wideband voice encodings. The CEVA-X2 is an advanced, unified DSP/controller aimed at high-end multi-standard cellular baseband and intensive sound processing applications. It is designed for mobile broadband Physical Layer (PHY) control, intensive multi-microphone speech processing, and cutting-edge audio workloads. The CEVA-X2 is based on a VLIW/SIMD architecture with a 10-stage pipeline operating at 2GHz in typical conditions of a 16nm process. The architecture supports quad 16×16 MAC operations per cycle, dual 32×32 MAC operations per cycle, 64-bit SIMD fixed-point operations, and IEEE single-precision floating-point operations.

Always-on and Sensor Fusion

The company designs especially low-power and small-die-size DSP IP cores for always-on sensing and sensor fusion. Mobile devices, wearables and IoT devices all include multiple MEMS sensors to detect sound, motion, gestures, velocity, temperature, pressure, and other data, depending on the purpose and function of each device. The dedicated sensor fusion DSP is designed to enable nonstop reading of environmental data while other device systems are powered off or on standby, activated only when necessary. These devices are typically very small and battery-powered. For these reasons, stringent power consumption and minimal silicon area are critical to this category of products. The CEVA-TL410 DSP core is based on, and compliant with, the high-performance, low-power CEVA-TeakLite-4 DSP architecture. Primarily intended for ultra-low power, always-on audio, and sensing DSP applications in voice activation, audio CODECs, and low-power audio chips, the CEVA-TL410 DSP core offers the smallest die size with its single 32×32-bit MAC, dual 16×16-bit MAC, and direct memory interface. It provides audio instructions through a dedicated audio instruction set architecture (ISA), and incorporates a second-generation Power Scaling Unit (PSU 2.0) for smart power management.

Connectivity Solutions

he company designs wireless and wired connectivity IPs for embedded designs targeting mobile, wearables, consumer electronic s, industrial, automotive and IoT markets. Among other wired and LPWA technologies, the company licenses solutions for Wi-Fi 802.11a/b/g/n/ac/ax, Classic Bluetooth, Bluetooth low-energy (BLE), and Bluetooth dual-mode (BTDM). The RivieraWaves Wi-Fi IP family is a comprehensive suite of SoC/ASSP-embeddable platforms for Wi-Fi 802.11a/b/g/n/ac. Each RivieraWaves Wi-Fi platform incorporates PHY modem functions and MAC functions, including Lower MAC (LMAC) and Full MAC software stacks that are processor- and operating-system-agnostic to allow deployment on various embedded processors. The RivieraWaves Wi-Fi family consists of the following platforms:

• Wi-Fi Low Power: optimized for small, low cost and low power IoT devices, wearables, medical, low end smartphones and wireless audio, it includes 802.11n 1×1 and 802.11ax 1×1 20MHz configurations.
• Wi-Fi High Performance: addressing a vast array of media-sharing consumer devices, including smartphones, tablets, cameras, and smart-home products, it supports configurations such as 802.11n 2×2, 802.11ac 1×1 & 2×2, 802.11ax 1×1 & 2×2.
• Wi-Fi Multi-Gig: tailored for advanced products dealing with high data traffic including access points, media gateways, and Wi-Fi offload in small cells, it provides 4×4 configurations of 802.11ac and 802.11ax.

The RivieraWaves Bluetooth IP family is a suite of SoC/ASSP- embeddable platforms for Bluetooth low-energy (BLE) and dual-mode (BTDM). The platforms consist of a hardware baseband controller, a PHY (modem + RF), and a software protocol stack. For BLE, this protocol stack encompasses the Link layer up to the GAP/GATT, as well as a comprehensive list of services and profiles. For BTDM, this protocol stack presents an industry-standard HCI interface. A flexible radio interface enables the platform to be deployed with either RivieraWaves RF or other RF IPs, enabling selection of both foundry and process node. The software stack is portable to many embedded processors, including CEVA-TeakLite-4, CEVA-X1, ARM® Cortex-M™ series, ARC®EM family, RISC-V, Cortus APS family, AndesCore™ family, and others. CEVA’s connectivity solution suite for storage systems is made up of both SATA (AHCI-Host and Device-side) and SAS (Initiator and Target-side) IPs, all developed via extensive experience with multiple licensees and in volume production. They are provided as RTL IP packages, consisting of Link and Transport layers, as defined by the relevant specification. The packages are coupled with a very flexible PHY Control layer for connecting with various third-party PHY/SerDes IPs. At the system chip interface, the IPs present a high-performance DMA engine on the data path, as well as a hardware-accelerated Command layer.

See also

• Texas Instruments TMS320
• Qualcomm Hexagon