Company:Chronologic Simulation

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Short description: Electronic Design Automation simulation developing company
Chronologic Simulation
TypePrivate
HeadquartersLos Altos, California, United States
Key people
  • John Sanguinetti, CEO and founder
  • Peter Eichenberger, CTO and founder
  • Michael McNamara, VP Engineering
  • Simon Davidmann, VP Europe


History

In the late 1980s and early 1990s integrated circuits were being designed and verified in Verilog HDL simulators.[1] These simulators were focused on gate level speed and were implemented as language interpreters. Verilog HDL[2] was proprietary and owned by Cadence Design Systems after their acquisition in1989 of Gateway Design Automation, the developers of Verilog.

There was competition to Verilog from the US DoD VHDL language that became an IEEE standard and in 1991 Cadence made the proprietary Verilog HDL public and created Open Verilog International (OVI) (later renamed Accellera) to standardize it.[3][4]

The founders of Chronologic[5] saw the opening up of Verilog as an opportunity to adopt software compiler techniques and create a fast compiled code Verilog simulator.[6]

Founding team

  • John Sanguinetti, CEO and founder[7][8]
  • Peter Eichenberger, CTO and founder[8]
  • Michael McNamara, VP Engineering[8]
  • Martin Harding, VP Sales[9][2]
  • Simon Davidmann, VP Europe[9][2]

Development

The development of the Verilog Compiled Simulator (VCS) started in 1991 with early development by Sanguinetti,[7][8] Eichenberger,[8] and McNamara[8] and by 1993 the first version was released, Harding and Davidmann started up the sales channel,[2][9] and VCS was in use with commercial users and in education and research.[10][11][12][13] VCS initially parsed the Verilog source and using software compiler techniques created C code which is then subsequently compiled into executable binaries to run on the native host computer.[14] The performance of existing Verilog simulators was excellent at the gate level but lacked needed speed at the RTL level.[10] Chronologic's VCS focused on RTL speed and by using cycle based and complier optimization techniques was often reported as being 10-40 times faster than other commercial products.[15][16][17]

Acquisition

Chronologic Simulation was acquired in 1994 for $26.5 million by Viewlogic Systems, Inc. though there were complications that resulted in lawsuits that were ultimately resolved in 1995.[18][19][20] In 1997 Synopsys, Inc., acquired Viewlogic for $497 million.[21][22]

Status

VCS is still widely used and has been kept up to date with the evolution in the Verilog language, including features from Superlog that became part of SystemVerilog around 2005.[2] VCS is still a part of Synopsys verification solutions.[23][24]

References

  1. ↑ "A brief history of logic simulation" (in en-US). https://semiengineering.com/knowledge_centers/eda-design/verification/logic-simulation/a-brief-history-of-logic-simulation/. 
  2. ↑ 2.0 2.1 2.2 2.3 2.4 Flake, Peter; Moorby, Phil; Golson, Steve; Salz, Arturo; Davidmann, Simon (2020-06-12). "Verilog HDL and its ancestors and descendants". Proc. ACM Program. Lang. 4 (HOPL): 87:1–87:90. doi:10.1145/3386337. 
  3. ↑ "Open Verilog International" (in en-US). https://semiengineering.com/entities/open-verilog-international/. 
  4. ↑ Raval, Vrit (2019-08-24). "BRIEF HISTORY OF VERILOG !" (in en). https://medium.com/verilog-novice-to-wizard/brief-history-of-verilog-eb836b823d15. 
  5. ↑ "Chronologic Simulation" (in en-US). https://semiengineering.com/entities/chronologic-simulation/. 
  6. ↑ Sanguinetti, John (1993-09-11). "Simulation speed and logic design". https://www.computerhistory.org/collections/catalog/102624716. 
  7. ↑ 7.0 7.1 "John Sanguinetti - A Profile". http://www.aycinena.com/index2/index3/archive/john%20sanguinetti.html. 
  8. ↑ 8.0 8.1 8.2 8.3 8.4 8.5 Sanguinetti, John (2009-02-28). "Oral History of John Sanguinetti". https://archive.computerhistory.org/resources/access/text/2015/06/102702042-05-01-acc.pdf. 
  9. ↑ 9.0 9.1 9.2 Sutherland, Stuart; Davidmann, Simon; Flake, Peter (2006). SystemVerilog for Design. doi:10.1007/0-387-36495-1. ISBN 978-0-387-33399-1. [page needed]
  10. ↑ 10.0 10.1 French, Robert S.; Lam, Monica S.; Levitt, Jeremy R.; Olukotun, Kunle (1995). "A general method for compiling event-driven simulations". Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95. pp. 151–156. doi:10.1145/217474.217522. ISBN 0-89791-725-1. 
  11. ↑ Palnitkar, Samir (1995-03-27). "Cycle simulation techniques". http://archive.sigda.org/programs/cadathlon/refs/p5-verification.pdf. 
  12. ↑ Tsu-Hua Wang; Chong Guan Tan (1995). "Practical code coverage for Verilog". Proceedings. 1995 IEEE International Verilog HDL Conference. pp. 99–104. doi:10.1109/IVC.1995.512503. ISBN 0-8186-7082-7. 
  13. ↑ "Using VCS". https://www.cs.utexas.edu/~fussell/courses/cs352h/handouts/verilog/vcs_tut.html. 
  14. ↑ Murphy, Sean (2009-05-20). "Interview with John Sanguinetti" (in en-US). https://www.skmurphy.com/blog/2009/05/19/interview-with-john-sanguinetti/. 
  15. ↑ Wharton, David (1994-06-01). "Benchmarks Test a Few Simulators". Electronic Engineering Times (EE Times): pp. 50–52, 92. 
  16. ↑ Coumeri, S.L.; Thomas, D.E. (1994). "Benchmark descriptions for comparing the performance of Verilog and VHDL simulators". International Verilog HDL Conference. pp. 37–42. doi:10.1109/IVC.1994.323750. ISBN 0-8186-5655-7. 
  17. ↑ EETimes (1996-10-07). "Chronologic VCS 3.1 Increases Accurate Gate-Level Performance". https://www.eetimes.com/chronologic-vcs-3-1-increases-accurate-gate-level-performance/. 
  18. ↑ "Chronologic Simulation, Inc. v. Sanguinetti, 892 F. Supp. 318 (D. Mass. 1995)" (in en). https://law.justia.com/cases/federal/district-courts/FSupp/892/318/2295715/. 
  19. ↑ "Viewlogic Systems, Inc." (in en-US). https://semiengineering.com/entities/viewlogic-systems-inc/. 
  20. ↑ "Viewlogic settles with Chronologic". Electronic Engineering Times: p. 2. 10 June 1996. ProQuest 208126322. 
  21. ↑ Writer, CBR Staff (1997-10-16). "SYNOPSYS ACQUIRES VIEWLOGIC FOR $500M" (in en-US). https://www.techmonitor.ai/technology/synopsys_acquires_viewlogic_for_500m. 
  22. ↑ EETimes (1997-12-08). "Shareholders Approve Synopsys/Viewlogic Merger". https://www.eetimes.com/shareholders-approve-synopsys-viewlogic-merger/. 
  23. ↑ "VCS Datasheet". 2024-03-01. https://www.synopsys.com/content/dam/synopsys/gated-assets/verification/vcs-ds.pdf. 
  24. ↑ "VCS: Functional Verification Solution | Synopsys" (in en). https://www.synopsys.com/verification/simulation/vcs.html. 



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