Engineering:Front end of line

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Short description: Part of manufacturing process used to create integrated circuits
Illustration of FEOL (device generation in the silicon, bottom) and BEOL (depositing metalization layers, middle part) to connect the devices.
CMOS fabrication process

The front end of line (FEOL) is the first portion of IC fabrication where the individual components (transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate.[1] FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers.[2]

Steps

For the CMOS process, FEOL contains all fabrication steps needed to form isolated CMOS elements:[3][4]

  1. Selecting the type of wafer to be used; Chemical-mechanical planarization (CMP) and cleaning of the wafer.
  2. Shallow trench isolation (STI) (or LOCOS in early processes with feature size > 0.25 μm);
  3. Well formation;
  4. Gate module formation;
  5. Source and drain module formation.

Finally, the surface is treated to prepare the contacts for the subsequent metallization. This concludes the FEOL process, that is, all devices have been built.[4]

Following these steps, the devices must be connected electrically as per the nets to build the electrical circuit. This is done in the back end of line (BEOL). BEOL is thus the second portion of IC fabrication where the individual devices are connected.[4]

See also

References

  1. ↑ Karen A. Reinhardt and Werner Kern (2008). Handbook of Silicon Wafer Cleaning Technology (2nd ed.). William Andrew. p. 202. ISBN 978-0-8155-1554-8. https://books.google.com/books?id=UPaD8JUCKr0C&pg=PA202. 
  2. ↑ "FEOL (Front End of Line: substrate process, the first half of wafer processing) 1. Isolation | USJC：United Semiconductor Japan Co., Ltd." (in ja). 2019-02-22. https://www.usjpc.com/en/tech-intro-e/process-e/element-e. 
  3. ↑ Ramsundar, Bharath (26 February 2021). "A Deep Dive into Chip Manufacturing: Front End of Line (FEOL) Basics" (in en). https://deepforest.substack.com/p/a-deep-dive-into-chip-manufacturing. 
  4. ↑ 4.0 4.1 4.2 J. Lienig, J. Scheible (2020). "Chap. 2.9.3: FEOL: Creating Devices". Fundamentals of Layout Design for Electronic Circuits. Springer. pp. 78–82. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. https://link.springer.com/book/10.1007/978-3-030-39284-0. 

Further reading

  • "CMOS: Circuit Design, Layout, and Simulation" Wiley-IEEE, 2010. ISBN 978-0-470-88132-3. pages 177-178 (Chapter 7.2 CMOS Process Integration); pages 180-199 (7.2.1 Frontend-of-the-line integration)
  • "Fundamentals of Layout Design for Electronic Circuits", by Lienig, Scheible, Springer, doi:10.1007/978-3-030-39284-0ISBN 978-3-030-39284-0, 2020. Chapter 2: Technology Know-How: From Silicon to Devices, pages 78-82 (2.9.3 FEOL: Creating Devices)



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