Engineering:Front end of line
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Short description: Part of manufacturing process used to create integrated circuits
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BEOL (metalization layer) and FEOL (devices).
The front-end-of-line (FEOL) is the first portion of IC fabrication where the individual components (transistors, capacitors, resistors, etc.) are patterned in the semiconductor.[1] FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers.[2]
For the CMOS process, FEOL contains all fabrication steps needed to form isolated CMOS elements:[3]
- Selecting the type of wafer to be used; Chemical-mechanical planarization and cleaning of the wafer.
- Shallow trench isolation (STI) (or LOCOS in early processes, with feature size > 0.25 μm)
- Well formation
- Gate module formation
- Source and drain module formation
See also
References
- ↑ Karen A. Reinhardt and Werner Kern (2008). Handbook of Silicon Wafer Cleaning Technology (2nd ed.). William Andrew. p. 202. ISBN 978-0-8155-1554-8. https://books.google.com/books?id=UPaD8JUCKr0C&pg=PA202.
- ↑ "FEOL (Front End of Line: substrate process, the first half of wafer processing) 1. Isolation | USJC：United Semiconductor Japan Co., Ltd." (in ja). 2019-02-22. https://www.usjpc.com/en/tech-intro-e/process-e/element-e.
- ↑ Ramsundar, Bharath. "A Deep Dive into Chip Manufacturing: Front End of Line (FEOL) Basics" (in en). https://deepforest.substack.com/p/a-deep-dive-into-chip-manufacturing.
Further reading
- "CMOS: Circuit Design, Layout, and Simulation" Wiley-IEEE, 2010. ISBN:978-0-470-88132-3. pages 177-178 (Chapter 7.2 CMOS Process Integration); pages 180-199 (7.2.1 Frontend-of-the-line integration)
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