Engineering:Logarithmic resistor ladder

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A logarithmic resistor ladder is an electronic circuit, composed of a series of resistors and switches, designed to create an attenuation from an input to an output signal, where the logarithm of the attenuation ratio is proportional to a binary number that represents the state of the switches. The logarithmic behavior of the circuit is its main differentiator in comparison with digital-to-analog converters (DACs) in general, and traditional R-2R Ladder networks specifically. Logarithmic attenuation is desired in situations where a large dynamic range needs to be handled. The circuit described in this article is applied in audio devices, since human perception of sound level is properly expressed on a logarithmic scale.

Logarithmic input/output behavior

As in digital-to-analog converters, a binary number is applied to the ladder network, whose N bits are treated as representing an integer value:

[math]\displaystyle{ \mathrm{CodeValue} = \sum_{i=1}^N s_i \cdot 2^{i-1} }[/math]

where [math]\displaystyle{ s_i }[/math] is 0 or 1 depending on the state of the ith switch.

For comparison, recall a conventional linear DAC or R-2R network produces an output voltage signal of:

[math]\displaystyle{ V_{out} = V_{in} \cdot c \cdot (\mathrm{CodeValue} + d ) }[/math]

where [math]\displaystyle{ c }[/math] and [math]\displaystyle{ d }[/math] are design constants and where [math]\displaystyle{ V_{in} }[/math] typically is a constant reference voltage (or is a variable input voltage for a multiplying DAC.[1])

In contrast, the logarithmic ladder network discussed in this article creates a behavior as:

[math]\displaystyle{ \log (V_{out} / V_{in}) = c \cdot \mathrm{CodeValue} }[/math]

which can also be expressed as [math]\displaystyle{ V_{in} }[/math] multiplied by some base [math]\displaystyle{ \alpha }[/math] raised to the power of the code value:

[math]\displaystyle{ V_{out} = V_{in} \cdot \alpha ^ \mathrm{CodeValue} }[/math]

where [math]\displaystyle{ c = \log(\alpha) \, . }[/math]

Circuit implementation

Schematic diagram

This example circuit is composed of 4 stages, numbered 1 to 4, and includes a source resistance Rsource and load resistance Rload.

Each stage i has a designed input-to-output voltage attenuation Ratioi as:

[math]\displaystyle{ Ratio_i = \text{if}\; sw_i \;\text{then}\; \alpha^{2^{i-1}} \;\text{else}\; 1 }[/math]

For logarithmic scaled attenuators, it is common practice to equivalently express their attenuation in decibels:

[math]\displaystyle{ dB(Ratio_i) = 20 \log_{10} \alpha^{2^{i-1}} = 2^{i-1} \cdot 20 \cdot \log_{10} \alpha }[/math] for [math]\displaystyle{ i = 1 .. N }[/math] and [math]\displaystyle{ sw_i = 1 }[/math]

This reveals a basic property: [math]\displaystyle{ dB(Ratio_{i+1}) = 2 \cdot dB(Ratio_i) }[/math]

To show that this [math]\displaystyle{ Ratio_i }[/math] satisfies the overall intention:

[math]\displaystyle{ \log (V_{out}/V_{in}) = \log (\prod_{i=1}^N Ratio_i) = \sum_{i=1}^N \log (Ratio_i) = \log (\alpha) \cdot CodeValue = c \cdot CodeValue }[/math]

The different stages 1 .. N should function independently of each other, as to obtain 2N different states with a composable behavior. To achieve an attenuation of each stage that is independent of its surrounding stages, either one of two design choices is to be implemented: constant input resistance or constant output resistance. Because the stages operate independently, they can be inserted in the chain in any order.

Constant input resistance

The input resistance of any stage shall be independent of its on/off switch position, and must be equal to Rload.

This leads to:

[math]\displaystyle{ \begin{cases} R_{i,parr} = (R_{i,b} \cdot R_{load}) / (R_{i,b} + R_{load}) \\ R_{i,a} + R_{i,parr} = R_{load} \\ R_{i,parr} / (R_{i,a} + R_{i,parr}) = Ratio_i \end{cases} }[/math]

With these equations, all resistor values of the circuit diagram follow easily after choosing values for N, [math]\displaystyle{ \alpha }[/math] and Rload. (The value of Rsource does not influence the logarithmic behavior)

Constant output resistance

The output resistance of any stage shall be independent of its on/off switch position, and must be equal to Rsource.

This leads to:

[math]\displaystyle{ \begin{cases} R_{i,ser} = R_{i,a} + R_{source} \\ R_{i,ser} \cdot R_{i,b} / (R_{i,ser} + R_{i,b}) = R_{source} \\ R_{i,b} / (R_{i,ser} + R_{i,b}) = Ratio_i \end{cases} }[/math]

Again, all resistor values of the circuit diagram follow easily after choosing values for N, [math]\displaystyle{ \alpha }[/math] and Rsource. (The value of Rload does not influence the logarithmic behavior).

For example, with a Rload of 1 kΩ, and 1 dB attenuation, the resistor values would be: Ra = 108.7 Ω, Rb = 8195.5 Ω.

The next step (2 dB) would use: Ra = 369.0 Ω, Rb = 1709.7 Ω.

Circuit variations

  • The circuit as depicted above, can also be applied in reverse direction. That correspondingly reverses the role of constant-input and constant-output resistance equations.
  • Since the stages do not significantly influence each other's attenuation, the stage order can be chosen arbitrarily. Such reordering can have a significant effect on the input resistance of the constant output resistance attenuator and vice versa.


R-2R ladder networks used for linear digital-to-analog conversion are old (Resistor ladder § History mentions a 1953 article and a 1955 patent).

Multiplying DACs with logarithmic behavior were not known for a long time after that. An initial approach was to map the logarithmic code to a much longer code word, which could be applied to the classical (linear) R-2R based DAC. Lengthening the codeword is needed in that approach to achieve sufficient dynamic range. This approach was implemented in a device from Analog Devices Inc.,[2] protected through a 1981 patent filing.[3]

See also


  1. "Multiplying DACs, flexible building blocks". Analog Devices inc.. 2010. Retrieved 29 March 2012. 
  2. "LOGDAC CMOS Logarithmic D/A Converter AD7118". Analog Devices Inc.. 
  3. Burton, David P., "Signal-controllable attenuator employing a digital-to-analog converter", US patent 4521764, issued 4 June 1985

External links