Memory rank
A memory rank is a set of DRAM chips connected to the same chip select, which are therefore accessed simultaneously. In practice all DRAM chips share all of the other command and control signals, and only the chip select pins for each rank are separate (the data pins are shared across ranks).[1]
The rank and per-chip bus width of a memory module is written in a concise string. For example, 2R×4 means that the module has two ranks of four-bit-wide chips.
Details
The term rank was created and defined by JEDEC, the memory industry standards group. On a DDR, DDR2, or DDR3 memory module, each rank has a 64-bit-wide data bus (72 bits wide on DIMMs that support ECC). The number of physical DRAMs depends on their individual widths. For example, a rank of ×8 (8-bit wide) DRAMs would consist of eight physical chips (nine if ECC is supported), but a rank of ×4 (4-bit wide) DRAMs would consist of 16 physical chips (18, if ECC is supported). Multiple ranks can coexist on a single DIMM. Modern DIMMs can feature 1, 2, 4, or 8 ranks (single-, dual-, quad-, and octa- rank).[2]
Predating the term rank (sometimes also called row) is the use of single-sided and double-sided modules, especially with SIMMs. While most often the number of sides used to carry RAM chips corresponded to the number of ranks, sometimes they did not. This could lead to confusion and technical issues.[3][4]
Multi-Ranked Buffered DIMM
A Multi-Ranked (also Multiplexed Rank according to JEDEC) Buffered DIMM (MR-DIMM) allows both ranks to be accessed simultaneously by the memory controller, and is supported by AMD, Google, Microsoft, JEDEC, and Intel.[5]
Performance of multiple rank modules
There are several effects to consider regarding memory performance in multi-rank configurations:
- Multi-rank modules allow several open DRAM pages (row) in each rank (typically eight pages per rank). This increases the possibility of getting a hit on an already open row address. The performance gain that can be achieved is highly dependent on the application and the memory controller's ability to take advantage of open pages.[6]
- Multi-rank modules have higher loading on the data bus (and on unbuffered DIMMs the CA bus as well). Therefore if more than dual rank DIMMs are connected in one channel, the speed might be reduced.[7]
- There is a small performance reduction for multi-rank systems as they require some pipeline stalls between accessing different ranks. For two ranks on a single DIMM it might not even be required, but this parameter is often programmed independently of the rank location in the system (if on the same DIMM or different DIMMs). Nevertheless, this pipeline stall is negligible compared to the aforementioned effects.[8]
See also
References
- ↑ "Definition of Rank". http://h17007.www1.hpe.com/docs/iss/DL380pGen8/setup_install/advanced/Content/138678.htm. Retrieved 2017-09-25.
- ↑ "DRAM Memory Module Rank Calculation, Whitepaper AN0033". 2020-05-26. pp. 4-5. https://www.vikingtechnology.com/wp-content/uploads/2021/03/AN033_Module_Rank_Whitepaper.pdf.
- ↑ "An Overview of Memory". 2008-05-06. http://www.professormesser.com/free-a-plus-training/a-plus-videos/an-overview-of-memory/. Retrieved 2017-08-09.
- ↑ "Computer Memory Issues". https://de.ifixit.com/Wiki/Computer_Memory_Issues. Retrieved 2017-08-09.
- ↑ "Next-Generation CAMM, MR-DIMM Memory Modules Show up at Computex". https://www.anandtech.com/show/18893/next-generation-camm-mr-dimm-modules-at-computex.
- ↑ "DDR4 memory organization and how it affects memory bandwidth" (in en-us). 2023-04-19. https://blog.cloudflare.com/ddr4-memory-organization-and-how-it-affects-memory-bandwidth/.
- ↑ "Memory Rank Explained: Single Rank vs Dual Rank (1R vs 2R)" (in en). https://www.atpinc.com/blog/dram-memory-rank-explained.
- ↑ "DDR4 memory organization and how it affects memory bandwidth" (in en-us). 2023-04-19. https://blog.cloudflare.com/ddr4-memory-organization-and-how-it-affects-memory-bandwidth/.
Bibliography
- Balasubramonian, Rajeev (May 2022). Innovations in the Memory System. Springer. ISBN 9783031017636.
- Bruce, Jacob; Wang, David; Ng, Spencer (2008). Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann Publishers. ISBN 978-0-12-379751-3.
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