Software:Preesm
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 PREESM 0.5.0 screenshot | |
| Developer(s) | PREESM Development Team at IETR |
|---|---|
| Initial release | 2008 |
| Written in | Java as Eclipse plug-ins |
| Type | Rapid Prototyping Tool |
| License | CeCILL-B or CeCILL-C depending on the plug-ins |
| Website | preesm.org |
PREESM (the Parallel and Real-time Embedded Executives Scheduling Method) is an open-source rapid prototyping and code generation tool. It is primarily employed to simulate signal processing applications and generate code for multi-core Digital Signal Processors. PREESM is developed at the Institute of Electronics and Telecommunications-Rennes (IETR) in collaboration with Texas Instruments France in Nice.
The PREESM tool inputs are an algorithm graph, an architecture graph, and a scenario which is a set of parameters and constraints that specify the conditions under which the deployment will run. The chosen type of algorithm graph is a hierarchical extension of Synchronous Dataflow (SDF) graphs named Interface-Based hierarchical Synchronous Dataflow (IBSDF). The architecture graph is named System-Level Architecture Model (S-LAM). From these inputs, PREESM maps and schedules automatically the code over the multiple processing elements and generates multi-core code.
Documentation
Online documentation is provided in the PREESM Website.
Publications
- Desnos, Karol; Pelcat, Maxime; Nezan, Jean-François; Aridhi, Slaheddine (2012). "Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph". 2012 International Conference on Embedded Computer Systems (SAMOS). pp. 160–167. doi:10.1109/SAMOS.2012.6404170. ISBN 978-1-4673-2297-3. http://hal.archives-ouvertes.fr/docs/00/72/13/35/PDF/Samos12.pdf.
- Pelcat, Maxime; Nezan, Jean-François; Piat, Jonathan; Aridhi, Slaheddine (2012). Springer. ed. Physical Layer Multicore Prototyping: A Dataflow-Based Approach for LTE eNodeB. https://www.springer.com/engineering/signals/book/978-1-4471-4209-6.
- Piat, Jonathan (2010). "Data flow modelling and optimization of loops for multi-core architectures". PhD Thesis, INSA de Rennes. http://tel.archives-ouvertes.fr/docs/00/56/45/22/PDF/full_thesis_jpiat.pdf.
- Pelcat, Maxime (2010). "Rapid Prototyping and Dataflow-Based Code Generation for the 3GPP LTE eNodeB Physical Layer mapped onto Multi-Core DSPs". PhD Thesis, INSA de Rennes. http://tel.archives-ouvertes.fr/docs/00/57/80/43/PDF/thesis_mpelcat_final_pdf.pdf.
- {{cite journal
|first1 = Maxime |last1 = Pelcat |first2 = Jonathan |last2 = Piat |first3 = Matthieu |last3 = Wipliez |first4 = Slaheddine |last4 = Aridhi |first5 = Jean-François |last5 = Nezan |year = 2009 |title = An Open Framework for Rapid Prototyping of Signal Processing Applications |journal = EURASIP Journal on Embedded Systems |volume = 2009 |pages = 1–13 |doi = 10.1155/2009/598529 |doi-access = free |url= https://hal.archives-ouvertes.fr/hal-00429312/file/ES598529_finalVersion.pdf
- Piat, Jonathan; Bhattacharyya, Shuvra S.; Pelcat, Maxime; Raulet, Mickaël (2009). "Multi-Core Code Generation From Interface Based Hierarchy". DASIP Sophia Antipolis. http://hal.archives-ouvertes.fr/docs/00/44/04/79/PDF/piat_dasip.pdf.
- Pelcat, Maxime; Nezan, Jean-François; Piat, Jonathan; Croizer, Jérôme; Aridhi, Slaheddine (2009). "A System-Level Architecture Model for Rapid Prototyping of Heterogeneous Multicore Embedded Systems". DASIP Sophia Antipolis. http://hal.archives-ouvertes.fr/docs/00/42/93/97/PDF/2009_DASIP_Maxime_Pelcat.pdf.
- Piat, Jonathan; Bhattacharyya, Shuvra S.; Raulet, Mickaël (2009). "Interface-based hierarchy for synchronous data-flow graphs". SiPS Tampere. http://hal.archives-ouvertes.fr/docs/00/44/04/78/PDF/sips2009.pdf.
- Pelcat, Maxime; Menuet, Pierrick; Aridhi, Slaheddine; Nezan, Jean-François (2009). "Scalable compile-time scheduler for multi-core architectures". DATE Nice. Archived from the original on 2011-07-08. https://web.archive.org/web/20110708233935/http://www.date-conference.com/proceedings/PAPERS/2009/DATE09/PDFFILES/IP5_02.PDF.
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