Trace scheduling

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Short description: Optimization technique in computing

Trace scheduling is an optimization technique developed by Josh Fisher used in compilers for computer programs.[1]

A compiler often can, by rearranging its generated machine instructions for faster execution, improve program performance. It increases ILP (Instruction Level Parallelism) along the important execution path by statically predicting frequent execution path. Trace scheduling is one of many known techniques for doing so.[2]

A trace is a sequence of instructions, including branches but not including loops, that is executed for some input data. Trace scheduling uses a basic block scheduling method to schedule the instructions in each entire trace, beginning with the trace with the highest frequency. It then adds compensation code at the entry and exit of each trace to compensate for any effects that out-of-order execution may have had.

This can result in large increases in code sizes and poor or erratic performance if program's behavior varies significantly with the input.

Trace scheduling was originally developed for Very Long Instruction Word, or VLIW machines, and is a form of global code motion. It works by converting a loop to long straight-line code sequence using loop unrolling and static branch prediction. This process separates out "unlikely" code and adds handlers for exits from trace. The goal is to have the most common case executed as a sequential set of instructions without branches.

See also

References

  1. Steven Muchnick; Muchnick and Associates (15 August 1997). Advanced Compiler Design Implementation. Morgan Kaufmann. ISBN 978-1-55860-320-2. https://archive.org/details/advancedcompiler00much. "Trace scheduling ." 
  2. Fisher, Joseph (7 July 1981). "Trace Scheduling: A Technique for Global Microcode Compaction". IEEE Transactions on Computers c-30 (7): 478–490. doi:10.1109/TC.1981.1675827. http://people.eecs.berkeley.edu/~kubitron/courses/cs252-S12/handouts/papers/TraceScheduling.pdf. 
  • "Trace Scheduling: A Technique for Global Microcode Compaction". IEEE Transactions on Computers 30 (7): 478–490. 1981. doi:10.1109/TC.1981.1675827.