View source for Engineering:5 nm process

{{short description|Semiconductor manufacturing processes at the 5 nm FinFET technology node}}
In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the '''5&nbsp;nm process''' as the [[Engineering:MOSFET|MOSFET]] technology node following the 7 nm node. In 2020, [[Company:Samsung Electronics|Samsung]] and [[Company:TSMC|TSMC]] entered volume production of 5&nbsp;nm chips, manufactured for companies including [[Company:Apple Inc.|Apple]], [[Company:Marvell Technology Group|Marvell]], [[Company:Huawei|Huawei]] and [[Company:Qualcomm|Qualcomm]].<ref>{{Cite web|last=Cutress|first=Dr Ian|title='Better Yield on 5nm than 7nm': TSMC Update on Defect Rates for N5|url=https://www.anandtech.com/show/16028/better-yield-on-5nm-than-7nm-tsmc-update-on-defect-rates-for-n5|access-date=28 August 2020|website=[[AnandTech]]|archive-date=30 August 2020|archive-url=https://web.archive.org/web/20200830112510/https://www.anandtech.com/show/16028/better-yield-on-5nm-than-7nm-tsmc-update-on-defect-rates-for-n5|url-status=live}}</ref><ref>{{cite web|title=Marvell and TSMC Collaborate to Deliver Data Infrastructure Portfolio on 5nm Technology|url=https://www.hpcwire.com/off-the-wire/marvell-and-tsmc-collaborate-to-deliver-data-infrastructure-portfolio-on-5nm-technology/|access-date=28 August 2020|website=HPCwire|archive-date=15 September 2020|archive-url=https://web.archive.org/web/20200915082115/https://www.hpcwire.com/off-the-wire/marvell-and-tsmc-collaborate-to-deliver-data-infrastructure-portfolio-on-5nm-technology/|url-status=live}}</ref>

The term "5 nm" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors being 5 nanometers in size. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a "5 nm node is expected to have a contacted gate pitch of 51 nanometers and a tightest metal pitch of 30 nanometers".<ref>{{citation |url=https://irds.ieee.org/editions/2021/more-moore |title=International Roadmap for Devices and Systems: 2021 Update: More Moore |year=2021 |publisher=IEEE |page=7 |access-date=7 August 2022 | url-status=live | archive-date=7 August 2022 |archive-url=https://web.archive.org/web/20220807181530/https://irds.ieee.org/editions/2021/more-moore }}</ref> However, in real world commercial practice, "5 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization),  increased speed and reduced power consumption compared to the previous 7 nm process.<ref>{{Cite web |url=https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-numbers |title=TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is" |date=10 September 2019 |access-date=20 April 2020 |archive-date=17 June 2020 |archive-url=https://web.archive.org/web/20200617230408/https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-numbers |url-status=live }}</ref><ref>{{Cite journal |url=https://spectrum.ieee.org/semiconductors/devices/a-better-way-to-measure-progress-in-semiconductors |author=Samuel K. Moore |title=A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric |publisher=IEEE |journal=IEEE Spectrum |date=21 July 2020 |access-date=20 April 2021 |archive-date=2 December 2020 |archive-url=https://web.archive.org/web/20201202002819/https://spectrum.ieee.org/semiconductors/devices/a-better-way-to-measure-progress-in-semiconductors |url-status=live }}</ref>

==History==
===Background===
[[Physics:Quantum tunnelling|Quantum tunnelling]] effects through the gate oxide layer on 7&nbsp;nm and 5&nbsp;nm [[Engineering:Transistor|transistor]]s became increasingly difficult to manage using existing semiconductor processes.<ref>{{cite news|url=https://semiengineering.com/quantum-effects-at-7-5nm/|title=Quantum Effects At 7/5nm And Beyond|work=Semiconductor Engineering|access-date=15 July 2018|archive-date=15 July 2018|archive-url=https://web.archive.org/web/20180715211218/https://semiengineering.com/quantum-effects-at-7-5nm/|url-status=live}}</ref> Single-transistor devices below 7&nbsp;nm were first demonstrated by researchers in the early 2000s. In 2002, an [[Company:IBM|IBM]] research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.<ref>{{cite web|url=http://www.theinquirer.net/inquirer/news/1034321/ibm-claims-worlds-smallest-silicon-transistor|archive-url=https://web.archive.org/web/20110531040504/http://www.theinquirer.net/inquirer/news/1034321/ibm-claims-worlds-smallest-silicon-transistor|url-status=dead|archive-date=31 May 2011|title=IBM claims world's smallest silicon transistor - TheINQUIRER|website=Theinquirer.net|access-date=7 December 2017|date=9 December 2002}}</ref><ref>{{cite conference |last1=Doris |first1=Bruce B. |last2=Dokumaci |first2=Omer H. |last3=Ieong |first3=Meikei K. |last4=Mocuta |first4=Anda |last5=Zhang |first5=Ying |last6=Kanarsky |first6=Thomas S. |last7=Roy |first7=R. A. |title=Extreme scaling with ultra-thin Si channel MOSFETs |conference=Digest. International Electron Devices Meeting |date=December 2002 |pages=267–270 |doi=10.1109/IEDM.2002.1175829|isbn=0-7803-7462-2 |s2cid=10151651 }}</ref>

In 2003, a Japanese research team at [[Company:NEC|NEC]], led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5&nbsp;nm MOSFET.<ref>{{cite web|url=http://www.thefreelibrary.com/NEC+test-produces+world%27s+smallest+transistor.-a0111295563|title=NEC test-produces world's smallest transistor|website=Thefreelibrary.com|access-date=7 December 2017|archive-date=15 April 2017|archive-url=https://web.archive.org/web/20170415012122/https://www.thefreelibrary.com/NEC+test-produces+world%27s+smallest+transistor.-a0111295563|url-status=live}}</ref><ref>{{cite conference |last1=Wakabayashi |first1=Hitoshi |last2=Yamagami |first2=Shigeharu |last3=Ikezawa |first3=Nobuyuki |last4=Ogura |first4=Atsushi |last5=Narihiro |first5=Mitsuru |last6=Arai |first6=K. |last7=Ochiai |first7=Y. |last8=Takeuchi |first8=K. |last9=Yamamoto |first9=T. |last10=Mogami |first10=T. |title=Sub-10-nm planar-bulk-CMOS devices using lateral junction control |conference=IEEE International Electron Devices Meeting 2003 |date=December 2003 |pages=20.7.1–20.7.3 |doi=10.1109/IEDM.2003.1269446|isbn=0-7803-7872-5 |s2cid=2100267 }}</ref>

In 2015, [[Company:IMEC|IMEC]] and Cadence had fabricated 5&nbsp;nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of [[Engineering:Interconnects (integrated circuits)|interconnect]] layers.<ref>{{cite web |url=https://semiwiki.com/eda/cadence/5080-imec-and-cadence-disclose-5nm-test-chip/ |title=IMEC and Cadence Disclose 5nm Test Chip |website=Semiwiki.com |date=4 July 2023 |access-date=4 July 2023}}</ref><ref>{{cite web |url=http://www.semi.org/en/node/55926 |title=The Roadmap to 5nm: Convergence of Many Solutions Needed |website=Semi.org |access-date=25 November 2015 |archive-url=https://web.archive.org/web/20151126115543/http://www.semi.org/en/node/55926 |archive-date=26 November 2015 |url-status=dead  }}</ref>

In 2015, [[Company:Intel|Intel]] described a lateral nanowire (or gate-all-around) FET concept for the 5&nbsp;nm node.<ref name="semiengineering_2016Jan">{{cite web |url=http://semiengineering.com/5nm-fab-challenges/ |title=5nm Fab Challenges |author=Mark LaPedus |quote=Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS). |date=20 January 2016 |access-date=22 January 2016 |archive-date=27 January 2016 |archive-url=https://web.archive.org/web/20160127230827/http://semiengineering.com/5nm-fab-challenges/ |url-status=live }}</ref>

In 2017, [[Company:IBM|IBM]] revealed that it had created 5&nbsp;nm [[Chemistry:Silicon|silicon]] chips,<ref>{{cite web|last1=Sebastian|first1=Anthony|title=IBM unveils world's first 5nm chip|url=https://arstechnica.com/gadgets/2017/06/ibm-5nm-chip/|website=Ars Technica|date=5 June 2017|access-date=5 June 2017|archive-date=5 June 2017|archive-url=https://web.archive.org/web/20170605202822/https://arstechnica.com/gadgets/2017/06/ibm-5nm-chip/|url-status=live}}</ref> using silicon nanosheets in a ''gate-all-around'' configuration (GAAFET), a break from the usual [[Engineering:FinFET|FinFET]] design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50&nbsp;mm<sup>2</sup> and had 600 million transistors per mm<sup>2</sup>, for a total of 30 billion transistors (1667&nbsp;nm<sup>2</sup> per transistor or 41&nbsp;nm transistor spacing).<ref>{{Cite web|last=Huiming|first=Bu|date=5 June 2017|title=5 nanometer transistors inching their way into chips|website=[[Company:IBM|IBM]]|url=https://www.ibm.com/blogs/think/2017/06/5-nanometer-transistors/|access-date=9 June 2021|archive-date=9 June 2021|archive-url=https://web.archive.org/web/20210609002051/https://www.ibm.com/blogs/think/2017/06/5-nanometer-transistors/|url-status=live}}</ref><ref>{{cite web|url=http://uk.pcmag.com/news/89652/ibm-figures-out-how-to-make-5nm-chips|title=IBM Figures Out How to Make 5nm Chips|date=5 June 2017|website=Uk.pcmag.com|access-date=7 December 2017|archive-date=3 December 2017|archive-url=https://web.archive.org/web/20171203054459/http://uk.pcmag.com/news/89652/ibm-figures-out-how-to-make-5nm-chips|url-status=live}}</ref>

===Commercialization===
In April 2019, [[Company:Samsung Electronics|Samsung Electronics]] announced they had been offering their 5&nbsp;nm process (5LPE) tools to their customers since 2018 Q4.<ref name="anandtech-samsung">{{Cite web|url=https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology|title=Samsung Completes Development of 5nm EUV Process Technology|last=Shilov|first=Anton|website=[[AnandTech]]|access-date=31 May 2019|archive-date=20 April 2019|archive-url=https://web.archive.org/web/20190420144452/https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology|url-status=live}}</ref> In April 2019, TSMC announced that their 5&nbsp;nm process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use [[Physics:Extreme ultraviolet lithography|EUVL]] on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++.<ref name="tsmc">{{cite press release | url = https://pr.tsmc.com/english/news/1987 | title = TSMC and OIP Ecosystem Partners Deliver Industry's First Complete Design Infrastructure for 5nm Process Technology | date = 3 April 2019 | publisher = TSMC }}</ref> For the expected 28&nbsp;nm minimum metal pitch, [[Physics:Extreme ultraviolet lithography#Use with multiple-patterning|SALELE]] is the proposed best patterning method.<ref>{{cite web|url=https://www.linkedin.com/pulse/salele-double-patterning-7nm-5nm-nodes-frederick-chen|title=SALELE Double Patterning for 7nm and 5nm Nodes|website=[[Company:LinkedIn|LinkedIn]]|access-date=25 March 2021|archive-date=20 September 2021|archive-url=https://web.archive.org/web/20210920235246/https://www.linkedin.com/pulse/salele-double-patterning-7nm-5nm-nodes-frederick-chen|url-status=live}}</ref>

For their 5&nbsp;nm process, Samsung started process defect mitigation by automated check and fix, due to occurrence of stochastic (random) defects in the metal and via layers.<ref>{{cite conference|author1=Jaehwan Kim|author2=Jin Kim|author3=Byungchul Shin|author4=Sangah Lee|author5=Jae-Hyun Kang|author6=Joong-Won Jeon|author7=Piyush Pathak|author8=Jac Condella|author9=Frank E. Gennari|author10=Philippe Hurat|author11=Ya-Chieh Lai|title=Process related yield risk mitigation with in-design pattern replacement for system ICs manufactured at advanced technology nodes|conference=Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280I|location=San Jose, California, United States|date=23 March 2020|doi=10.1117/12.2551970}}</ref>
 
In October 2019, TSMC reportedly started sampling 5&nbsp;nm [[Engineering:Apple A14|A14 processors for Apple]].<ref>{{Cite web|url=https://www.notebookcheck.net/TSMC-already-sampling-Apple-s-5-nm-A14-Bionic-SoCs-for-2020-iPhones.440058.0.html|title=TSMC already sampling Apple's 5 nm A14 Bionic SoCs for 2020 iPhones|first=Bogdan|last=Solca|website=Notebookcheck|date=22 October 2019 |access-date=12 January 2020|archive-date=12 January 2020|archive-url=https://web.archive.org/web/20200112210149/https://www.notebookcheck.net/TSMC-already-sampling-Apple-s-5-nm-A14-Bionic-SoCs-for-2020-iPhones.440058.0.html|url-status=live}}</ref>

In December 2019, TSMC announced an average yield of approximately 80%, with a peak yield per wafer of over 90% for their 5&nbsp;nm test chips with a die size of 17.92&nbsp;mm<sup>2</sup>.<ref>{{Cite web|url=https://www.anandtech.com/show/15219/early-tsmc-5nm-test-chip-yields-80-hvm-coming-in-h1-2020|title=Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020|first=Dr Ian|last=Cutress|website=[[AnandTech]]|access-date=19 December 2019|archive-date=25 May 2020|archive-url=https://web.archive.org/web/20200525115643/https://www.anandtech.com/show/15219/early-tsmc-5nm-test-chip-yields-80-hvm-coming-in-h1-2020|url-status=live}}</ref> In mid 2020 TSMC claimed its (N5) 5&nbsp;nm process offered 1.8x the density of its 7&nbsp;nm N7 process, with 15% speed improvement or 30% lower power consumption; an improved sub-version (N5P or N4) was claimed to improve on N5 with +5% speed or -10% power.<ref>{{cite web | url = https://www.extremetech.com/computing/314204-tsmc-plots-an-aggressive-course-for-3nm-lithography-and-beyond | title = TSMC Plots an Aggressive Course for 3nm Lithography and Beyond | first = Joel | last = Hruska | date = 25 August 2020 | website = [[ExtremeTech]] | access-date = 12 September 2020 | archive-date = 22 September 2020 | archive-url = https://web.archive.org/web/20200922235956/https://www.extremetech.com/computing/314204-tsmc-plots-an-aggressive-course-for-3nm-lithography-and-beyond | url-status = live }}</ref>

On 13 October 2020, Apple announced a new iPhone 12 lineup using the [[Engineering:Apple A14|A14]]. Together with the [[Engineering:Huawei Mate 40|Huawei Mate 40]] lineup using the [[Company:HiSilicon#Kirin 9000 & Kirin 9000E|HiSilicon Kirin 9000]], the A14 and Kirin 9000 were the first devices to be commercialized on TSMC's 5&nbsp;nm node. Later, on 10 November 2020, Apple also revealed three new Mac models using the [[Engineering:Apple M1|Apple M1]], another 5&nbsp;nm chip. According to Semianalysis, the A14 processor has a transistor density of 134 million transistors per mm<sup>2</sup>.<ref>{{cite web|last=Patel|first=Dylan|date=27 October 2020|title=Apple's A14 Packs 134 Million Transistors/mm², but Falls Short of TSMC's Density Claims|url=https://semianalysis.com/apples-a14-packs-134-million-transistors-mm2-but-falls-far-short-of-tsmcs-density-claims/|access-date=29 October 2020|website=SemiAnalysis|archive-date=12 December 2020|archive-url=https://web.archive.org/web/20201212210748/https://semianalysis.com/apples-a14-packs-134-million-transistors-mm2-but-falls-far-short-of-tsmcs-density-claims/|url-status=live}}</ref>

In October 2021, TSMC introduced a new member of its 5&nbsp;nm process family: N4P. Compared to N5, the node offers 11% higher performance (6% higher vs N4), 22% higher power efficiency, 6% higher transistor density and lower mask count. TSMC expects first tapeouts by the second half of 2022.<ref>{{cite press release|url=https://pr.tsmc.com/english/news/2874|title=TSMC Expands Advanced Technology Leadership with N4P Process|website=TSMC|date=26 October 2021}}</ref><ref>{{cite web|url=https://fuse.wikichip.org/news/6439/tsmc-extends-its-5nm-family-with-a-new-enhanced-performance-n4p-node/|title=TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node|website=WikiChip|date=26 October 2021|access-date=28 May 2022|archive-date=29 May 2022|archive-url=https://web.archive.org/web/20220529192402/https://fuse.wikichip.org/news/6439/tsmc-extends-its-5nm-family-with-a-new-enhanced-performance-n4p-node/|url-status=live}}</ref>

In December 2021, TSMC announced a new member of its 5&nbsp;nm process family designed for HPC applications: N4X. The process features optimized transistor design and structures, reduced resistance and capacitance of targeted metal layers and high-density MiM capacitors. The process will offer up to 15% higher performance vs N5 (or up to 4% vs N4P) at 1.2&nbsp;V and supply voltage in excess of 1.2&nbsp;V. TSMC expects N4X to enter risk production by the first half of 2023.<ref name=n4x_pr /><ref name=n4x_blog /><ref name=n4x_at />

In June 2022, Intel presented some details about the Intel 4 process (known as 7&nbsp;nm before renaming in 2021): the company's first process to use EUV, 2x higher transistor density compared to Intel 7 (known as 10&nbsp;nm ESF (Enhanced Super Fin) before the renaming), use of cobalt-clad copper for the finest five layers of interconnect, 21.5% higher performance at iso power or 40% lower power at iso frequency at 0.65 V compared to Intel 7 etc. Intel's first product to be fabbed on Intel 4 is Meteor Lake, powered on in Q2 2022 and scheduled for shipping in 2023.<ref name=intel4_at /> Intel 4 has contacted gate pitch of 50&nbsp;nm, both fin and minimum metal pitch of 30&nbsp;nm, and library height of 240&nbsp;nm. Metal-insulator-metal capacitance was increased to 376 fF/μm², roughly 2x compared to Intel 7.<ref>{{cite web
 |first=Scotten
 |last=Jones
 |url=https://semiwiki.com/semiconductor-manufacturers/intel/314047-intel-4-presented-at-vlsi/
 |title=Intel 4 Deep Dive
 |website=SemiWiki
 |date=13 June 2022
}}</ref> The process is optimized for HPC applications and supports voltage from <0.65 V to >1.3 V. WikiChip's transistor density estimate for Intel 4 is 123.4 Mtr./mm², 2.04x from 60.5 Mtr./mm² for Intel 7. However, high-density SRAM cell has scaled only by 0.77x (from 0.0312 to 0.024 μm²) and high-performance cell by 0.68x (from 0.0441 to 0.03 μm²) compared to Intel 7.<ref name=intel4_wikichip>{{cite web
 |first=David
 |last=Schor
 |url=https://fuse.wikichip.org/news/6720/a-look-at-intel-4-process-technology/
 |title=A Look At Intel 4 Process Technology
 |website=WikiChip Fuse
 |date=19 June 2022
}}</ref>

On 27 September 2022, [[Engineering:AMD|AMD]] officially launched their [[Engineering:Ryzen|Ryzen]] 7000 series of central processing units, based on the TSMC 5&nbsp;nm process and [[Engineering:Zen 4|Zen 4]] microarchitecture.<ref>{{cite press release |date=29 August 2022 |title=AMD Launches Ryzen 7000 Series Desktop Processors with "Zen 4" Architecture: the Fastest Core in Gaming |url=https://www.amd.com/en/press-releases/2022-08-29-amd-launches-ryzen-7000-series-desktop-processors-zen-4-architecture-the|access-date=31 March 2023}}</ref> Zen 4 marks the first utilization of the 5&nbsp;nm process for x86-based desktop processors. AMD also launched the [[Engineering:Radeon|Radeon]] 7000 series of graphics processing unit based on [[Engineering:RDNA 3|RDNA 3]] which also uses TSMC 5&nbsp;nm process.<ref>{{cite web |last1=Wickens |first1=Katie |date=30 August 2022 |title=AMD's Lisa Su confirms chiplet-based RDNA 3 GPU architecture |url=https://www.pcgamer.com/amds-lisa-su-confirms-chiplet-based-rdna-3-gpu-architecture/ |access-date=20 September 2022 |website=PC Gamer }}</ref>

==5&nbsp;nm process nodes==
{| class="wikitable" style="text-align:center"
|+5&nbsp;nm
!
! colspan=2|IRDS roadmap 2017<ref>{{Cite web|url=https://irds.ieee.org/images/files/pdf/2017/2017IRDS_MM.pdf|title=IRDS international roadmap for devices and systems 2017 edition|archive-url=https://web.archive.org/web/20181025031319/https://irds.ieee.org/images/files/pdf/2017/2017IRDS_MM.pdf|archive-date=25 October 2018|url-status=dead}}</ref>
! colspan=2|[[Company:Samsung Electronics|Samsung]]<ref name=5nm>{{citation| url =https://semiwiki.com/semiconductor-manufacturers/intel/285192-can-tsmc-maintain-their-process-technology-lead/| title =Can TSMC Maintain Their Process Technology Lead| first =Scotten| last =Jones| website =SemiWiki| date =29 April 2020| access-date =11 April 2022| archive-date =13 May 2022| archive-url =https://web.archive.org/web/20220513103058/https://semiwiki.com/semiconductor-manufacturers/intel/285192-can-tsmc-maintain-their-process-technology-lead/}}</ref><ref>{{cite web|url=https://semiwiki.com/semiconductor-manufacturers/samsung-foundry/259664-samsung-foundry-update-2019/|title=Samsung Foundry Update 2019|website=SemiWiki|date=6 August 2019|access-date=14 May 2022|archive-date=29 May 2022|archive-url=https://web.archive.org/web/20220529211918/https://semiwiki.com/semiconductor-manufacturers/samsung-foundry/259664-samsung-foundry-update-2019/|url-status=live}}</ref><ref name="Samsung 5 nm and 4 nm Update">{{cite web|url=https://fuse.wikichip.org/news/2823/samsung-5-nm-and-4-nm-update/|title=Samsung 5 nm and 4 nm Update|website=WikiChip|date=19 October 2019}}</ref><ref name="5 nm lithography process">{{cite web|url=https://en.wikichip.org/wiki/5_nm_lithography_process|title=5 nm lithography process|website=WikiChip|access-date=30 April 2017|archive-date=6 November 2020|archive-url=https://web.archive.org/web/20201106143813/https://en.wikichip.org/wiki/5_nm_lithography_process|url-status=live}}</ref><ref name="Samsung"/>
! colspan="3" |[[Company:TSMC|TSMC]]<ref name=5nm/>
|-
! Process name
| 7&nbsp;nm
| 5&nbsp;nm
| 5LPE
| 5LPP
| N5
| N5P
|4N<ref>{{cite web |title=NVIDIA Delivers Quantum Leap in Performance, Introduces New Era of Neural Rendering With GeForce RTX 40 Series |url=http://nvidianews.nvidia.com/news/nvidia-delivers-quantum-leap-in-performance-introduces-new-era-of-neural-rendering-with-geforce-rtx-40-series |access-date=20 September 2022 |website=NVIDIA Newsroom}}</ref>
|-
! Transistor density (MTr/mm<sup>2</sup>)
| {{Unknown}}
| {{Unknown}}
| 126.9<ref name=Samsung>{{cite web | url=https://fuse.wikichip.org/news/6932/samsung-3nm-gaafet-enters-risk-production-discusses-next-gen-improvements/ | title=Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements | date=5 July 2022 }}</ref>
| {{Unknown}}
| colspan=2|138.2<ref>{{cite web | url=https://www.angstronomics.com/p/the-truth-of-tsmc-5nm | title=The TRUTH of TSMC 5nm }}</ref><ref>{{cite web | url=https://fuse.wikichip.org/news/7048/n3e-replaces-n3-comes-in-many-flavors/ | title=N3E Replaces N3; Comes in Many Flavors | date=4 September 2022 }}</ref>
|{{Unknown|Unknown}}
|-
! SRAM bit-cell size (μm<sup>2</sup>)
| 0.027<ref name=mm2/> 
| 0.020<ref name=mm2/>
| colspan=2|0.0262<ref name="BitS">{{cite web | url=https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-witness-the-death-of-sram/ | title=Did We Just Witness The Death Of SRAM? | date=4 December 2022 }}</ref>
| colspan=2|0.021<ref name=BitS/>
|{{Unknown|Unknown}}
|-
! Transistor gate pitch (nm)
| 48
| 42
| colspan=2|57
| colspan=2|51
|{{Unknown|Unknown}}
|-
! Interconnect pitch (nm)
| 28
| 24
| 36
| {{Unknown}}
| colspan=2|28<ref>{{cite conference|author1=J.C. Liu|display-authors=0|title=A Reliability Enhanced 5nm CMOS Technology Featuring 5th Generation FinFET with Fully-Developed EUV and High Mobility Channel for Mobile SoC and High Performance Computing Application|conference=2020 IEEE International Electron Devices Meeting (IEDM)|doi=10.1109/IEDM13553.2020.9372009}}</ref>
|{{Unknown|Unknown}}
|-
! Release status
| 2019
| 2021
| {{yes|2018 risk production<ref name="anandtech-samsung"/><br/>2020 production}}
| {{yes|2022 production}}
| {{yes|2019 risk production<ref name="tsmc"/><br/>2020 production}}
| {{yes|2020 risk production<br/>2021 production}}
|{{Yes|2022 production}}
|-
|}

== 4 nm process nodes ==
{| class="wikitable" style="text-align:center"
!
! colspan="5" |[[Company:Samsung Electronics|Samsung]]<ref name="5nm" /><ref name="Samsung 5 nm and 4 nm Update"/><ref name="5 nm lithography process"/><ref name="Samsung"/><ref>{{cite web | url=https://www.anandtech.com/show/18854/-samsung-foundry-vows-to-surpass-tsmc-within-five-years | title=Samsung Foundry Vows to Surpass TSMC within Five Years }}</ref>
! colspan="3" |[[Company:TSMC|TSMC]]
! [[Company:Intel|Intel]]<ref name="intel_rm_2025">{{Cite web|last=Cutress|first=Dr Ian|title=Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!|url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros|access-date=27 July 2021|website=[[AnandTech]]|archive-date=3 November 2021|archive-url=https://web.archive.org/web/20211103110548/https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros|url-status=live}}</ref><ref name="intel4_at">{{Cite web|last=Smith|first=Ryan|title=Intel 4 Process Node In Detail: 2x Density Scaling, 20% Improved Performance|url=https://www.anandtech.com/show/17448/intel-4-process-node-in-detail-2x-density-scaling-20-improved-performance|access-date=13 June 2022|website=[[AnandTech]]|archive-date=13 June 2022|archive-url=https://web.archive.org/web/20220613113909/https://www.anandtech.com/show/17448/intel-4-process-node-in-detail-2x-density-scaling-20-improved-performance|url-status=live}}</ref>
|-
! Process name
| 4LPE
| 4LPP
| 4LPP+
| 4HPC
| 4LPA
| N4
| N4P
| N4X<ref name="n4x_pr">{{cite press release|url=https://pr.tsmc.com/english/news/2895|title=TSMC Introduces N4X Process|publisher=TSMC|date=16 December 2021}}</ref><ref name="n4x_blog">{{cite web|url=https://www.tsmc.com/english/news-events/blog-article-20211216|title=The Future Is Now (blog post)|website=TSMC|date=16 December 2021|access-date=25 May 2022|archive-date=7 May 2022|archive-url=https://web.archive.org/web/20220507120500/https://www.tsmc.com/english/news-events/blog-article-20211216|url-status=live}}</ref><ref name="n4x_at">{{cite web|url=https://www.anandtech.com/print/17123/tsmc-unveils-n4x-node-high-voltages-for-high-clocks|title=TSMC Unveils N4X Node|website=AnandTech|date=17 December 2021|access-date=25 May 2022|archive-date=25 May 2022|archive-url=https://web.archive.org/web/20220525052113/https://www.anandtech.com/print/17123/tsmc-unveils-n4x-node-high-voltages-for-high-clocks|url-status=live}}</ref>
| 4
|-
! Transistor density (MTr/mm<sup>2</sup>)
| colspan="2" |137<ref name="Samsung" />
| {{Unknown}}
| {{Unknown}}
| {{Unknown}}
| colspan="2" |143.7<ref>{{cite web | url=https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/ | title=TSMC N3, and Challenges Ahead | date=27 May 2023 }}</ref>
| {{Unknown}}
| 123.4<ref name="intel4_wikichip" />
|-
! SRAM bit-cell size (μm<sup>2</sup>)
| colspan="2" |0.0262<ref name="BitS"/>
| {{Unknown}}
| {{Unknown}}
| {{Unknown}}
| {{Unknown}}
| {{Unknown}}
| {{Unknown}}
| 0.024<ref name="BitS" />
|-
! Transistor gate pitch (nm)
| colspan="2" |57
| {{Unknown}}
| {{Unknown}}
| {{Unknown}}
| colspan="2" |51
| {{Unknown}}
| 50
|-
! Interconnect pitch (nm)
| colspan="2" |32
| {{Unknown}}
| {{Unknown}}
| {{Unknown}}
| colspan="2" |28
| {{Unknown}}
| 30
|-
! Release status
| {{yes|2020 risk production<br/>2021 production}}
| {{yes|2022 production}}
| {{yes|2023 production}}
| {{no|2024 production}}
| {{no|2025 production}}
| {{yes|2021 risk production<br/>2022 production}}
| {{yes|2022 risk production<br/>2022 production}}
| {{partial|Risk production by H1 2023<br/>2024 production}}
| {{yes|2022 risk production}}<ref>{{cite news |last1=Gartenberg |first1=Chaim |title=The summer Intel fell behind |url=https://www.theverge.com/22597713/intel-7nm-delay-summer-2020-apple-arm-switch-roadmap-gelsinger-ceo |access-date=22 December 2021 |work=[[The Verge]] |date=29 July 2021 |archive-date=22 December 2021 |archive-url=https://web.archive.org/web/20211222123234/https://www.theverge.com/22597713/intel-7nm-delay-summer-2020-apple-arm-switch-roadmap-gelsinger-ceo |url-status=live }}</ref><br>2023 production<ref>https://www.anandtech.com/show/20046/intel-unveils-meteor-lake-architecture-intel-4-heralds-the-disaggregated-future-of-mobile-cpus/2</ref>
|-
|}

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).<ref>{{Cite web|url=https://www.semiconductors.org/clientuploads/Research_Technology/ITRS/2015/0_2015%20ITRS%202.0%20Executive%20Report%20(1).pdf|title=International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report|website=Semiconductors.org|access-date=7 December 2017|archive-url=https://web.archive.org/web/20161002215308/http://www.semiconductors.org/clientuploads/Research_Technology/ITRS/2015/0_2015%20ITRS%202.0%20Executive%20Report%20%281%29.pdf|archive-date=2 October 2016|url-status=dead}}</ref><ref>{{cite web|url=https://en.wikichip.org/wiki/5_nm_lithography_process|title=5 nm lithography process|website=WikiChip|access-date=7 December 2017|archive-date=6 November 2020|archive-url=https://web.archive.org/web/20201106143813/https://en.wikichip.org/wiki/5_nm_lithography_process|url-status=live}}</ref>

==Beyond 4&nbsp;nm==

''3&nbsp;nm'' (3-nanometer) is the usual term for the next node after 5&nbsp;nm. {{As of|2023}}, [[Company:TSMC|TSMC]] has started producing chips for select customers, while [[Company:Samsung|Samsung]] and [[Company:Intel|Intel]] have plans for 2024.<ref name=intel_rm_2025/><ref>{{Cite web|url=https://www.techpowerup.com/283983/samsung-3-nm-gaafet-node-delayed-to-2024|title=Samsung 3 nm GAAFET Node Delayed to 2024|date=30 June 2021 |access-date=8 July 2021|archive-date=17 December 2021|archive-url=https://web.archive.org/web/20211217032212/https://www.techpowerup.com/283983/samsung-3-nm-gaafet-node-delayed-to-2024|url-status=live}}</ref><ref>{{Cite web|last=Shilov|first=Anton|title=Samsung: Deployment of 3nm GAE Node on Track for 2022|url=https://www.anandtech.com/show/16815/samsung-deployment-of-3nm-gae-on-track-for-2022|access-date=27 July 2021|website=[[AnandTech]]|archive-date=27 July 2021|archive-url=https://web.archive.org/web/20210727190914/https://www.anandtech.com/show/16815/samsung-deployment-of-3nm-gae-on-track-for-2022|url-status=live}}</ref><ref>{{Cite web|last=Shilov|first=Anton|title=TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022|url=https://www.anandtech.com/show/16639/tsmc-update-2nm-in-development-3nm-4nm-on-track-for-2022|access-date=27 July 2021|website=[[AnandTech]]|archive-date=27 July 2021|archive-url=https://web.archive.org/web/20210727190912/https://www.anandtech.com/show/16639/tsmc-update-2nm-in-development-3nm-4nm-on-track-for-2022|url-status=live}}</ref>

3.5&nbsp;nm has also been given as a name for the first node beyond 5&nbsp;nm.<ref>{{cite web|url=https://www.eetimes.com/document.asp?doc_id=1331185|title=15 Views from a Silicon Summit: Macro to nano perspectives of chip horizon|date=16 January 2017|website=EE Times|access-date=4 June 2018|archive-date=28 June 2018|archive-url=https://web.archive.org/web/20180628100622/https://www.eetimes.com/document.asp?doc_id=1331185|url-status=live}}</ref>

==References==
{{Reflist| refs =
<ref name=mm2>{{citation | url = https://irds.ieee.org/images/files/pdf/2017/2017IRDS_MM.pdf | title = INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - MORE MOORE | publisher = ITRS | year = 2017 | access-date = 24 October 2018 | archive-url = https://web.archive.org/web/20181025031319/https://irds.ieee.org/images/files/pdf/2017/2017IRDS_MM.pdf | archive-date = 25 October 2018 | url-status = dead |at = Section 4.5 Table MM-10 (p.12) entries : "SRAM bitcell area (um2)" ; "SRAM 111 bit cell area density - Mbits/mm2" }}</ref>
}}

==External links==
* [https://en.wikichip.org/wiki/5_nm_lithography_process 5 nm lithography process]

{{sequence
| prev=7&nbsp;nm ([[Engineering:FinFET|FinFET]])
| list=[[Engineering:MOSFET|MOSFET]] [[Engineering:Semiconductor device fabrication|semiconductor device fabrication]] process
| next=[[Engineering:3 nm process|3&nbsp;nm]] ([[Engineering:FinFET|FinFET]]/GAAFET)
}}

{{DEFAULTSORT:5 nanometre}}
[[Category:Application-specific integrated circuits]]

{{Sourceattribution|5 nm process}}