View source for Engineering:CMOS

'''Complementary metal–oxide–semiconductor''' ('''CMOS''' {{IPAc-en|ˈ|s|iː|m|ɒ|s}} {{respell|SEE|-|moss}}) is a type of [[Engineering:MOSFET|metal–oxide–semiconductor field-effect transistor]] (MOSFET) [[Engineering:Semiconductor device fabrication|fabrication process]] that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions.<ref>{{cite web |title=What is CMOS Memory? |url=http://wickedsago.blogspot.com/2011/04/what-is-cmos-memory.html |work=Wicked Sago |access-date=3 March 2013 |url-status=live |archive-url=https://web.archive.org/web/20140926064548/http://wickedsago.blogspot.com/2011/04/what-is-cmos-memory.html |archive-date=26 September 2014 }}</ref> CMOS technology is used for constructing [[Engineering:Integrated circuit|integrated circuit]] (IC) chips, including [[Engineering:Microprocessor|microprocessor]]s, [[Engineering:Microcontroller|microcontroller]]s, memory chips, and other digital logic circuits. CMOS overtook [[NMOS logic]] as the dominant MOSFET fabrication process for very large-scale integration (VLSI) chips in the 1980s, replacing earlier [[Transistor–transistor logic|transistor–transistor logic]] (TTL) technology at the same time. CMOS has since remained the standard fabrication process for MOSFET [[Physics:Semiconductor device|semiconductor device]]s. {{As of|2011}}, 99% of IC chips, including most [[Engineering:Digital electronics|digital]], analog and mixed-signal ICs, were fabricated using CMOS technology.<ref>{{cite book |last1=Voinigescu |first1=Sorin |title=High-Frequency Integrated Circuits |date=2013 |publisher=Cambridge University Press |isbn=978-0-521-87302-4 |page=164 |url=https://books.google.com/books?id=71dHe1yb9jgC&pg=PA164}}</ref>

In 1948, Bardeen and Brattain patented an insulated-gate transistor (IGFET) with an inversion layer. Bardeen's concept forms the basis of CMOS technology today. The CMOS process was presented by [[Company:Fairchild Semiconductor|Fairchild Semiconductor]]'s Frank Wanlass and Chih-Tang Sah at the International Solid-State Circuits Conference in 1963. Wanlass later filed US patent 3,356,858 for CMOS circuitry and it was granted in 1967. [[RCA Corporation|{{Tooltip|RCA|Radio Corporation of America, now a defunct American electronics company established in 1919}}]] commercialized the technology with the trademark "COS-MOS" in the late 1960s, forcing other manufacturers to find another name, leading to "CMOS" becoming the standard name for the technology by the early 1970s. 
Two important characteristics of CMOS devices are high noise immunity and low static power consumption.<ref>Fairchild. Application Note 77. [https://www.fairchildsemi.com/application-notes/AN/AN-77.pdf "CMOS, the Ideal Logic Family"]; {{webarchive|url=https://web.archive.org/web/20150109070537/https://www.fairchildsemi.com/application-notes/AN/AN-77.pdf |date=2015-01-09 }}. 1983.</ref> Since one [[Engineering:Transistor|transistor]] of the MOSFET pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as much [[Astronomy:Waste heat|waste heat]] as other forms of logic, like [[NMOS logic]] or [[Transistor–transistor logic|transistor–transistor logic]] (TTL), which normally have some standing current even when not changing state. These characteristics allow CMOS to integrate a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most widely used technology to be implemented in VLSI chips.

The phrase "metal–oxide–semiconductor" is a reference to the physical structure of MOS [[Engineering:Field-effect transistor|field-effect transistor]]s, having a [[Physics:Metal gate|metal gate]] electrode placed on top of an oxide insulator, which in turn is on top of a [[Physics:Semiconductor|semiconductor material]]. [[Chemistry:Aluminium|Aluminium]] was once used but now the material is polysilicon. Other metal gates have made a comeback with the advent of [[Engineering:High-κ dielectric|high-κ dielectric]] materials in the CMOS process, as announced by IBM and Intel for the 45 nanometer node and smaller sizes.<ref>{{cite web|url=http://www.intel.com/technology/45nm/index.htm|title=Intel Architecture Leads the Microarchitecture Innovation Field|publisher=Intel|access-date=2 May 2018|url-status=live|archive-url=https://web.archive.org/web/20110629140302/http://www.intel.com/technology/45nm/index.htm|archive-date=29 June 2011}}</ref>

CMOS technology is also used for analog circuits such as [[Engineering:Image sensor|image sensor]]s (CMOS sensors), [[Data conversion|data converters]], RF circuits ([[Engineering:RF CMOS|RF CMOS]]), and highly integrated [[Transceiver|transceiver]]s for many types of communication.

== History ==
{{Main|Engineering:History of the transistor}}
{{See|MOSFET|Transistor density}}
[[File:1957(Figure_9)-Gate_oxide_transistor_by_Frosch_and_Derrick.png|thumb|310x310px|1957 diagram of one of the transistor devices made by Frosch and Derick<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref>]]

The principle of complementary symmetry was first introduced by George Sziklai in 1953 who then discussed several complementary bipolar circuits. Paul Weimer, also at [[Company:RCA Corporation|RCA]], invented in 1962 [[Physics:Thin-film transistor|thin-film transistor]] (TFT) complementary circuits, a close relative of CMOS. He invented complementary [[Engineering:Flip-flop (electronics)|flip-flop]] and inverter circuits, but did no work in a more complex complementary logic. He was the first person able to put p-channel and n-channel TFTs in a circuit on the same substrate. Three years earlier, John T. Wallmark and Sanford M. Marcus published a variety of complex logic functions implemented as integrated circuits using [[Engineering:JFET|JFET]]s, including complementary memory circuits. Frank Wanlass was familiar with work done by Weimer at RCA.<ref>{{cite journal |last1=George Clifford |first1=Sziklai |title=Symmetrical Properties of Transistors and Their Applications |date=1953 | volume=41 | issue=6 | pages=717–724 |journal=Proceedings of the IRE |doi=10.1109/JRPROC.1953.274250|bibcode=1953PIRE...41..717S |s2cid=51639018 }}</ref><ref>{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer |isbn=978-3-540-34258-8 |page=162}}</ref><ref>{{cite journal |first=Richard |last=Ahrons | title=Industrial Research in Microcircuitry at RCA: The Early Years, 1953–1963 | year=2012 | volume=12 | issue=1 | pages=60–73 |journal= IEEE Annals of the History of Computing |doi=10.1109/MAHC.2011.62|bibcode=2012IAHC...34a..60A |s2cid=18912623 }}</ref><ref>{{cite web | title=Oral History of Thomas (Tom) Stanley | url=https://archive.computerhistory.org/resources/access/text/2015/06/102702047-05-01-acc.pdf}}</ref><ref>{{cite journal | title=IRE News and Radio Notes |journal = Proceedings of the IRE|year = 1954|volume = 42|issue = 6|pages = 1027–1043|doi = 10.1109/JRPROC.1954.274784 | bibcode=1954PIRE...42.1027. }}</ref><ref>{{cite book|first1=J.T. |last1=Wallmark |first2=S.M. |last2=Marcus|chapter=Integrated devices using Direct-Coupled Unipolar Transistor Logic|year=1959 |title=1959 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |volume=EC-8|issue=2|pages=58–59 |doi=10.1109/ISSCC.1959.1157035}}</ref>

In 1955, Carl Frosch and Lincoln Derick accidentally grew a layer of silicon dioxide over the silicon wafer, for which they observed surface passivation effects.<ref name=":0">{{Cite journal |last1=Huff |first1=Howard |last2=Riordan |first2=Michael |date=2007-09-01 |title=Frosch and Derick: Fifty Years Later (Foreword) |url=https://iopscience.iop.org/article/10.1149/2.F02073IF |journal=The Electrochemical Society Interface |volume=16 |issue=3 |page=29 |doi=10.1149/2.F02073IF |issn=1064-8208}}</ref> By 1957, Frosch and Derick, using masking and predeposition, were able to manufacture silicon transistors. They showed that silicon dioxide protected silicon wafers from dopants diffusing into the wafer, and insulated the wafer from damage due to heat during the process.<ref name=":0" /><ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |page=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> J.R. Ligenza and W.G. Spitzer studied the mechanism of thermally grown oxides and fabricated a high quality Si/[[Chemistry:Silicon dioxide|SiO<sub>2</sub>]] stack in 1960.<ref>{{Cite journal |last1=Ligenza |first1=J. R. |last2=Spitzer |first2=W. G. |date=1960-07-01 |title=The mechanisms for silicon oxidation in steam and oxygen |url=https://linkinghub.elsevier.com/retrieve/pii/0022369760902195 |journal=Journal of Physics and Chemistry of Solids |volume=14 |pages=131–136 |doi=10.1016/0022-3697(60)90219-5 |bibcode=1960JPCS...14..131L |issn=0022-3697|url-access=subscription }}</ref><ref name="Deal">{{cite book |last1=Deal |first1=Bruce E. |title=Silicon materials science and technology |date=1998 |publisher=The Electrochemical Society |isbn=978-1-56677-193-1 |page=183 |chapter=Highlights Of Silicon Thermal Oxidation Technology |chapter-url=https://books.google.com/books?id=cr8FPGkiRS0C&pg=PA183}}</ref><ref>{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer Science & Business Media |isbn=978-3-540-34258-8 |page=322}}</ref>

[[File:Threshold_formation_nowatermark.gif|thumb|Simulation of formation of inversion channel (electron density) and attainment of [[Physics:Threshold voltage|threshold voltage]] (IV) in a nanowire MOSFET. Threshold voltage for this device lies around 0.45&nbsp;V.]]

Following this research, Mohamed Atalla and [[Biography:Dawon Kahng|Dawon Kahng]] proposed a silicon MOS transistor in 1959<ref name="Bassett22">{{cite book |last1=Bassett |first1=Ross Knox |url=https://books.google.com/books?id=UUbB3d2UnaAC&pg=PA22 |title=To the Digital Age: Research Labs, Start-up Companies, and the Rise of MOS Technology |date=2007 |publisher=Johns Hopkins University Press |isbn=978-0-8018-8639-3 |pages=22–23}}</ref> and successfully demonstrated a working MOS device with their Bell Labs team in 1960.<ref>{{cite journal |last1=Atalla |first1=M. |last2=Kahng |first2=D. |date=1960 |title=Silicon-silicon dioxide field induced surface devices |journal=IRE-AIEE Solid State Device Research Conference}}</ref><ref>{{cite journal |title=1960 – Metal Oxide Semiconductor (MOS) Transistor Demonstrated |url=https://www.computerhistory.org/siliconengine/metal-oxide-semiconductor-mos-transistor-demonstrated/ |journal=The Silicon Engine |publisher=Computer History Museum |access-date=2023-01-16}}</ref> Their team included E. E. LaBate and E. I. Povilonis who fabricated the device; M. O. Thurston, L. A. D'Asaro, and J. R. Ligenza who developed the diffusion processes, and H. K. Gummel and R. Lindner who characterized the device.<ref>{{Cite book |last=KAHNG |first=D. |title=Semiconductor Devices: Pioneering Papers |year=1961 |chapter=Silicon-Silicon Dioxide Surface Device |journal=Technical Memorandum of Bell Laboratories |pages=583–596 |doi=10.1142/9789814503464_0076 }} Reprinted in Sze, S. M. (1991). ''Semiconductor Devices: Pioneering Papers''. Singapore: World Scientific. {{doi|10.1142/1087}}. {{ISBN|978-981-02-0209-5}}.</ref><ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> There were originally two types of MOSFET logic, [[PMOS logic|PMOS]] (p-type MOS) and [[NMOS logic|NMOS]] (n-type MOS).<ref>{{cite journal |title=1960 - Metal Oxide Semiconductor (MOS) Transistor Demonstrated |url=https://www.computerhistory.org/siliconengine/metal-oxide-semiconductor-mos-transistor-demonstrated/ |journal=The Silicon Engine |publisher=Computer History Museum}}</ref>

In 1948, Bardeen and Brattain patented the progenitor of MOSFET, an insulated-gate FET (IGFET) with an inversion layer. Bardeen's patent, and the concept of an inversion layer, forms the basis of CMOS technology today.<ref>{{cite book |author=Howard R. Duff |title=AIP Conference Proceedings |date=2001 |volume=550 |pages=3–32 |chapter=John Bardeen and transistor physics |doi=10.1063/1.1354371 |doi-access=free}}</ref> A new type of MOSFET logic combining both the PMOS and NMOS processes was developed, called complementary MOS (CMOS), by Chih-Tang Sah and Frank Wanlass at Fairchild. In February 1963, they published the invention in a research paper.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |website=Computer History Museum |access-date=6 July 2019}}</ref><ref name="sah">{{cite conference |last1=Sah |first1=Chih-Tang |last2=Wanlass |first2=Frank |title=Nanowatt logic using field-effect metal-oxide semiconductor triodes |conference=1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |date=1963 |volume=VI |pages=32–33 |doi=10.1109/ISSCC.1963.1157450}}</ref> In both the research paper and the [[Social:Patent|patent]] filed by Wanlass, the fabrication of CMOS devices was outlined, on the basis of [[Physics:Thermal oxidation|thermal oxidation]] of a silicon substrate to yield a layer of [[Chemistry:Silicon dioxide|silicon dioxide]] located between the drain contact and the source contact.<ref>{{cite web| url = http://www.freepatentsonline.com/3356858.pdf| title = Low stand-by power complementary field effect circuitry}}</ref><ref name="sah"/>

CMOS was commercialised by [[Company:RCA Corporation|RCA]] in the late 1960s. RCA adopted CMOS for the design of [[Engineering:Integrated circuit|integrated circuit]]s (ICs), developing CMOS circuits for an Air Force computer in 1965 and then a 288-[[Bit|bit]] CMOS [[Static random-access memory|SRAM]] memory chip in 1968.<ref name="computerhistory1963"/> RCA also used CMOS for its [[Engineering:4000-series integrated circuits|4000-series integrated circuits]] in 1968, starting with a 20{{nbsp}}μm semiconductor manufacturing process before gradually scaling to a 10&nbsp;μm process over the next several years.<ref name="Lojek330">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer |isbn=978-3-540-34258-8 |page=330 |url=https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA330}}</ref>

CMOS technology was initially overlooked by the American [[Engineering:Semiconductor industry|semiconductor industry]] in favour of NMOS, which was more powerful at the time. However, CMOS was quickly adopted and further advanced by Japanese semiconductor manufacturers due to its low power consumption, leading to the rise of the Japanese semiconductor industry.<ref>{{cite book |last1=Gilder |first1=George |title=Microcosm: The Quantum Revolution In Economics And Technology |date=1990 |publisher=Simon and Schuster |isbn=978-0-671-70592-3 |pages=[https://archive.org/details/microcosm00geor/page/144 144]–5 |url=https://archive.org/details/microcosm00geor|url-access=registration }}</ref> [[Company:Toshiba|Toshiba]] developed C<sup>2</sup>MOS (''clocked CMOS''), a circuit technology with lower power consumption and faster operating speed than ordinary CMOS, in 1969. Toshiba used its C<sup>2</sup>MOS technology to develop a large-scale integration (LSI) chip for [[Company:Sharp Corporation|Sharp]]'s Elsi Mini [[Engineering:LED|LED]] pocket calculator, developed in 1971 and released in 1972.<ref>{{cite web |title=1972 to 1973: CMOS LSI circuits for calculators (Sharp and Toshiba) |url=http://www.shmj.or.jp/english/pdf/ic/exhibi707E.pdf |website=Semiconductor History Museum of Japan |access-date=5 July 2019 |archive-url=https://web.archive.org/web/20190706035338/http://www.shmj.or.jp/english/pdf/ic/exhibi707E.pdf |archive-date=2019-07-06 }}</ref> Suwa Seikosha (now [[Company:Seiko Epson|Seiko Epson]]) began developing a CMOS IC chip for a [[Company:Seiko|Seiko]] quartz watch in 1969, and began mass-production with the launch of the [[Company:Seiko|Seiko]] Analog Quartz 38SQW watch in 1971.<ref>{{cite web |title=Early 1970s: Evolution of CMOS LSI circuits for watches |url=http://www.shmj.or.jp/english/pdf/ic/exhibi757E.pdf |website=Semiconductor History Museum of Japan |access-date=6 July 2019 |archive-url=https://web.archive.org/web/20190706144338/http://www.shmj.or.jp/english/pdf/ic/exhibi757E.pdf |archive-date=6 July 2019 }}</ref> The first mass-produced CMOS consumer electronic product was the [[Company:Hamilton Watch Company|Hamilton]] Pulsar "Wrist Computer" digital watch, released in 1970.<ref name="computerhistory-digital">{{cite web |title=Tortoise of Transistors Wins the Race - CHM Revolution |url=https://www.computerhistory.org/revolution/digital-logic/12/279 |website=Computer History Museum |access-date=22 July 2019}}</ref> Due to low power consumption, CMOS logic has been widely used for calculators and watches since the 1970s.<ref name="shmj">{{cite web |title=1978: Double-well fast CMOS SRAM (Hitachi) |url=http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf |website=Semiconductor History Museum of Japan |access-date=5 July 2019 |archive-url=https://web.archive.org/web/20190705234921/http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf |archive-date=5 July 2019 }}</ref>

The [[Microprocessor chronology|earliest microprocessors]] in the early 1970s were PMOS processors, which initially dominated the early [[Engineering:Microprocessor|microprocessor]] industry. By the late 1970s, NMOS microprocessors had overtaken PMOS processors.<ref name="Kuhn">{{cite book |last1=Kuhn |first1=Kelin |title=High Mobility Materials for CMOS Applications |date=2018 |publisher=[[Company:Woodhead Publishing|Woodhead Publishing]] |isbn=978-0-08-102062-3 |chapter=CMOS and Beyond CMOS: Scaling Challenges |page=1 |chapter-url=https://books.google.com/books?id=sOJgDwAAQBAJ&pg=PA1}}</ref> CMOS microprocessors were introduced in 1975, with the [[Engineering:Intersil 6100|Intersil 6100]],<ref name="Kuhn"/> and RCA CDP 1801.<ref>{{cite journal |title=CDP 1800 μP Commercially available |journal=Microcomputer Digest |volume=2 |issue=4 |pages=1–3 |date=October 1975 |url=http://www.bitsavers.org/pdf/microcomputerAssociates/Microcomputer_Digest_v02n04_Oct75.pdf |access-date=2019-07-22 |archive-date=2019-09-23 |archive-url=https://web.archive.org/web/20190923120937/http://bitsavers.org/pdf/microcomputerAssociates/Microcomputer_Digest_v02n04_Oct75.pdf }}</ref> However, CMOS processors did not become dominant until the 1980s.<ref name="Kuhn"/>

CMOS was initially slower than [[NMOS logic]], thus NMOS was more widely used for computers in the 1970s.<ref name="shmj"/> The [[Company:Intel|Intel]] 5101 (1{{nbsp}}[[Kibibit|kb]] [[Static random-access memory|SRAM]]) CMOS memory chip (1974) had an [[Access time|access time]] of 800{{nbsp}}[[Nanosecond|ns]],<ref>{{cite web |title=Silicon Gate MOS 2102A |url=https://drive.google.com/file/d/0B9rh9tVI0J5mMmZlYWRlMDQtNDYzYS00OWJkLTg4YzYtZDYzMzc5Y2ZlYmVk/view |publisher=[[Company:Intel|Intel]] |access-date=27 June 2019}}</ref><ref name="Intel-Product-Timeline">{{cite web|url=http://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf|title=A chronological list of Intel products. The products are sorted by date.|date=July 2005|work=Intel museum|publisher=Intel Corporation|archive-url=https://web.archive.org/web/20070809053720/http://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf|archive-date=August 9, 2007|access-date=July 31, 2007}}</ref> whereas the fastest NMOS chip at the time, the Intel 2147 (4{{nbsp}}kb SRAM) HMOS memory chip (1976), had an access time of 55/70{{nbsp}}ns.<ref name="shmj"/><ref name="Intel-Product-Timeline"/> In 1978, a [[Company:Hitachi|Hitachi]] research team led by Toshiaki Masuhara introduced the twin-well Hi-CMOS process, with its HM6147 (4{{nbsp}}kb SRAM) memory chip, manufactured with a 3 μm process.<ref name="shmj"/><ref>{{cite conference |last1=Masuhara |first1=Toshiaki |last2=Minato |first2=Osamu |last3=Sasaki |first3=Toshio |last4=Sakai |first4=Yoshio |last5=Kubo |first5=Masaharu |last6=Yasui |first6=Tokumasa |title=A high-speed, low-power Hi-CMOS 4K static RAM |conference=1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |date=February 1978 |volume=XXI |pages=110–111 |doi=10.1109/ISSCC.1978.1155749|s2cid=30753823 }}</ref><ref>{{cite journal |last1=Masuhara |first1=Toshiaki |last2=Minato |first2=Osamu |last3=Sakai |first3=Yoshi |last4=Sasaki |first4=Toshio |last5=Kubo |first5=Masaharu |last6=Yasui |first6=Tokumasa |title=Short Channel Hi-CMOS Device and Circuits |journal=ESSCIRC 78: 4th European Solid State Circuits Conference - Digest of Technical Papers |date=September 1978 |pages=131–2 |url=https://ieeexplore.ieee.org/document/5469023}}</ref> The Hitachi HM6147 chip was able to match the performance (55/70{{nbsp}}ns access) of the Intel 2147 HMOS chip, while the HM6147 also consumed significantly less power (15{{nbsp}}mA) than the 2147 (110{{nbsp}}mA). With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most common semiconductor manufacturing process for computers in the 1980s.<ref name="shmj"/>

In the 1980s, CMOS microprocessors overtook NMOS microprocessors.<ref name="Kuhn"/> [[Organization:NASA|NASA]]'s [[Engineering:Galileo (spacecraft)|Galileo]] spacecraft, sent to orbit [[Astronomy:Jupiter|Jupiter]] in 1989, used the RCA 1802 CMOS microprocessor due to low power consumption.<ref name="computerhistory-digital"/>

Intel introduced a 1.5 μm process for CMOS [[Engineering:Semiconductor device fabrication|semiconductor device fabrication]] in 1983.<ref name="Gealow">{{cite web |last1=Gealow |first1=Jeffrey Carl |title=Impact of Processing Technology on DRAM Sense Amplifier Design |url=https://core.ac.uk/download/pdf/4426308.pdf |publisher=[[Organization:Massachusetts Institute of Technology|Massachusetts Institute of Technology]] |via=[[CORE (research service)|CORE]] |date=10 August 1990 |pages=149–166 |access-date=25 June 2019 |hdl=1721.1/61805/23264695-MIT}}</ref> In the mid-1980s, Bijan Davari of [[Company:IBM|IBM]] developed high-performance, low-voltage, [[Engineering:Nanoelectronics|deep sub-micron]] CMOS technology, which enabled the development of faster computers as well as portable computers and battery-powered handheld electronics.<ref name="recipients">{{cite web |title=IEEE Andrew S. Grove Award Recipients |url=https://www.ieee.org/about/awards/bios/grove-recipients.html |archive-url=https://web.archive.org/web/20180909112404/https://www.ieee.org/about/awards/bios/grove-recipients.html |archive-date=September 9, 2018 |website=IEEE Andrew S. Grove Award |publisher=[[Organization:Institute of Electrical and Electronics Engineers|Institute of Electrical and Electronics Engineers]] |access-date=4 July 2019}}</ref> In 1988, Davari led an IBM team that demonstrated a high-performance 250 nanometer CMOS process.<ref name="Davari1988">{{cite conference|last1=Davari |display-authors=0 |first1=Bijan|title=Technical Digest, International Electron Devices Meeting 1988 |chapter=A high performance 0.25 mu m CMOS technology |issn= 0163-1918  |id=IEEE Cat. No. 88CH2528-8|date=1988|pages=56–59 |doi=10.1109/IEDM.1988.32749 |s2cid=114078857 }}</ref>

[[Company:Fujitsu|Fujitsu]] commercialized a 700{{nbsp}}[[Nanometre|nm]] CMOS process in 1987,<ref name="Gealow"/> and then Hitachi, [[Company:Mitsubishi Electric|Mitsubishi Electric]], [[Company:NEC|NEC]] and Toshiba commercialized 500{{nbsp}}nm CMOS in 1989.<ref name="stol">{{cite web|url=http://maltiel-consulting.com/Semiconductor_technology_memory.html|title=Memory|website=STOL (Semiconductor Technology Online)|access-date=25 June 2019|archive-date=2 November 2023|archive-url=https://web.archive.org/web/20231102131915/http://maltiel-consulting.com/Semiconductor_technology_memory.html}}</ref> In 1993, [[Company:Sony|Sony]] commercialized a 350{{nbsp}}nm CMOS process, while Hitachi and NEC commercialized 250{{nbsp}}nm CMOS. Hitachi introduced a 160{{nbsp}}nm CMOS process in 1995, then Mitsubishi introduced 150{{nbsp}}nm CMOS in 1996, and then [[Company:Samsung Electronics|Samsung Electronics]] introduced 140{{nbsp}}nm in 1999.<ref name="stol"/>

In 2000, Gurtej Singh Sandhu and Trung T. Doan at [[Company:Micron Technology|Micron Technology]] invented [[Physics:Atomic layer deposition|atomic layer deposition]] [[Engineering:High-κ dielectric|High-κ dielectric]] [[Physics:Thin film|films]], leading to the development of a cost-effective 90&nbsp;nm CMOS process.<ref name="recipients"/><ref>{{cite web |last1=Sandhu |first1=Gurtej |last2=Doan |first2=Trung T. |title=Atomic layer doping apparatus and method |url=https://patents.google.com/patent/WO2002038841A3 |website=Google Patents |access-date=5 July 2019 |date=22 August 2001}}</ref> Toshiba and Sony developed a 65 nm CMOS process in 2002,<ref>{{cite news |title=Toshiba and Sony Make Major Advances in Semiconductor Process Technologies |url=https://www.toshiba.co.jp/about/press/2002_12/pr0301.htm |access-date=26 June 2019 |work=[[Company:Toshiba|Toshiba]] |date=3 December 2002}}</ref> and then [[Company:TSMC|TSMC]] initiated the development of 45 nm CMOS logic in 2004.<ref>{{cite web |title=A Banner Year: TSMC Annual Report 2004 |url=https://www.tsmc.com/download/ir/annualReports/2004/2004e.pdf |publisher=[[Company:TSMC|TSMC]] |access-date=5 July 2019}}</ref> The development of pitch double patterning by Gurtej Singh Sandhu at Micron Technology led to the development of 30{{nbsp}}nm class CMOS in the 2000s.<ref name="recipients"/>

CMOS is used in most modern LSI and VLSI devices.<ref name="shmj"/> As of 2010, CPUs with the best [[Performance per watt|performance per watt]] each year have been CMOS [[Static logic (digital logic)|static logic]] since 1976. As of 2019, planar CMOS technology is still the most common form of semiconductor device fabrication, but is gradually being replaced by non-planar [[Engineering:FinFET|FinFET]] technology, which is capable of manufacturing semiconductor nodes smaller than 20{{nbsp}}nm.<ref>{{cite news |title=Global FinFET Technology Market 2024 Growth Analysis by Manufacturers, Regions, Type and Application, Forecast Analysis |url=https://financialplanning24.com/global-finfet-technology-market-2024-growth-analysis-by-manufacturers-regions-type-and-application-forecast-analysis/ |access-date=6 July 2019 |work=Financial Planning |date=July 3, 2019 |archive-date=6 July 2019 |archive-url=https://web.archive.org/web/20190706032036/https://financialplanning24.com/global-finfet-technology-market-2024-growth-analysis-by-manufacturers-regions-type-and-application-forecast-analysis/ }}</ref>

== Technical details ==
{{See|Semiconductor manufacturing processes}}

"CMOS" refers to both a particular style of digital circuitry design and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates [[Physics:Low-power electronics|less power]] than [[Logic family|logic families]] with resistive loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate, thus the vast majority of modern integrated circuit manufacturing is on CMOS processes.<ref>{{cite book |title=CMOS: circuit design, layout, and simulation |last=Baker |first=R. Jacob |year=2008 |publisher=Wiley-IEEE |edition=Second |isbn=978-0-470-22941-5 |page=xxix}}</ref> CMOS logic consumes around one seventh the power of [[NMOS logic]],<ref name="shmj"/> and about 10 million times less power than bipolar transistor-transistor logic (TTL).<ref>{{cite book |last1=Higgins |first1=Richard J. |title=Electronics with digital and analog integrated circuits |date=1983 |publisher=Prentice-Hall |isbn=978-0-13-250704-2 |page=[https://archive.org/details/electronicswithd0000higg/page/101 101] |url=https://archive.org/details/electronicswithd0000higg |url-access=registration |quote=The dominant difference is power: CMOS gates can consume about 100,000 times less power than their TTL equivalents!}}</ref><ref>{{cite journal |last1=Stephens |first1=Carlene |last2=Dennis |first2=Maggie |title=Engineering Time: Inventing the Electronic Wristwatch |journal=The British Journal for the History of Science |date=2000 |volume=33 |issue=4 |pages=477–497 (485) |publisher=Cambridge University Press |url=http://ieee-uffc.org/wp-content/uploads/2016/11/step.pdf#page=11 |issn=0007-0874 |doi=10.1017/S0007087400004167 |access-date=2019-11-10 |archive-date=2017-12-01 |archive-url=https://web.archive.org/web/20171201035923/http://ieee-uffc.org/wp-content/uploads/2016/11/step.pdf#page=11 }}</ref>


CMOS always uses all enhancement-mode MOSFETs (in other words, a zero gate-to-source voltage turns the transistor off).<ref>{{Cite web|title=What is CMOS?|url=https://www.ionos.com/digitalguide/server/know-how/what-is-cmos/|access-date=2022-01-21|website=IONOS Digitalguide|date=8 December 2021 |language=en}}</ref>

== Inversion ==
CMOS circuits are constructed in such a way that all [[PMOS logic|p-type metal–oxide–semiconductor]] (PMOS) transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all [[NMOS logic|NMOS]] transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low [[Physics:Electrical resistance|resistance]] between its source and drain contacts when a low gate [[Physics:Voltage|voltage]] is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct, while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time, both pMOS and nMOS MOSFETs conduct briefly as the gate voltage transitions from one state to another. This induces a brief spike in power consumption and becomes a serious issue at high frequencies.

[[File:CMOS Inverter.svg|thumb|Static CMOS inverter. '''V<sub>dd</sub>''' and '''V<sub>ss</sub>''' stand for [[IC power-supply pin|drain and source]], respectively.{{Efn|name=Symbols|Transistors symbols show here are simplified logic symbols and not electrical schematic symbols.}}]]
The adjacent image shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). Vdd is some positive voltage connected to a power supply and Vss is ground. A is the input and Q is the output.

When the voltage of A is low (i.e. close to Vss), the NMOS transistor's channel is in a high resistance state, disconnecting Vss from Q. The PMOS transistor's channel is in a low resistance state, connecting Vdd to Q. Q, therefore, registers Vdd.

On the other hand, when the voltage of A is high (i.e. close to Vdd), the PMOS transistor is in a high resistance state, disconnecting Vdd from Q. The NMOS transistor is in a low resistance state, connecting Vss to Q. Now, Q registers Vss.

In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. No matter what the input is, the output is never left floating (charge is never stored due to wire capacitance and lack of electrical drain/ground). Because of this behavior of input and output, the CMOS circuit's output is the inverse of the input.

The transistors' resistances are never exactly equal to zero or infinity, so Q will never exactly equal Vss or Vdd, but Q will always be closer to Vss than A was to Vdd (or vice versa if A were close to Vss). Without this amplification, there would be a very low limit to the number of logic gates that could be chained together in series, and CMOS logic with billions of transistors would be impossible.

=== Power supply pins ===
{{See also|Engineering:IC power-supply pin}}
The power supply pins for CMOS are called ''V<sub>DD</sub>'' and ''V<sub>SS</sub>'', or ''V<sub>CC</sub>'' and ''ground (GND)'' depending on the manufacturer. ''V<sub>DD</sub>'' and ''V<sub>SS</sub>'' are carryovers from conventional MOS circuits and stand for the ''drain'' and ''source'' supplies.<ref>{{cite web |url=http://www.fairchildsemi.com/an/AN/AN-77.pdf |title=CMOS, the Ideal Logic Family |publisher=Fairchild Semiconductor |date=January 1983 |access-date=2011-11-25 |archive-url=https://web.archive.org/web/20111209004748/http://www.fairchildsemi.com/an/AN/AN-77.pdf |archive-date=2011-12-09 }}</ref> These do not apply directly to CMOS, since both supplies are really source supplies. ''V<sub>CC</sub>'' and ''ground'' are carryovers from TTL logic and that nomenclature has been retained with the introduction of the 54C/74C line of CMOS.

=== Duality ===
An important characteristic of a CMOS circuit is the duality that exists between its PMOS transistors and NMOS transistors. A CMOS circuit is created to allow a path always to exist from the output to either the power source or ground. To accomplish this, the set of all paths to the voltage source must be the [[Complement (set theory)#Logical complement|complement]] of the set of all paths to ground. This can be easily accomplished by defining one in terms of the NOT of the other. Due to the logic based on [[De Morgan's laws]], the PMOS transistors in parallel have corresponding NMOS transistors in series while the PMOS transistors in series have corresponding NMOS transistors in parallel.

=== Logic ===
[[File:CMOS NAND.svg|thumb|upright|[[Engineering:NAND gate|NAND gate]] in CMOS logic.{{Efn|name=Symbols}}]]

More complex logic functions such as those involving [[Engineering:AND gate|AND]] and [[OR gate]]s require manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, both transistors must have low resistance to the corresponding supply voltage, modelling an AND. When a path consists of two transistors in parallel, either one or both of the transistors must have low resistance to connect the supply voltage to the output, modelling an OR.

Shown on the right is a [[Circuit diagram|circuit diagram]] of a [[Engineering:NAND gate|NAND gate]] in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and ''V''<sub>ss</sub> (ground), bringing the output low. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and ''V''<sub>dd</sub> (voltage source), bringing the output high. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and ''V''<sub>dd</sub> (voltage source), bringing the output high. As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a [[Engineering:NAND gate|NAND]] (NOT AND) logic gate.

An advantage of CMOS over NMOS logic is that both low-to-high and high-to-low output transitions are fast since the (PMOS) pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full [[Physics:Voltage|voltage]] between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

See [[Engineering:Logical effort|Logical effort]] for a method of calculating delay in a CMOS circuit.

=== Example: NAND gate in physical layout ===
[[File:CMOS NAND Layout.svg|thumb|upright|The physical layout of a NAND circuit. The larger regions of n-type diffusion and p-type diffusion are part of the transistors. The two smaller regions on the left are taps to prevent latchup. ]]
[[File:CMOS fabrication process.svg|thumb|upright|Simplified process of fabrication of a CMOS inverter on p-type substrate in semiconductor microfabrication. In step 1, [[Chemistry:Silicon dioxide|silicon dioxide]] layers are formed initially through [[Physics:Thermal oxidation|thermal oxidation]] Note: gate, source and drain contacts are not normally in the same plane in real devices, and the diagram is not to scale.]]

This example shows a NAND logic device drawn as a physical representation as it would be manufactured. The physical layout perspective is a "bird's eye view" of a stack of layers. The circuit is constructed on a [[Chemistry:Extrinsic semiconductor#P-type semiconductors|p-type]] substrate. The polysilicon, diffusion, and n-well are referred to as "base layers" and are actually inserted into trenches of the p-type substrate. (See steps 1 to 6 in the process diagram below right) The contacts penetrate an insulating layer between the base layers and the first layer of metal (metal1) making a connection.

The inputs to the [[Engineering:NAND gate|NAND]] (illustrated in green color) are in polysilicon. The transistors (devices) are formed by the intersection of the polysilicon and diffusion; N diffusion for the N device & P diffusion for the P device (illustrated in salmon and yellow coloring respectively). The output ("out") is connected together in metal (illustrated in cyan coloring). Connections between metal and polysilicon or diffusion are made through contacts (illustrated as black squares). The physical layout example matches the NAND logic circuit given in the previous example.

The N device is manufactured on a p-type substrate while the P device is manufactured in an [[Chemistry:Extrinsic semiconductor#N-type semiconductors|n-type]] well (n-well). A p-type substrate "tap" is connected to V<sub>SS</sub> and an n-type n-well tap is connected to V<sub>DD</sub> to prevent latchup.

[[Image:Cmos impurity profile-en.svg|center|thumbnail|500px|Cross section of two transistors in a CMOS gate, in an n-well CMOS process]]

== Power: switching and leakage ==
CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching ("dynamic power"). On a typical [[Engineering:Application-specific integrated circuit|ASIC]] in a modern 90 nanometer process, switching the output might take 120 picoseconds, and happens once every ten nanoseconds. NMOS logic dissipates power whenever the transistor is on, because there is a current path from V<sub>dd</sub> to V<sub>ss</sub> through the load resistor and the n-type network.

Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. Earlier, the power consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area dominated the design parameters. As the CMOS technology moved below sub-micron levels the power consumption per unit area of the chip has risen tremendously.

Broadly classifying, power dissipation in CMOS circuits occurs because of two components, static and dynamic:

=== Static dissipation ===

Both NMOS and PMOS transistors have a gate–source [[Physics:Threshold voltage|threshold voltage]] (V<sub>th</sub>), below which the current (called ''sub threshold'' current) through the device will drop exponentially. Historically, CMOS circuits operated at supply voltages much larger than their threshold voltages (V<sub>dd</sub> might have been 5&nbsp;V, and V<sub>th</sub> for both NMOS and PMOS might have been 700&nbsp;mV). A special type of the transistor used in some CMOS circuits is the [[Engineering:Native transistor|native transistor]], with near zero [[Physics:Threshold voltage|threshold voltage]].

SiO<sub>2</sub> is a good insulator, but at very small thickness levels electrons can tunnel across the very thin insulation; the probability drops off exponentially with oxide thickness. Tunnelling current becomes very important for transistors below 130&nbsp;nm technology with gate oxides of 20&nbsp;Å or thinner.

Small reverse leakage currents are formed due to formation of reverse bias between diffusion regions and wells (for e.g., p-type diffusion vs. n-well), wells and substrate (for e.g., n-well vs. p-substrate). In modern process diode leakage is very small compared to sub threshold and tunnelling currents, so these may be neglected during power calculations.

If the ratios do not match, then there might be different currents of PMOS and NMOS; this may lead to imbalance and thus improper current causes the CMOS to heat up and dissipate power unnecessarily. Furthermore, recent studies have shown that leakage power reduces due to aging effects as a trade-off for devices to become slower.<ref>{{cite book |first1=A.L.H. |last1=Martínez |first2=S. |last2=Khursheed |first3=D. |last3=Rossi |chapter=Leveraging CMOS Aging for Efficient Microelectronics Design |title=2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS) |publisher= |year=2020 |isbn= 978-1-7281-8187-5|pages=1–4 |doi=10.1109/IOLTS50870.2020.9159742|s2cid=225582202 }}</ref>

To speed up designs, manufacturers have switched to constructions that have lower voltage thresholds but because of this a modern NMOS transistor with a V<sub>th</sub> of 200&nbsp;mV has a significant subthreshold leakage current. Designs (e.g. desktop processors) which include vast numbers of circuits which are not actively switching still consume power because of this leakage current. Leakage power is a significant portion of the total power consumed by such designs. [[Multi-threshold CMOS]] (MTCMOS), now available from foundries, is one approach to managing leakage power. With MTCMOS, high V<sub>th</sub> transistors are used when switching speed is not critical, while low V<sub>th</sub> transistors are used in speed sensitive paths. Further technology advances that use even thinner gate dielectrics have an additional [[Engineering:Leakage (electronics)|leakage]] component because of current [[Physics:Quantum tunnelling|tunnelling]] through the extremely thin gate dielectric. Using [[Engineering:High-κ dielectric|high-κ dielectric]]s instead of [[Chemistry:Silicon dioxide|silicon dioxide]] that is the conventional gate dielectric allows similar device performance, but with a thicker gate insulator, thus avoiding this current. Leakage power reduction using new material and system designs is critical to sustaining scaling of CMOS.<ref>A good overview of leakage and reduction methods are explained in the book [https://www.springer.com/engineering/circuits+%26+systems/book/978-0-387-25737-2 Leakage in Nanometer CMOS Technologies] {{webarchive|url=https://web.archive.org/web/20111202012235/http://www.springer.com/engineering/circuits+%26+systems/book/978-0-387-25737-2 |date=2011-12-02 }} {{ISBN|0-387-25737-3}}.</ref>

=== Dynamic dissipation ===

==== Charging and discharging of load capacitances ====
CMOS circuits dissipate power by charging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. In one complete cycle of CMOS logic, current flows from V<sub>DD</sub> to the load capacitance to charge it and then flows from the charged load capacitance (C<sub>L</sub>) to ground during discharge. Therefore, in one complete charge/discharge cycle, a total of Q=C<sub>L</sub>V<sub>DD</sub> is thus transferred from V<sub>DD</sub> to ground. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by the average voltage again to get the characteristic switching power dissipated by a CMOS device: <math> P = 0.5 C V^2 f </math>.

Since most gates do not operate/switch at every [[Clock signal|clock cycle]], they are often accompanied by a factor <math>\alpha</math>, called the activity factor. Now, the dynamic power dissipation may be re-written as <math> P = \alpha C V^2 f </math>.

A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data has an activity factor of 0.1.<ref>{{cite journal |first1=Konstantin |last1=Moiseev |first2=Avinoam |last2=Kolodny |first3=Shmuel |last3=Wimer |title=Timing-aware power-optimal ordering of signals |journal=ACM Trans. Des. Autom. Electron. Syst. |volume=13 |issue=4 |at=Article 65 |date=September 2008 |doi=10.1145/1391962.1391973 |citeseerx=10.1.1.222.9211|s2cid=18895687 }}</ref> If correct load capacitance is estimated on a node together with its activity factor, the dynamic power dissipation at that node can be calculated effectively.

==== Short-circuit power ====
Since there is a finite rise/fall time for both pMOS and nMOS, during transition, for example, from off to on, both the transistors will be on for a small period of time in which current will find a path directly from V<sub>DD</sub> to ground, hence creating a short-circuit current, sometimes called a ''crowbar'' current. Short-circuit power dissipation increases with the rise and fall time of the transistors.

This form of power consumption became significant in the 1990s as wires on chip became narrower and the long wires became more resistive. CMOS gates at the end of those resistive wires see slow input transitions. Careful design which avoids weakly driven long skinny wires reduces this effect, but crowbar power can be a substantial part of dynamic CMOS power.

== Input protection ==
Parasitic transistors that are inherent in the CMOS structure may be turned on by input signals outside the normal operating range, e.g. [[Physics:Electrostatic discharge|electrostatic discharge]]s or [[Engineering:Reflections of signals on conducting lines|line reflections]]. The resulting [[Engineering:Latch-up|latch-up]] may damage or destroy the CMOS device. Clamp diodes are included in CMOS circuits to deal with these signals. Manufacturers' data sheets specify the maximum permitted current that may flow through the diodes.

== Analog CMOS ==
{{See|CMOS amplifier|Mixed-signal integrated circuit}}


=== RF CMOS ===
{{Main|Engineering:RF CMOS}}

RF CMOS refers to RF circuits ([[Engineering:Radio frequency|radio frequency]] circuits) which are based on [[Engineering:Mixed-signal integrated circuit|mixed-signal]] [[Engineering:MOS integrated circuit|CMOS integrated circuit]] technology. They are widely used in wireless telecommunication technology. RF CMOS was developed by Asad Abidi while working at UCLA in the late 1980s. This changed the way in which RF circuits were designed, leading to the replacement of discrete bipolar transistors with CMOS integrated circuits in [[Social:Radio|radio]] transceivers.<ref name="O'Neill">{{cite journal |last1=O'Neill |first1=A. |title=Asad Abidi Recognized for Work in RF-CMOS |journal=IEEE Solid-State Circuits Society Newsletter |date=2008 |volume=13 |issue=1 |pages=57–58 |doi=10.1109/N-SSC.2008.4785694 |issn=1098-4232}}</ref> It enabled sophisticated, low-cost and portable end-user terminals, and gave rise to small, low-cost, low-power and portable units for a wide range of wireless communication systems. This enabled "anytime, anywhere" communication and helped bring about the wireless revolution, leading to the rapid growth of the wireless industry.<ref>{{cite journal |last1=Daneshrad |first1=Babal |last2=Eltawil |first2=Ahmed M. |title=Integrated Circuit Technologies for Wireless Communications |journal=Wireless Multimedia Network Technologies |volume=524 |date=2002 |pages=227–244 |doi=10.1007/0-306-47330-5_13 |isbn=0-7923-8633-7 |publisher=Springer US|series=The International Series in Engineering and Computer Science }}</ref>

The [[Engineering:Baseband processor|baseband processor]]s<ref>{{cite book |last1=Chen |first1=Wai-Kai |title=The VLSI Handbook |date=2018 |publisher=CRC Press |isbn=978-1-4200-0596-7 |pages=60–2 |url=https://books.google.com/books?id=rMsqBgAAQBAJ&pg=SA60-PA2}}</ref><ref>{{cite book |last1=Morgado |first1=Alonso |last2=Río |first2=Rocío del |last3=Rosa |first3=José M. de la |title=Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio |date=2011 |publisher=Springer |isbn=978-1-4614-0037-0 |page=1 |url=https://books.google.com/books?id=Alv6nWVCkDIC&pg=PA1}}</ref> and radio transceivers in all modern wireless networking devices and mobile phones are mass-produced using RF CMOS devices.<ref name="O'Neill"/> RF CMOS circuits are widely used to transmit and receive wireless signals, in a variety of applications, such as [[Astronomy:Satellite|satellite]] technology (such as [[Engineering:GPS|GPS]]), [[Bluetooth]], [[Wi-Fi]], [[Near-field communication|near-field communication]] (NFC), mobile networks (such as [[3G|3G]] and [[4G|4G]]), [[Engineering:Terrestrial television|terrestrial]] broadcast, and [[Engineering:Automotive electronics|automotive]] [[Engineering:Radar|radar]] applications, among other uses.<ref>{{cite book |last1=Veendrick |first1=Harry J. M. |title=Nanometer CMOS ICs: From Basics to ASICs |date=2017 |publisher=Springer |isbn=978-3-319-47597-4 |page=243 |url=https://books.google.com/books?id=Lv_EDgAAQBAJ&pg=PA243}}</ref>

Examples of commercial RF CMOS chips include Intel's [[Digital Enhanced Cordless Telecommunications|DECT]] cordless phone, and 802.11 ([[Wi-Fi]]) chips created by [[Company:Atheros|Atheros]] and other companies.<ref name="IEEE-CMOS-dualband-n">{{cite web|last1=Nathawad|first1=L.|last2=Zargari|first2=M.|last3=Samavati|first3=H.|last4=Mehta|first4=S.|last5=Kheirkhaki|first5=A.|last6=Chen|first6=P.|last7=Gong|first7=K.|last8=Vakili-Amini|first8=B.|last9=Hwang|first9=J.|last10=Chen|first10=M.|last11=Terrovitis|first11=M.|last12=Kaczynski|first12=B.|last13=Limotyrakis|first13=S.|last14=Mack|first14=M.|last15=Gan|first15=H.|last16=Lee|first16=M.|last17=Abdollahi-Alibeik|first17=B.|last18=Baytekin|first18=B.|last19=Onodera|first19=K.|last20=Mendis|first20=S.|last21=Chang|first21=A.|last22=Jen|first22=S.|last23=Su|first23=D.|last24=Wooley|first24=B.|title=20.2: A Dual-band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN|url=http://www.ewh.ieee.org/r6/scv/ssc/May2008_WLAN.pdf|website=IEEE Entity Web Hosting|publisher=IEEE|access-date=22 October 2016|archive-date=23 October 2016|archive-url=https://web.archive.org/web/20161023053607/http://www.ewh.ieee.org/r6/scv/ssc/May2008_WLAN.pdf}}</ref> Commercial RF CMOS products are also used for [[Bluetooth]] and [[Wireless LAN|wireless LAN]] (WLAN) networks.<ref>{{cite journal |title=Abidi Receives IEEE Pederson Award at ISSCC 2008 |journal= IEEE Solid-State Circuits Society Newsletter|date=Spring 2008 |volume=13 |issue=2 |page=12 |doi=10.1109/N-SSC.2008.4785734 |last1=Olstein |first1=Katherine |s2cid=30558989 }}</ref> RF CMOS is also used in the radio transceivers for wireless standards such as GSM, Wi-Fi, and Bluetooth, transceivers for mobile networks such as 3G, and remote units in [[Wireless sensor network|wireless sensor network]]s (WSN).<ref>{{cite book |last1=Oliveira |first1=Joao |last2=Goes |first2=João |title=Parametric Analog Signal Amplification Applied to Nanoscale CMOS Technologies |date=2012 |publisher=Springer |isbn=978-1-4614-1670-8 |page=7 |url=https://books.google.com/books?id=Ahl_OuKxsToC&pg=PR7}}</ref>

RF CMOS technology is crucial to modern wireless communications, including wireless networks and mobile communication devices. One of the companies that commercialized RF CMOS technology was Infineon. Its bulk CMOS RF switches sell over 1{{nbsp}}billion units annually, reaching a cumulative 5{{nbsp}}billion units, {{as of|2018|lc=y}}.<ref>{{cite news |title=Infineon Hits Bulk-CMOS RF Switch Milestone |url=https://www.eetasia.com/news/article/18112004-infineon-hits-bulk-cmos-rf-switch-milestone |access-date=26 October 2019 |work=EE Times |date=20 November 2018 |language=en-PH}}</ref>

== Temperature range ==
Conventional CMOS devices work over a range of −55&nbsp;°C to +125&nbsp;°C.

There were theoretical indications as early as August 2008 that silicon CMOS will work down to −233&nbsp;°C (40&nbsp;[[Kelvin|K]]).<ref>Edwards C., "Temperature control", ''Engineering & Technology'' 26 July{{snd}} 8 August 2008, [[Organization:Institution of Engineering and Technology|IET]].</ref> Functioning temperatures near 40&nbsp;K have since been achieved using overclocked AMD [[Engineering:Phenom II|Phenom II]] processors with a combination of [[Chemistry:Liquid nitrogen|liquid nitrogen]] and [[Chemistry:Liquid helium|liquid helium]] cooling.<ref>{{cite web |url=http://blogs.amd.com/home/2009/01/15/breaking-records-with-dragons-and-helium-in-the-las-vegas-desert/ |title=Breaking Records with Dragons and Helium in the Las Vegas Desert |first=Patrick |last=Moorhead |publisher=blogs.amd.com/patmoorhead |date=January 15, 2009 |access-date=2009-09-18 |archive-url=https://web.archive.org/web/20100915140806/http://blogs.amd.com/home/2009/01/15/breaking-records-with-dragons-and-helium-in-the-las-vegas-desert/ |archive-date=September 15, 2010 }}</ref>

[[Chemistry:Silicon carbide|Silicon carbide]] CMOS devices have been tested for a year at 500&nbsp;°C.<ref>{{cite journal |last1=Clark |first1=D.T. |last2=Ramsay |first2=E.P. |last3=Murphy |first3=A.E. |last4=Smith |first4=D.A. |last5=Thompson |first5=Robin.F. |last6=Young |first6=R.A.R. |last7=Cormack |first7=J.D. |last8=Zhu |first8=C. |last9=Finney |first9=S. |last10=Fletcher |first10=J. |title=High Temperature Silicon Carbide CMOS Integrated Circuits |journal=Materials Science Forum |volume=679–680 |pages=726–729 |year=2011 |doi=10.4028/www.scientific.net/msf.679-680.726 |s2cid=110071501 }}</ref><ref>{{cite web |first1=Alan |last1=Mantooth |first2=Carl-Mikael |last2=Zetterling |first3=Ana |last3=Rusu  |title=The Radio We Could Send to Hell: Silicon carbide radio circuits can take the volcanic heat of Venus |date=28 April 2021 |work=IEEE Spectrum |publisher= |url=https://spectrum.ieee.org/the-radio-we-could-send-to-hell}}</ref>

== Single-electron MOS transistors ==
Ultra small (L = 20&nbsp;nm, W = 20&nbsp;nm) MOSFETs achieve the single-electron limit when operated at cryogenic temperature over a range of −269&nbsp;°C (4&nbsp;[[Kelvin|K]]) to about −258&nbsp;°C (15&nbsp;[[Kelvin|K]]). The transistor displays [[Physics:Coulomb blockade|Coulomb blockade]] due to progressive charging of electrons one by one. The number of electrons confined in the channel is driven by the gate voltage, starting from an occupation of zero electrons, and it can be set to one or many.<ref>{{Cite journal |last1=Prati |first1=E. |last2=De Michielis |first2=M. |last3=Belli |first3=M. |last4=Cocco |first4=S. |last5=Fanciulli |first5=M. |last6=Kotekar-Patil |first6=D. |last7=Ruoff |first7=M. |last8=Kern |first8=D. P. |last9=Wharam |first9=D. A. |last10=Verduijn |doi=10.1088/0957-4484/23/21/215204 |first10=J. |last11=Tettamanzi |first11=G. C. |last12=Rogge |first12=S. |last13=Roche |first13=B. |last14=Wacquez |first14=R. |last15=Jehl |first15=X. |last16=Vinet |first16=M. |last17=Sanquer |first17=M. |title=Few electron limit of n-type metal oxide semiconductor single electron transistors |journal=Nanotechnology |volume=23 |issue=21 |article-number=215204 |year=2012 |pmid=22552118 |arxiv=1203.4811 |bibcode=2012Nanot..23u5204P |s2cid=206063658 }}</ref>

== See also ==
* {{annotated link|Engineering:Beyond CMOS}}
* {{annotated link|Physics:Gate equivalent}}
* {{annotated link|Engineering:HCMOS}}
* {{annotated link|LVCMOS}}
* {{annotated link|Engineering:SCMOS}}

== Notes ==
{{Notes}}

== References ==
{{reflist|30em}}

== Further reading ==
* {{cite journal |first1=S.J. |last1=Bader |first2=H. |last2=Lee |first3=R. |last3=Chaudhuri |first4=S. |last4=Huang |first5=A. |last5=Hickman |first6=A. |last6=Molnar |first7=H.G. |last7=Xing |first8=D. |last8=Jena |first9=H. |last9=W. Then |first10=N. |last10=Chowdhury |first11=T. |last11=Palacios |title=Prospects for Wide Bandgap and Ultrawide Bandgap CMOS Devices |journal=IEEE Transactions on Electron Devices |volume=67 |issue=10 |pages=4010–20 |date=October 2020 |doi=10.1109/TED.2020.3010471 |bibcode=2020ITED...67.4010B |s2cid=221913316 |url=https://djena.engineering.cornell.edu/papers/2020/ted20_sam_uwbg_review.pdf}}
* {{cite book |last=Baker |first=R. Jacob |title=CMOS: Circuit Design, Layout, and Simulation |edition=3rd |url=http://CMOSedu.com |publisher=Wiley-IEEE |year=2010 |isbn=978-0-470-88132-3 }} 
* {{cite book |last1=Mead |first1=Carver A. |last2=Conway |first2=Lynn |title=Introduction to VLSI systems |publisher=Addison-Wesley |year=1980 |isbn=0-201-04358-0 |url-access=registration |url=https://archive.org/details/introductiontovl00mead }}
* {{cite book |last=Veendrick |first=H.J.M. |title=Nanometer CMOS ICs: From Basics to ASICs |year=2025 |publisher=Springer |doi=10.1007/978-3-031-64249-4 |url=https://link.springer.com/book/10.1007/978-3-031-64249-4 |isbn=978-3-031-64248-7}} 
* {{cite book |last1=Weste |first1=Neil H. E. |last2=Harris |first2=David M. |title=CMOS VLSI Design: A Circuits and Systems Perspective |edition=4th |url=http://CMOSVLSI.com/ |publisher=Pearson/Addison-Wesley |year=2010 |isbn=978-0-321-54774-3 }}

== External links ==
* [https://web.archive.org/web/20110719014039/http://tams-www.informatik.uni-hamburg.de/applets/cmos/ CMOS gate description and interactive illustrations]

{{Logic Families|state=expanded}}
{{Electronic components}}

[[Category:Electronic design]]
[[Category:Digital electronics]]
[[Category:Logic families]]
[[Category:Integrated circuits]]

{{Sourceattribution|CMOS}}