View source for Engineering:Gracemont (microarchitecture)

{{Short description|CPU microarchitecture by Intel}}
{{Infobox CPU
| name           = Gracemont
| image          = GracemontRevised.png
| produced-start = {{Start date and age|2021|11|04}}<ref>{{Cite web |last=Cutress |first=Ian |date=October 27, 2021 |title=Intel 12th Gen Core Alder Lake for Desktops: Top SKUs Only, Coming November 4th |url=https://www.anandtech.com/show/16959/intel-innovation-alder-lake-november-4th |website=AnandTech |language=en-US |access-date=September 14, 2022}}</ref>
| soldby         = [[Company:Intel|Intel]]
| designfirm     = [[Company:Intel|Intel]]
| manuf1         = [[Company:Intel|Intel]]
| model          =
| code           =
| created        =
| pcode1         = [[Engineering:Alder Lake|Alder Lake]] <small>(client)</small>
| pcode2         = [[Engineering:Raptor Lake|Raptor Lake]] <small>(client)</small>
| pcode3         =
| cores          = 4 per module
| transistors    = 
| slowest        = 0.7
| slow-unit      = GHz
| fastest        = 4.3
| fast-unit      = GHz
| l1cache        = 96{{nbsp}}KB per core: <br/> {{bulleted list|64{{nbsp}}KB instructions |32{{nbsp}}KB data}}
| l2cache        = 2 or 4{{nbsp}}MB per module
| l3cache        = 3{{nbsp}}MB per module
| llcache        = 
| dmi            = 
| gpu            = 
| arch           = [[X86-64|x86-64]]
| extensions     = [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4]], SSE4.1, SSE4.2, [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions#Advanced Vector Extensions 2|AVX2]], FMA3, [[Advanced Vector Extensions#AVX-VNNI|AVX-VNNI]], [[AES instruction set|AES-NI]], CLMUL, [[RDRAND]], [[Intel SHA extensions|SHA]], [[Engineering:Trusted Execution Technology|TXT]], VT-d, VT-x
| socket         = 
| predecessor    = [[Engineering:Tremont (microarchitecture)|Tremont]]
| successor      = Crestmont
}}

'''Gracemont''' is a [[Microarchitecture|microarchitecture]] for low-power processors used in [[System on a chip|systems on a chip]] (SoCs) made by [[Company:Intel|Intel]], and is the successor to [[Engineering:Tremont (microarchitecture)|Tremont]]. Like its predecessor, it is also implemented as low-power cores in a hybrid design of the [[Engineering:Alder Lake|Alder Lake]], [[Engineering:Raptor Lake|Raptor Lake]] and Raptor Lake Refresh processors.<ref>{{cite web |last1=Cutress |first1=Ian |date=August 14, 2020 |title=Intel Alder Lake: Confirmed x86 Hybrid with Golden Cove and Gracemont for 2021 |url=https://www.anandtech.com/show/15979/intel-alder-lake-confirmed-x86-hybrid-with-golden-cove-and-gracemont-for-2021 |website=AnandTech |access-date=September 14, 2022}}</ref>

== Design ==
Gracemont is the fourth generation [[Out-of-order execution|out-of-order]] low-power [[Engineering:Atom (system on chip)|Atom]] microarchitecture, built on the Intel 7 manufacturing process.<ref name="anandtech-deep-dive-into-alder-lake">{{Cite web |last1=Cutress |first1=Ian |last2=Frumusanu |first2=Andrei |date=August 19, 2021 |title=Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed |url=https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures |website=AnandTech |language=en-US |access-date=August 31, 2022}}</ref>

The Gracemont microarchitecture has the following enhancements over [[Engineering:Tremont (microarchitecture)|Tremont]]:<ref name=wikichip>{{cite web |title=Gracemont – Microarchitectures – Intel |url=https://en.wikichip.org/wiki/intel/microarchitectures/gracemont |website=WikiChip |language=en-US |access-date=September 14, 2022}}</ref><ref name="anandtech-deep-dive-into-alder-lake">{{Cite web |last1=Cutress |first1=Ian |last2=Frumusanu |first2=Andrei |date=August 19, 2021 |title=Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed |url=https://www.anandtech.com/show/16881/a-deep-dive-into-intels-alder-lake-microarchitectures |website=AnandTech |language=en-US |access-date=August 31, 2022}}</ref>

* Level 1 cache per core:
** eight-way-associative 64{{nbsp}}KB instruction cache  
** eight-way-associative 32{{nbsp}}KB data cache
* New On-Demand Instruction Length Decoder
* Instruction issue increased to five per clock (from four)
* Instruction retire increased to eight per clock (from seven)
* Execution ports (functional units) there are now 17 (from eight)
* Reorder buffer increased to 256 entries (from 208)
* Improved branch prediction
* Support for [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions#Advanced Vector Extensions 2|AVX2]], FMA3 and [[Advanced Vector Extensions#AVX-VNNI|AVX-VNNI]] instructions<ref name="tomshardware_1">{{cite web |last1=Shilov |first1=Anton |date=October 7, 2020 |title=Intel's Upcoming Gracemont Microarchitecture to Support AVX, AVX2, and AVX-VNNI |url=https://www.tomshardware.com/news/intels-upcoming-gracemont-microarchitecture-to-support-avx-avx2-and-avx-vnni |website=Tom's Hardware |access-date=September 14, 2022}}</ref>

== Technology ==
* [[System on a chip]] (SoC) architecture
* 3D tri-gate transistors
* 64{{nbsp}}KB L1 instruction cache, up from 32&nbsp;KB in [[Engineering:Tremont (microarchitecture)|Tremont]]<ref name="anandtech-deep-dive-into-alder-lake"/>
* 2 or 4{{nbsp}}MB shared L2 cache per 4-core cluster<ref name="anandtech-deep-dive-into-alder-lake"/> Alder Lake-S/H/P/U family has 2{{nbsp}}MB.  Raptor Lake-S/H/P/U family has 4{{nbsp}}MB.
* [[Intel Xe]] (Gen. 12.2) GPU with DirectX 12, [[Software:OpenGL|OpenGL 4.6]], [[Software:Vulkan (API)|Vulkan 1.3]], OpenGL ES 3.2 and [[OpenCL|OpenCL 3.0]] support.<ref>{{cite web |title=Intel® Processor Graphics Xᵉ-LP API Developer and Optimization Guide |url=https://www.intel.com/content/www/us/en/developer/articles/guide/lp-api-developer-optimization-guide.html |website=Intel |language=en-US |access-date=September 14, 2022}}</ref>
* [[Thermal design power]] (TDP)
** 10{{nbsp}}W desktop processors
** 6{{nbsp}}W mobile processors

== List of Gracemont processors ==
{{Main|Engineering:Alder Lake|Engineering:Raptor Lake}}
The microarchitecture is used as the efficient cores of the 12th generation of Intel Core hybrid processors (codenamed "Alder Lake"), the 13th generation of Intel Core hybrid processors (codenamed "Raptor Lake") and the 14th generation of Intel Core hybrid processors (codenamed "Raptor Lake Refresh"). It's used exclusively in the [[Engineering:Alder Lake#Alder Lake-N|Alder Lake-N]] line-up.

=== Alder Lake-N ===
{| class="wikitable sortable" style="text-align:center"
! rowspan="3" | Branding
! rowspan="3" | Model
! rowspan="3" | Cores <br/> (threads)
! colspan="2" | [[Clock rate]] (GHz)
! colspan="4" | [[Engineering:Intel Graphics Technology|GPU]]
! colspan="2" | [[CPU cache|Cache]]
! colspan="2" | [[Thermal design power|TDP]]
! rowspan="3" | Release date
! rowspan="3" | Price <br> (USD){{efn|name="RCP"}}
|-
! rowspan="2" | Base
! rowspan="2" | Turbo
! rowspan="2" | Model
! rowspan="2" | {{abbr|EUs|Execution Units}}
! colspan="2" | Clock rate <br> (GHz)
! rowspan="2" | L2
! rowspan="2" | L3
! rowspan="2" | Base
! rowspan="2" | cTDP <br>Down
|-
! Base
! Turbo
|-
| rowspan="2" | Core <br> i3
| rowspan="1" | [https://ark.intel.com/content/www/us/en/ark/products/231805/intel-core-i3n305-processor-6m-cache-up-to-3-80-ghz.html N305]
| rowspan="2" | 8 (8)
| 1.8
| rowspan="2" | 3.8
| rowspan="10" | [[Engineering:Intel Graphics Technology|UHD <br> Graphics]]
| rowspan="3" | 32
| rowspan="4" {{dunno}}
| rowspan="2" | 1.25
| rowspan="10" | 2{{nbsp}}MB
| rowspan="10" | 6{{nbsp}}MB
| 15{{nbsp}}W
| 9{{nbsp}}W
| rowspan="10" | {{dts|2023|January|03|format=mdy|abbr=on}}
| rowspan="2" | $309
|-
| [https://ark.intel.com/content/www/us/en/ark/products/231806/intel-core-i3n300-processor-6m-cache-up-to-3-80-ghz.html N300]
| 1.1
| 7{{nbsp}}W
| rowspan="9" {{NA}}
|-
| rowspan="5" | Intel <br> Processor
| [https://ark.intel.com/content/www/us/en/ark/products/231804/intel-processor-n200-6m-cache-up-to-3-70-ghz.html N200]
| rowspan="4" | 4 (4)
| 1.8
| 3.7
| rowspan="2" | 0.75
| rowspan="2" | 6{{nbsp}}W
| $193
|-
| [https://ark.intel.com/content/www/us/en/ark/products/231803/intel-processor-n100-6m-cache-up-to-3-40-ghz.html N100]
| 1.8
| 3.4
| rowspan="2" | 24
| $128
|-
| [https://ark.intel.com/content/www/us/en/ark/products/233090/intel-processor-n97-6m-cache-up-to-3-60-ghz.html N97]
| 2.0
| 3.6
| 0.85
| rowspan="2" | 1.2
| 12{{nbsp}}W
| $128
|-
| [https://ark.intel.com/content/www/us/en/ark/products/231800/intel-processor-n95-6m-cache-up-to-3-40-ghz.html N95]
| 1.7
| 3.4
| rowspan="2" | 16
| {{dunno}}
| 15{{nbsp}}W
| {{dunno}}
|-
| [https://ark.intel.com/content/www/us/en/ark/products/233089/intel-processor-n50-6m-cache-up-to-3-40-ghz.html N50]
| 2 (2)
| 1.0
| rowspan="2" | 3.4
| 0.6
| 0.75
| 6{{nbsp}}W
| $128
|-
| rowspan="3" | Atom
|[https://ark.intel.com/content/www/us/en/ark/products/233093/intel-atom-x7425e-6m-cache-up-to-3-40-ghz.html x7425E]
| 4 (4)
| 1.5
| 24
| rowspan="2" | 0.8
| rowspan="3" | 1.0
| 12{{nbsp}}W
| $58
|-
| [https://ark.intel.com/content/www/us/en/ark/products/233091/intel-atom-x7213e-6m-cache-up-to-3-20-ghz.html x7213E]
| rowspan="2" | 2 (2)
| 1.7
| rowspan="2" | 3.2
| rowspan="2" | 16
| 10{{nbsp}}W
| $47
|-
| [https://ark.intel.com/content/www/us/en/ark/products/233092/intel-atom-x7211e-6m-cache-up-to-3-20-ghz.html x7211E]
| 1.0
| 0.6
| 6{{nbsp}}W
| $39
|-
|}
{{Notelist|refs=
{{efn|name="RCP"|Price is Recommended Customer Price (RCP) at launch. RCP is the trade price that processors are sold by Intel to retailers and OEMs. Actual MSRP for consumers is higher}}<!-- There needs to be a disclaimer that price is not reflective of MSRP unlike AMD and Nvidia CPU and GPU tables which give official MSRP -->
}}
{{reflist|group="note"}}

==See also==
* [[Engineering:List of Intel CPU microarchitectures|List of Intel CPU microarchitectures]]

==References==
{{Reflist|30em}}

{{Intel processors|silvermont}}
{{IntelProcessorRoadmap}}

[[Category:Intel x86 microprocessors]]
[[Category:Intel microarchitectures]]

{{Sourceattribution|Gracemont (microarchitecture)}}