View source for Engineering:Heterogeneous System Architecture

'''Heterogeneous System Architecture''' ('''HSA''') is a cross-vendor set of specifications that allow for the integration of [[Central processing unit|central processing unit]]s and graphics processors on the same bus, with shared memory and [[Task (computing)|tasks]].<ref>{{cite web |url=http://www.tomshardware.com/news/AMD-HSA-hUMA-APU,22324.html |title=AMD Unveils its Heterogeneous Uniform Memory Access (hUMA) Technology |website=Tom's Hardware |author=Tarun Iyer |date=30 April 2013}}</ref> The HSA is being developed by the [[Organization:HSA Foundation|HSA Foundation]], which includes (among many others) [[Company:Advanced Micro Devices|AMD]] and [[Engineering:ARM Holdings|ARM]]. The platform's stated aim is to reduce communication latency between CPUs, GPUs and other compute devices, and make these various devices more compatible from a programmer's perspective,<ref name="whitepaper">{{Cite report |author=George Kyriazis |date=30 August 2012 |title=Heterogeneous System Architecture: A Technical Review |url=http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/hsa10.pdf |publisher=AMD |access-date=26 May 2014 |archive-url=https://web.archive.org/web/20140328140823/http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/hsa10.pdf |archive-date=28 March 2014 |url-status=dead }}</ref>{{rp|3}}<ref name="whatis">{{cite web |title=What is Heterogeneous System Architecture (HSA)? |url=http://developer.amd.com/resources/heterogeneous-computing/what-is-heterogeneous-system-architecture-hsa/ |publisher=AMD |access-date=23 May 2014 |archive-url=https://web.archive.org/web/20140621213832/http://developer.amd.com/resources/heterogeneous-computing/what-is-heterogeneous-system-architecture-hsa/ |archive-date=21 June 2014 |url-status=dead }}</ref> relieving the programmer of the task of planning the moving of data between devices' disjoint memories (as must currently be done with [[OpenCL]] or [[Software:CUDA|CUDA]]).<ref>{{cite web |author=Joel Hruska |title=Setting HSAIL: AMD explains the future of CPU/GPU cooperation |url=http://www.extremetech.com/gaming/164817-setting-hsail-amd-cpu-gpu-cooperation |website=[[ExtremeTech]] |publisher=Ziff Davis |date=2013-08-26}}</ref>
CUDA and OpenCL as well as most other fairly advanced programming languages can use HSA to increase their execution performance.<ref>{{cite web|url=http://www.slideshare.net/mobile/linaroorg/hsa-linaro-updatejuly102013|title=LCE13: Heterogeneous System Architecture (HSA) on ARM|author=Linaro|work=slideshare.net|date=21 March 2014}}</ref>  Heterogeneous computing is widely used in system-on-chip devices such as [[Engineering:Tablet computer|tablets]], [[Engineering:Smartphone|smartphone]]s, other mobile devices, and [[Engineering:Video game console|video game console]]s.<ref name="gpuscience">{{cite web
 | url = http://gpuscience.com/cs/heterogeneous-system-architecture-purpose-and-outlook/
 | archive-url = https://web.archive.org/web/20140201183411/http://gpuscience.com/cs/heterogeneous-system-architecture-purpose-and-outlook/
 | title = Heterogeneous System Architecture: Purpose and Outlook
 | date = 2012-11-09 | access-date = 2014-05-24
 | archive-date = 2014-02-01
 | website = gpuscience.com
}}</ref> HSA allows programs to use the graphics processor for floating point calculations without separate memory or scheduling.<ref>{{cite web |title=Heterogeneous system architecture: Multicore image processing using a mix of CPU and GPU elements |website=Embedded Computing Design |url=http://embedded-computing.com/articles/heterogeneous-processing-using-mix-cpu-gpu-elements/ |access-date=23 May 2014}}</ref>

==Rationale==
The rationale behind HSA is to ease the burden on programmers when offloading calculations to the GPU. Originally driven solely by AMD and called the FSA, the idea was extended to encompass processing units other than GPUs, such as other manufacturers' [[Engineering:Digital signal processor|DSPs]], as well.

{{Gallery
 | width  = 320
 | height = 190
 | align  = center
 | File:HSA – using the GPU without HSA.svg
   | Steps performed when offloading calculations to the [[Graphics processing unit|GPU]] on a non-HSA system

 |File:HSA – using the GPU with HSA.svg
   | Steps performed when offloading calculations to the GPU on a HSA system, using the HSA functionality
}}

Modern GPUs are very well suited to perform [[Single instruction, multiple data|single instruction, multiple data]] (SIMD) and [[Single instruction, multiple threads|single instruction, multiple threads]] (SIMT), while modern CPUs are still being optimized for branching. etc.

==Overview==
Originally introduced by [[Embedded system|embedded system]]s such as the Cell Broadband Engine, sharing system memory directly between multiple system actors makes heterogeneous computing more mainstream. Heterogeneous computing itself refers to systems that contain multiple processing units{{snd}} [[Central processing unit|central processing unit]]s (CPUs), [[Graphics processing unit|graphics processing unit]]s (GPUs), [[Engineering:Digital signal processor|digital signal processor]]s (DSPs), or any type of [[Engineering:Application-specific integrated circuit|application-specific integrated circuit]]s (ASICs). The system architecture allows any accelerator, for instance a graphics processor, to operate at the same processing level as the system's CPU.

Among its main features, HSA defines a unified [[Virtual address space|virtual address space]] for compute devices: where GPUs traditionally have their own memory, separate from the main (CPU) memory, HSA requires these devices to share [[Page (computer memory)|page tables]] so that devices can exchange data by sharing [[Pointer (computer programming)|pointers]]. This is to be supported by custom [[Memory management unit|memory management unit]]s.<ref name="whitepaper"/>{{rp|6–7}}  To render interoperability possible and also to ease various aspects of programming, HSA is intended to be ISA-agnostic for both CPUs and accelerators, and to support high-level programming languages.

So far, the HSA specifications cover:

===HSA Intermediate Layer===<!--incoming redirect-->
HSAIL (Heterogeneous System Architecture Intermediate Language), a [[P-code machine|virtual instruction set]] for parallel programs
* similar to LLVM Intermediate Representation and [[Software:Standard Portable Intermediate Representation|SPIR]] (used by [[OpenCL]] and [[Software:Vulkan (API)|Vulkan]])
* finalized to a specific instruction set by a [[Just-in-time compilation|JIT compiler]]
* make late decisions on which core(s) should run a task
* explicitly parallel
* supports exceptions, virtual functions and other high-level features
* debugging support

===HSA memory model===
* compatible with [[C++11]], OpenCL, [[Java (programming language)|Java]] and .NET memory models
* relaxed consistency
* designed to support both managed languages (e.g. Java) and unmanaged languages (e.g. [[C (programming language)|C]])
* will make it much easier to develop 3rd-party compilers for a wide range of heterogeneous products programmed in [[Fortran]], C++, [[Software:C++ AMP|C++ AMP]], Java, et al.

===HSA dispatcher and run-time===
* designed to enable heterogeneous task queueing: a work queue per core, distribution of work into queues, load balancing by work stealing
* any core can schedule work for any other, including itself
* significant reduction of overhead of scheduling work for a core

Mobile devices are one of the HSA's application areas, in which it yields improved power efficiency.<ref name="gpuscience" />

===Block diagrams===
The illustrations below compare CPU-GPU coordination under HSA versus under traditional architectures.

{{Gallery
 | width  = 320
 | height = 190
 | align  = center
 | File:Desktop computer bus bandwidths.svg
   | Standard architecture with a discrete [[Engineering:Graphics card|GPU]] attached to the [[Engineering:PCI Express|PCI Express]] bus. [[Zero-copy]] between the GPU and CPU is not possible due to distinct physical memories.

 |File:HSA-enabled virtual memory with distinct graphics card.svg
   | HSA brings unified virtual memory and facilitates passing pointers over PCI Express instead of copying the entire data.

 | File:Integrated graphics with distinct memory allocation.svg
   | In partitioned main memory, one part of the system memory is exclusively allocated to the GPU.  As a result, zero-copy operation is not possible.

 | File:HSA-enabled integrated graphics.svg
   | Unified main memory, where GPU and CPU are HSA-enabled.  This makes zero-copy operation possible.<ref>{{cite web |url=http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/ |title=Kaveri microarchitecture |date=2014-01-15 |work=SemiAccurate}}</ref>

 | File:MMU and IOMMU.svg
   | The CPU's [[Memory management unit|MMU]] and the GPU's IOMMU must both comply with HSA hardware specifications.
}}

{{Clear}}

==Software support{{Anchor|AMDKFD|HQ|HMM}}==
[[File:Linux AMD graphics stack.svg|thumb|upright=1.8|AMD GPUs contain certain additional functional units intended to be used as part of HSA.  In Linux, kernel driver {{Mono|amdkfd}} provides required support.<ref>{{cite web
 | url = https://www.phoronix.com/scan.php?page=news_item&px=MTc0NTk
 | title = AMDKFD Driver Still Evolving For Open-Source HSA On Linux
 | date = 21 July 2014 | access-date = 21 January 2015
 | author = Michael Larabel | publisher = Phoronix
}}</ref><ref name="kernelnewbies-3.19" />]]

Some of the HSA-specific features implemented in the hardware need to be supported by the operating system kernel and specific device drivers.  For example, support for AMD [[Engineering:Radeon|Radeon]] and [[Engineering:AMD FirePro|AMD FirePro]] graphics cards, and [[Engineering:AMD Accelerated Processing Unit|APUs]] based on [[Graphics Core Next]] (GCN), was merged into version 3.19 of the Linux kernel mainline, released on 8 February 2015.<ref name="kernelnewbies-3.19">{{cite web
 | url = http://kernelnewbies.org/Linux_3.19#head-ae54e026ef7588f4431f7e94178d27d5cd830bbf
 | title = Linux kernel 3.19, Section 1.3. HSA driver for AMD GPU devices
 | date = 8 February 2015 | access-date = 12 February 2015
 | website = kernelnewbies.org
}}</ref>  Programs do not interact directly with {{Mono|amdkfd}}{{Explain|date=December 2023}}, but queue their jobs utilizing the HSA runtime.<ref>{{cite web
 | url = https://github.com/HSAFoundation/HSA-Runtime-Reference-Source/blob/master/README.md
 | title = HSA-Runtime-Reference-Source/README.md at master
 | date = 14 November 2014 | access-date = 12 February 2015
 | website = github.com
}}</ref>  This very first implementation, known as {{Mono|amdkfd}}, focuses on [[Engineering:AMD Accelerated Processing Unit#Steamroller architecture .282014.29: Kaveri|"Kaveri"]] or "Berlin" APUs and works alongside the existing Radeon kernel graphics driver.

Additionally, {{Mono|amdkfd}} supports ''heterogeneous queuing'' (HQ), which aims to simplify the distribution of computational jobs among multiple CPUs and GPUs from the programmer's perspective. Support for ''heterogeneous memory management'' (''HMM''), suited only for graphics hardware featuring version 2 of the AMD's IOMMU, was accepted into the Linux kernel mainline version 4.14.<ref>{{cite web|url=https://www.xda-developers.com/linux-kernel-414/|title=Linux Kernel 4.14 Announced with Secure Memory Encryption and More|date=13 November 2017}}</ref>

Integrated support for HSA platforms has been announced for the "Sumatra" release of [[Software:OpenJDK|OpenJDK]], due in 2015.<ref>{{cite web |url=http://www.hpcwire.com/2013/08/26/hsa_foundation_aims_to_boost_javas_gpu_prowess/ |title=HSA Foundation Aims to Boost Java's GPU Prowess |author=Alex Woodie |date=26 August 2013 |website=HPCwire}}</ref>

[[Software:AMD APP SDK|AMD APP SDK]] is AMD's proprietary software development kit targeting [[Parallel computing|parallel computing]], available for Microsoft Windows and Linux.  Bolt is a C++ template library optimized for heterogeneous computing.<ref>{{cite web |url=https://github.com/HSA-Libraries/Bolt |title=Bolt on github|website=[[GitHub]]|date=11 January 2022}}</ref>

[[Software:GPUOpen|GPUOpen]] comprehends a couple of other software tools related to HSA. [[Software:CodeXL|CodeXL]] version 2.0 includes an HSA profiler.<ref>{{cite web |url=http://gpuopen.com/codexl-2-0-is-here-and-open-source/ |title=CodeXL 2.0 includes HSA profiler |author=AMD GPUOpen |date=2016-04-19 |access-date=21 April 2016 |archive-date=27 June 2018 |archive-url=https://web.archive.org/web/20180627034628/https://gpuopen.com/codexl-2-0-is-here-and-open-source/ |url-status=dead }}</ref>

{{Clear}}

==Hardware support==
===AMD===

Post-2015 Carrizo and Bristol Ridge APUs also include the version 2 IOMMU functionality for the integrated GPU.{{Citation needed|date=June 2016}}

{{AMD APU features}}

===ARM===
ARM's [[Engineering:Bifrost (microarchitecture)|Bifrost]] microarchitecture, as implemented in the Mali-G71,<ref>{{cite web |url=http://www.anandtech.com/show/10375/arm-unveils-bifrost-and-mali-g71/5 |title=ARM Bifrost GPU Architecture |date=2016-05-30}}</ref> is fully compliant with the HSA 1.1 hardware specifications. {{As of|2016|6}}, ARM has not announced software support that would use this hardware feature.

==See also==
* [[General-purpose computing on graphics processing units]] (GPGPU)
* Non-Uniform Memory Access (NUMA)
* [[Software:OpenMP|OpenMP]]
* [[Shared memory]]
* [[Zero-copy]]

==References==
{{Reflist|30em}}

==External links==
* {{YouTube|id=ln8JpfaLvbM|title=HSA Heterogeneous System Architecture Overview}} by Vinod Tipparaju at SC13 in November 2013
* [https://web.archive.org/web/20160514070602/http://www.mpsoc-forum.org/previous/2013/slides/8-Hegde.pdf HSA and the software ecosystem]
* [http://www-conf.slac.stanford.edu/xldb2012/talks/xldb2012_wed_1400_MichaelHouston.pdf 2012 – HSA by Michael Houston]

[[Category:Heterogeneous System Architecture| ]]

{{Sourceattribution|Heterogeneous System Architecture}}