View source for F16C

The '''F16C'''<ref>{{cite web|url=https://blogs.msdn.microsoft.com/chuckw/2012/09/11/directxmath-f16c-and-fma/|title=DirectXMath: F16C and FMA|author=Chuck Walbourn|date=September 11, 2012}}</ref> (previously/informally known as '''CVT16''') instruction set is an [[X86|x86]] [[Instruction set architecture|instruction set architecture]] extension which provides support for converting between half-precision and standard IEEE [[Single-precision floating-point format|single-precision floating-point format]]s.

== History ==
The CVT16 instruction set, announced by [[Company:Advanced Micro Devices|AMD]] on May 1, 2009,<ref>{{cite news |url=http://support.amd.com/us/Processor_TechDocs/43479.pdf |archive-url=https://web.archive.org/web/20090520223024/http://support.amd.com/us/Processor_TechDocs/43479.pdf |archive-date=2009-05-20  | accessdate = 2022-07-05 | work = AMD64 Architecture Programmer's Manual | title = 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions | volume = 6 | date = 2009-05-01 }}</ref> is an extension to the 128-bit [[Streaming SIMD Extensions|SSE]] core instructions in the [[X86|x86]] and AMD64 instruction set.

CVT16 is a revision of part of the [[SSE5]] instruction set proposal announced on August 30, 2007, which is supplemented by the [[XOP instruction set|XOP]] and [[FMA instruction set|FMA4]] instruction sets. This revision makes the binary coding of the proposed new instructions more compatible with [[Company:Intel|Intel]]'s [[Advanced Vector Extensions|AVX]] instruction extensions, while the functionality of the instructions is unchanged.

In recent documents, the name F16C is formally used in both [[Company:Intel|Intel]] and [[Engineering:AMD|AMD]] [[X86-64|x86-64]] architecture specifications.

==Technical information==
There are variants that convert four floating-point values in an [[Streaming SIMD Extensions#Registers|XMM register]] or 8 floating-point values in a [[Advanced Vector Extensions|YMM register]].

The instructions are abbreviations for "vector convert packed half to packed single" and vice versa:

* <code>VCVTPH2PS xmmreg,xmmrm64</code>{{snd}} convert four half-precision floating point values in memory or the bottom half of an XMM register to four single-precision floating-point values in an XMM register.
* <code>VCVTPH2PS ymmreg,xmmrm128</code>{{snd}} convert eight half-precision floating point values in memory or an XMM register (the bottom half of a YMM register) to eight single-precision floating-point values in a YMM register.
* <code>VCVTPS2PH xmmrm64,xmmreg,imm8</code>{{snd}} convert four single-precision floating point values in an XMM register to half-precision floating-point values in memory or the bottom half an XMM register.
* <code>VCVTPS2PH xmmrm128,ymmreg,imm8</code>{{snd}} convert eight single-precision floating point values in a YMM register to half-precision floating-point values in memory or an XMM register.

The 8-bit immediate argument to <code>VCVTPS2PH</code> selects the [[Rounding|rounding]] mode.  Values 0–4 select nearest, down, up, truncate, and the mode set in <code>MXCSR.RC</code>.

Support for these instructions is indicated by bit 29 of ECX after [[CPUID#EAX=1: Processor Info and Feature Bits|CPUID with EAX=1]].

== CPUs with F16C ==

* [[Company:Advanced Micro Devices|AMD]]:
** [[Engineering:Jaguar (microarchitecture)|Jaguar-based]] processors and newer 
** [[Engineering:Puma (microarchitecture)|Puma-based]] processors and newer 
** "Heavy Equipment" processors 
*** [[Engineering:Bulldozer (microarchitecture)|Bulldozer-based]] processors, Q4 2011<ref>{{citation|url=http://developer.amd.com/2009/05/06/striking-a-balance/ |archive-url=https://archive.today/20131109140737/http://developer.amd.com/2009/05/06/striking-a-balance/ |url-status=dead |archive-date=2013-11-09 |title=Striking a balance |author=Dave Christie |publisher=AMD Developer blogs |date=2009-05-07 |access-date=2012-01-17 }}</ref>
*** [[Engineering:Piledriver (microarchitecture)|Piledriver-based]] processors, Q4 2012<ref>{{citation |url= http://developer.amd.com/wordpress/media/2012/10/New-Bulldozer-and-Piledriver-Instructions.pdf |title= New "Bulldozer" and "Piledriver" Instructions |publisher= AMD |date= October 2012}}</ref>
*** [[Engineering:Steamroller (microarchitecture)|Steamroller-based]] processors, Q1 2014
*** [[Engineering:Excavator (microarchitecture)|Excavator-based]] processors and newer, 2015
** [[Engineering:Zen (microarchitecture)|Zen-based]] processors, Q1 2017
** [[Engineering:Zen+|Zen+-based]] processors, Q2 2018
** [[Engineering:Zen 2|Zen2-based]] processors, Q3 2019
* Intel:
** Ivy Bridge processors and newer

==References==
{{Reflist}}

== External links ==
* New Bulldozer and Piledriver Instructions [http://developer.amd.com/wordpress/media/2012/10/New-Bulldozer-and-Piledriver-Instructions.pdf]{{Dead link|date=April 2023}}
* DirectX math F16C and FMA  [http://blogs.msdn.com/b/chuckw/archive/2012/09/11/directxmath-f16c-and-fma.aspx]
* AMD64 Architecture Programmer's Manual Volume 1 [http://developer.amd.com/wordpress/media/2012/10/24592_APM_v11.pdf]{{Dead link|date=April 2023}}
* AMD64 Architecture Programmer's Manual Volume 2 [https://web.archive.org/web/20160303230732/http://developer.amd.com/wordpress/media/2012/10/24593_APM_v21.pdf]
* AMD64 Architecture Programmer's Manual Volume 3 [http://developer.amd.com/wordpress/media/2008/10/24594_APM_v3.pdf]{{Dead link|date=April 2023}}
* AMD64 Architecture Programmer's Manual Volume 4 [http://developer.amd.com/wordpress/media/2012/10/26568_APM_v41.pdf]{{Dead link|date=April 2023}}
* AMD64 Architecture Programmer's Manual Volume 5 [http://developer.amd.com/wordpress/media/2012/10/26569_APM_v51.pdf]{{Dead link|date=April 2023}}
* IA32 Architectures Software Developer Manual [http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf]

{{AMD technology}}
{{Intel technology}}
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[[Category:X86 instructions]]

{{Sourceattribution|F16C}}