View source for Phase-change memory

{{Short description|Novel computer memory type}}
{{Memory types}}
'''Phase-change memory''' (also known as '''PCM''', '''PCME''', '''PRAM''', '''PCRAM''', '''OUM''' ('''ovonic unified memory''') and '''C-RAM''' or '''CRAM''' ('''chalcogenide RAM''')) is a type of [[Non-volatile random-access memory|non-volatile random-access memory]]. PRAMs exploit the unique behaviour of [[Physics:Chalcogenide glass|chalcogenide glass]]. In PCM, heat produced by the passage of an [[Physics:Electric current|electric current]] through a [[Physics:Heating element|heating element]] generally made of [[Chemistry:Titanium nitride|titanium nitride]] is used to either quickly heat and [[Engineering:Quenching|quench]] the glass, making it [[Physics:Amorphous solid|amorphous]], or to hold it in its crystallization temperature range for some time, thereby switching it to a [[Earth:Crystal|crystal]]line state.<ref>{{Cite journal|last1=Le Gallo|first1=Manuel|last2=Sebastian|first2=Abu|date=2020-03-30|title=An overview of phase-change memory device physics|journal=Journal of Physics D: Applied Physics|language=en|volume=53|issue=21|pages=213002|doi=10.1088/1361-6463/ab7794|bibcode=2020JPhD...53u3002L |s2cid=213023359 |issn=0022-3727|doi-access=free}}</ref> PCM also has the ability to achieve a number of distinct intermediary states, thereby having the ability to hold multiple [[Bit|bit]]s in a single cell,<ref>{{Cite journal|last1=Burr|first1=Geoffrey W.|last2=BrightSky|first2=Matthew J.|last3=Sebastian|first3=Abu|last4=Cheng|first4=Huai-Yu|last5=Wu|first5=Jau-Yi|last6=Kim|first6=Sangbum|last7=Sosa|first7=Norma E.|last8=Papandreou|first8=Nikolaos|last9=Lung|first9=Hsiang-Lan|last10=Pozidis|first10=Haralampos|last11=Eleftheriou|first11=Evangelos|date=June 2016|title=Recent Progress in Phase-Change Memory Technology|url=https://ieeexplore.ieee.org/document/7453199|journal=IEEE Journal on Emerging and Selected Topics in Circuits and Systems|volume=6|issue=2|pages=146–162|doi=10.1109/JETCAS.2016.2547718|bibcode=2016IJEST...6..146B |s2cid=26729693 |issn=2156-3357}}</ref> but the difficulties in programming cells in this way has prevented these capabilities from being implemented in other technologies (most notably [[Flash memory|flash memory]]) with the same capability.

Recent research on PCM has been directed towards attempting to find viable material alternatives to the [[Physics:Phase-change material|phase-change material]] [[Physics:GeSbTe|Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub>]] (GST), with mixed success. Other research has focused on the development of a [[Chemistry:Germanium|Ge]][[Chemistry:Tellurium|Te]]–[[Chemistry:Antimony|Sb]]<sub>2</sub>Te<sub>3</sub> [[Physics:Superlattice|superlattice]] to achieve non-thermal [[Physics:Phase transition|phase changes]] by changing the co-ordination state of the germanium atoms with a [[Physics:Laser|laser]] pulse. This new Interfacial Phase-Change Memory (IPCM) has had many successes and continues to be the site of much active research.<ref>{{cite journal|display-authors=4|last=Simpson|first=R.E.|author2=P. Fons|author3=A. V. Kolobov|author4=T. Fukaya|author5=M. Krbal|author6=T. Yagi|author7=J. Tominaga|name-list-style=amp|title=Interfacial phase-change memory|journal=Nature Nanotechnology|date=July 2011|doi=10.1038/nnano.2011.96|pmid=21725305|volume=6|issue=8|pages=501–5|bibcode=2011NatNa...6..501S|s2cid=6684244}}</ref>

Leon Chua has argued that all two-terminal [[Non-volatile memory|non-volatile-memory]] devices, including PCM, should be considered [[Engineering:Memristor|memristor]]s.<ref name="chua11">{{citation |last=Chua |first=L. O. |date=2011 |title=Resistance switching memories are memristors |journal=Applied Physics A |volume=102 |issue=4 |pages=765–783 |doi=10.1007/s00339-011-6264-9 |bibcode=2011ApPhA.102..765C|doi-access=free }}</ref> [[Biography:R. Stanley Williams|Stan Williams]] of HP Labs has also argued that PCM should be considered a memristor.<ref name="Mellor2011">{{Citation |last=Mellor |first=Chris |date=10 October 2011|title=HP and Hynix to produce the memristor goods by 2013|url=https://www.theregister.co.uk/2011/10/10/memristor_in_18_months/ |work=The Register |access-date=2012-03-07}}</ref> However, this terminology has been challenged, and the potential applicability of memristor theory to any physically realizable device is open to question.<ref name="Meuffels_2012">{{cite arXiv |last1=Meuffels |first1=P. |last2=Soni |first2=R. |date=2012 |title=Fundamental Issues and Problems in the Realization of Memristors |eprint=1207.7319 |class=cond-mat.mes-hall }}</ref><ref name="DiVentra_2013">{{cite journal|last=Di Ventra|first=Massimiliano|author2=Pershin, Yuriy V.|title=On the physical properties of memristive, memcapacitive and meminductive systems|journal=Nanotechnology|date=2013|volume=24|issue=25|doi=10.1088/0957-4484/24/25/255201|arxiv = 1302.7063 |bibcode = 2013Nanot..24y5201D|pmid=23708238|page=255201|citeseerx=10.1.1.745.8657|s2cid=14892809}}</ref>

==Background==
In the 1960s, [[Biography:Stanford R. Ovshinsky|Stanford R. Ovshinsky]] of [[Company:Energy Conversion Devices|Energy Conversion Devices]] first explored the properties of [[Physics:Chalcogenide glass|chalcogenide glass]]es as a potential memory technology. In 1969, Charles Sie published a  dissertation at [[Organization:Iowa State University|Iowa State University]] that both described and demonstrated the feasibility of a phase-change-memory device by integrating chalcogenide film with a [[Engineering:Diode|diode]] array.<ref>{{cite thesis |last=Sie |first=C.H. |title=Memory cell using bistable resistivity in amorphous As-Te-Ge film |year=1969 |work=Retrospective Theses and Dissertations |id=3604 https://lib.dr.iastate.edu/rtd/3604 |type=PhD |publisher=Iowa State University}}</ref><ref>{{cite journal |last1=Pohm |first1=A. |last2=Sie |first2=C. |last3=Uttecht |first3=R. |last4=Kao |first4=V. |last5=Agrawal |first5=O. |year=1970 |title=Chalcogenide glass bistable resistivity (Ovonic) memories |url= |journal=IEEE Transactions on Magnetics |volume=6 |issue=3 |pages=592 |bibcode=1970ITM.....6..592P |doi=10.1109/TMAG.1970.1066920}}</ref> A cinematographic study in 1970 established that the phase-change-memory mechanism in chalcogenide glass involves [[Physics:Electric field|electric-field]]-induced [[Physics:Crystal growth|crystalline filament growth]].<ref>"Electric-Field Induced Filament Formation in As-Te-Ge Semiconductor" C.H. Sie, R. Uttecht, H. Stevenson, J. D. Griener and K. Raghavan , Journal of Non-Crystalline Solids, 2, 358–370,1970</ref><ref>{{cite web|url=https://www.youtube.com/watch?v=0bgVsOk17vw  |archive-url=https://ghostarchive.org/varchive/youtube/20211221/0bgVsOk17vw |archive-date=2021-12-21 |url-status=live|title=A Cinematic Study of Mechanisms of Phase Change Memory |publisher=YouTube |date=2012-06-21 |access-date=2013-09-17}}{{cbignore}}</ref> In the September 1970 issue of ''[[Engineering:Electronics (magazine)|Electronics]]'', Gordon Moore, co-founder of [[Company:Intel|Intel]], published an article on the technology.<ref>{{Cite journal |last1=Moore |first1=Gordon E. |last2=Neale |first2=R.G. |last3=Nelson |first3=D.L. |date=September 28, 1970 |title=Nonvolatile and reprogramable, the read-mostly memory is here |url=https://objective-analysis.com/uploads/Electronics%201970%20Neale%20Nelson%20Moore.pdf |journal=[[Engineering:Electronics (magazine)|Electronics]] |pages=56–60}}</ref> However, material quality and power consumption issues prevented commercialization of the technology. More recently, interest and research have resumed as [[Flash memory|flash]] and [[Dynamic random-access memory|DRAM]] memory technologies are expected to encounter scaling difficulties as chip lithography shrinks.<ref>{{cite web|url=http://features.techworld.com/storage/3211959/is-nand-flash-memory-a-dying-technology/|publisher=Techworld|title=Is NAND flash memory a dying technology?|access-date= 2010-02-04}}</ref>

The [[Earth:Crystal|crystal]]line and [[Physics:Amorphous solid|amorphous]] states of chalcogenide glass have dramatically different electrical resistivity values. The amorphous, high resistance state represents a binary 0, while the crystalline, low resistance state represents a 1.{{citation needed|date=July 2012}} Chalcogenide is the same material used in re-writable [[Engineering:Optical disc|optical media]] (such as [[Engineering:CD-RW|CD-RW]] and DVD-RW). In those instances, the material's optical properties are manipulated, rather than its electrical resistivity, as chalcogenide's [[Physics:Refractive index|refractive index]] also changes with the state of the material.

Although PRAM has not yet reached the commercialization stage for consumer electronic devices, nearly all prototype devices make use of a chalcogenide alloy of [[Chemistry:Germanium|germanium]] (Ge), [[Chemistry:Antimony|antimony]] (Sb) and [[Chemistry:Tellurium|tellurium]] (Te) called [[Physics:GeSbTe|GeSbTe]] (GST). The [[Chemistry:Stoichiometry|stoichiometry]], or Ge:Sb:Te element ratio, is 2:2:5 in GST. When GST is heated to a high temperature (over 600&nbsp;°C), its chalcogenide crystallinity is lost. Once cooled, it is frozen into an amorphous glass-like state <ref>{{Cite journal|last1=Caravati|first1=Sebastiano|last2=Bernasconi|first2=Marco|last3=Kühne|first3=Thomas D.|last4=Krack|first4=Matthias|last5=Parrinello|first5=Michele|title=Coexistence of tetrahedral- and octahedral-like sites in amorphous phase change materials|journal=Applied Physics Letters|volume=91|issue=17|pages=171906|year=2007|doi=10.1063/1.2801626|arxiv=0708.1302|bibcode=2007ApPhL..91q1906C|s2cid=119628572}}</ref> and its [[Physics:Electrical resistance|electrical resistance]] is high. By heating the chalcogenide to a temperature above its [[Physics:Crystallization|crystallization point]], but below the [[Physics:Melting point|melting point]], it will transform into a crystalline state with a much lower resistance. The time to complete this phase transition is temperature-dependent. Cooler portions of the chalcogenide take longer to crystallize, and overheated portions may be remelted. A crystallization time scale on the order of 100[[Nanosecond|&nbsp;ns]] is commonly used.<ref>{{cite book |first=H. |last=Horii |display-authors=0 |chapter=A novel cell technology using N-doped GeSbTe films for phase change RAM |title=2003 Symposium on VLSI Technology. Digest of Technical Papers |year=2003 |isbn=4-89114-033-X |doi=10.1109/VLSIT.2003.1221143 |pages=177–8 |s2cid=40051862 |id=03CH37407}}</ref> This is longer than conventional volatile memory devices like modern DRAM, which have a switching time on the order of two nanoseconds. However, a January 2006 [[Company:Samsung Electronics|Samsung Electronics]] patent application indicates PRAM may achieve switching times as fast as five nanoseconds.

A 2008 advance pioneered by [[Company:Intel|Intel]] and ST Microelectronics allowed the material state to be more carefully controlled, allowing it to be transformed into one of four distinct states: the previous amorphous or crystalline states, along with two new partially crystalline ones. Each of these states has different electrical properties that can be measured during reads, allowing a single cell to represent two [[Bit|bit]]s, doubling [[Density (computer storage)|memory density]].<ref name=review>{{cite news |url=https://www.technologyreview.com/2008/02/04/35301/a-memory-breakthrough/ |title=A Memory Breakthrough |first=Kate |last=Greene |newspaper=Technology Review |date=4 February 2008}}</ref>

===Aluminum/antimony===
Phase-change memory devices based on [[Chemistry:Germanium|germanium]], [[Chemistry:Antimony|antimony]] and [[Chemistry:Tellurium|tellurium]] present manufacturing challenges, since etching and polishing of the material with [[Chemistry:Chalcogen|chalcogen]]s can change the material's composition. Materials based on [[Chemistry:Aluminium|aluminum]] and antimony are more thermally stable than [[Physics:GeSbTe|GeSbTe]].  [[Chemistry:Aluminium antimonide|Al<sub>50</sub>Sb<sub>50</sub>]] has three distinct resistance levels, offering the potential to store three bits of data in two cells as opposed to two (nine states possible for the pair of cells, using eight of those states yields log<sub>2</sub>&nbsp;8&nbsp;=&nbsp;3&nbsp;bits).<ref>{{cite web|url=http://www.kurzweilai.net/will-phase-change-memory-replace-flash-memory |title=Will phase-change memory replace flash memory? |publisher=KurzweilAI |access-date=2013-09-17}}</ref><ref>{{Cite journal | last1 = Zhou | first1 = X. | last2 = Wu | first2 = L. | last3 = Song | first3 = Z. | last4 = Rao | first4 = F. | last5 = Ren | first5 = K. | last6 = Peng | first6 = C. | last7 = Song | first7 = S. | last8 = Liu | first8 = B. | last9 = Xu | first9 = L. | last10 = Feng | first10 = S. | doi = 10.1063/1.4818662 | title = Phase transition characteristics of Al-Sb phase change materials for phase change memory application | journal = Applied Physics Letters | volume = 103 | issue = 7 | pages = 072114 | year = 2013 | bibcode = 2013ApPhL.103g2114Z }}</ref>

[[File:PRAM cell structure.svg|thumb|300px|right|A cross-section of two PRAM memory cells. One cell is in low resistance crystalline state, the other in high resistance amorphous state.]]

==PRAM vs. Flash==
PRAM's switching time and inherent scalability<ref name=scaling>{{cite journal|doi=10.1021/nl902777z | pmid=20041706 | volume=10 | issue=2 | title=Toward the Ultimate Limit of Phase Change in Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> | year=2010 | journal=Nano Letters | pages=414–9 | last1 = Simpson | first1 = R. E.| bibcode=2010NanoL..10..414S | s2cid=9585187 }}</ref> make it more appealing than [[Flash memory|flash memory]]. PRAM's temperature sensitivity is perhaps its most notable drawback, one that may require changes in the production process of manufacturers incorporating the technology.

Flash memory works by modulating charge ([[Physics:Electron|electron]]s) stored within the gate of a [[Engineering:MOSFET|MOS transistor]]. The gate is constructed with a special "stack" designed to trap charges (either on a floating gate or in [[Charge trap flash|insulator "traps"]]). The presence of charge within the gate shifts the transistor's [[Physics:Threshold voltage|threshold voltage]] <math>\,V_\mathrm{th}</math> higher or lower, corresponding to a change in the cell's [[Bit|bit]] state from 1 to 0 or 0 to 1. Changing the bit's state requires removing the accumulated charge, which demands a relatively large [[Physics:Voltage|voltage]] to "suck" the electrons off the floating gate. This burst of voltage is provided by a [[Engineering:Charge pump|charge pump]], which takes some time to build up power. General write times for common flash devices are on the order of 100[[Microsecond|&nbsp;μs]] (for a block of data), about 10,000 times the typical 10[[Nanosecond|&nbsp;ns]] read time for [[Static random-access memory|SRAM]] for example (for a [[Byte|byte]]).{{Citation needed|date=April 2022}}

PRAM can offer much higher performance in applications where writing quickly is important, both because the memory element can be switched more quickly, and also because single bits may be changed to either 1 or 0 without needing to first erase an entire block of cells. PRAM's high performance, thousands of times faster than conventional [[Engineering:Hard disk drive|hard drives]], makes it particularly interesting in [[Non-volatile memory|nonvolatile memory]] roles that are currently performance-limited by memory access timing.

In addition, with flash, each burst of voltage across the cell causes degradation. As the size of the cells decreases, damage from programming grows worse because the voltage necessary to program the device does not scale with the lithography. Most flash devices are rated for, currently, only 5,000 writes per sector, and many flash controllers perform [[Wear leveling|wear leveling]] to spread writes across many physical sectors.

PRAM devices also degrade with use, for different reasons than flash, but degrade much more slowly. A PRAM device may endure around 100 million write cycles.<ref name=DailyTech>{{Cite web |url=http://dailytech.com/Article.aspx?newsid=6371 |title=Intel to Sample Phase Change Memory This Year |access-date=2007-06-30 |archive-url=https://web.archive.org/web/20070323030303/http://dailytech.com/Article.aspx?newsid=6371 |archive-date=2007-03-23 |url-status=dead }}</ref> PRAM lifetime is limited by mechanisms such as degradation due to [[Physics:GeSbTe|GST]] [[Physics:Thermal expansion|thermal expansion]] during programming, metal (and other material) migration, and other mechanisms still unknown.

Flash parts can be programmed before being [[Chemistry:Solder|solder]]ed onto a [[Engineering:Printed circuit board|board]], or even purchased pre-programmed. The contents of a PRAM, however, are lost because of the high temperatures needed to solder the device to a board (see [[Engineering:Reflow soldering|reflow soldering]] or [[Engineering:Wave soldering|wave soldering]]). This was made worse by the requirement to have [[Chemistry:Restriction of Hazardous Substances Directive|lead-free]] manufacturing requiring higher soldering temperatures. A manufacturer using PRAM parts must provide a mechanism to program the PRAM "in-system" after it has been soldered in place.

The special gates used in flash memory "leak" charge (electrons) over time, causing corruption and loss of data. The [[Physics:Electrical resistivity and conductivity|resistivity]] of the memory element in PRAM is more stable; at the normal working temperature of 85&nbsp;°C, it is projected to retain data for 300 years.<ref>{{cite journal |last1=Pirovano |first1=A. |last2=Redaelli |first2=A. |last3=Pellizzer |first3=F. |last4=Ottogalli |first4=F. |last5=Tosi |first5=M. |last6=Ielmini |first6=D. |last7=Lacaita |first7=A.L. |last8=Bez |first8=R. |title=Reliability study of phase-change nonvolatile memories |journal=IEEE Transactions on Device and Materials Reliability |volume=4 |issue=3 |pages=422–7 |year=2004 |doi=10.1109/TDMR.2004.836724 |s2cid=22178768 }}</ref>

By carefully modulating the amount of charge stored on the gate, flash devices can store multiple (usually two) bits in each physical cell. In effect, this doubles the [[Density (computer storage)|memory density]], reducing cost. PRAM devices originally stored only a single bit in each cell, but [[Company:Intel|Intel]]'s recent advances have removed this problem.{{Citation needed|date=April 2022}}

Because flash devices trap electrons to store information, they are susceptible to data corruption from [[Physics:Radiation|radiation]], making them unsuitable for many space and military applications. PRAM exhibits higher resistance to radiation.

PRAM cell selectors can use various devices: [[Engineering:Diode|diode]]s, [[Engineering:Bipolar junction transistor|BJTs]] and [[Engineering:MOSFET|MOSFET]]s. Using a diode or a BJT provides the greatest amount of [[Physics:Electric current|current]] for a given cell size. However, the concern with using a diode stems from parasitic currents to neighboring cells, as well as a higher voltage requirement, resulting in higher power consumption. Chalcogenide resistance is necessarily larger than that of a diode, meaning operating voltage must exceed 1&nbsp;V by a wide margin to guarantee adequate [[Physics:P–n junction#Forward bias|forward bias]] current from the diode. Perhaps the most severe consequence of using a diode-selected array, in particular for large arrays, is the total [[Physics:P–n junction#Reverse bias|reverse bias]] leakage current from the unselected bit lines. In [[Engineering:Transistor|transistor]]-selected arrays, only the selected bit lines contribute reverse bias leakage current. The difference in leakage current is several orders of magnitude. A further concern with scaling below 40&nbsp;nm is the effect of discrete [[Chemistry:Dopant|dopant]]s as the [[Physics:P–n junction|p-n junction]] width scales down. [[Physics:Thin-film transistor|Thin film]]-based selectors allow higher densities, utilizing <&nbsp;4&nbsp;F<sup>2</sup> cell area by stacking memory layers horizontally or vertically. Often the isolation capabilities are inferior to the use of transistors if the on/off ratio for the selector is not sufficient, limiting the ability to operate very large arrays in this architecture. Chalcogenide-based threshold switches have been demonstrated as a viable selector for high-density PCM arrays <ref>{{cite book |last1=Karpov |first1=I.V. |last2=Kencke |first2=D. |last3=Kau |first3=D. |last4=Tang |first4=S. |last5=Spadini |first5=G. |chapter=Phase Change Memory with Chalcogenide Selector (PCMS): Characteristic Behaviors, Physical Models and Key Material Properties |title=Symposium G – Materials and Physics for Nonvolatile Memories II |publisher=Cambridge University Press |series=MRS Proceedings |volume=1250 |year=2010 |isbn= |pages=G14-01–H07-01 |doi=10.1557/PROC-1250-G14-01-H07-01}}</ref>

==2000 and later==
In August 2004, Nanochip licensed PRAM technology for use in [[Engineering:Microelectromechanical systems|MEMS]] (micro-electric-mechanical-systems) probe storage devices. These devices are not [[Solid-state drive|solid state]]. Instead, a very small platter coated in chalcogenide is dragged beneath thousands or even millions of electrical probes that can read and write the chalcogenide. [[Company:Hewlett-Packard|Hewlett-Packard]]'s micro-mover technology can accurately position the platter to 3[[Nanometre|&nbsp;nm]] so densities of more than 1[[Terabit|&nbsp;Tbit]] (125[[Gigabyte|&nbsp;GB]]) per square inch will be possible if the technology can be perfected. The basic idea is to reduce the amount of wiring needed on-chip; instead of wiring every cell, the cells are placed closer together and read by current passing through the MEMS probes, acting like wires. This approach resembles [[Company:IBM|IBM]]'s Millipede technology.

===Samsung 46.7 nm cell===
In September 2006, [[Company:Samsung|Samsung]] announced a prototype 512[[Megabit|&nbsp;Mb]] (64[[Megabyte|&nbsp;MB]]) device using [[Engineering:Diode|diode]] switches.<ref name=samsung>[http://www.samsung.com/us/business/semiconductor/newsView.do?news_id=766.0 SAMSUNG Introduces the Next Generation of Nonvolatile Memory—PRAM]</ref> The announcement was something of a surprise, and it was especially notable for its fairly high [[Density (computer storage)|memory density]]. The prototype featured a cell size of only 46.7&nbsp;nm, smaller than commercial [[Flash memory|flash]] devices available at the time. Although flash devices of higher ''capacity'' were available (64[[Gigabit|&nbsp;Gb]], or 8[[Gigabyte|&nbsp;GB]], was just coming to market), other technologies competing to replace flash in general offered lower densities (larger cell sizes). The only production [[Magnetoresistive RAM|MRAM]] and FeRAM devices are only 4&nbsp;Mb, for example. The high density of Samsung's prototype PRAM device suggested it could be a viable flash competitor, and not limited to niche roles as other devices have been. PRAM appeared to be particularly attractive as a potential [[NOR flash replacement|replacement for NOR flash]], where device capacities typically lag behind those of NAND flash devices. State-of-the-art capacities on NAND passed 512&nbsp;Mb some time ago. NOR flash offers similar densities to Samsung's PRAM prototype and already offers bit addressability (unlike NAND where memory is accessed in banks of many bytes at a time).

===Intel's PRAM device===
Samsung's announcement was followed by one from [[Company:Intel|Intel]] and [[Company:STMicroelectronics|STMicroelectronics]], who demonstrated their own PRAM devices at the 2006 Intel Developer Forum in October.<ref>{{Cite web|url=http://www.eweek.com/article2/0,1895,2021822,00.asp|title=Intel Previews Potential Replacement for Flash}}{{Dead link|date=October 2023 |bot=InternetArchiveBot |fix-attempted=yes }}</ref> They showed a 128 Mb part that began manufacture at STMicroelectronics's research lab in Agrate, Italy. Intel stated that the devices were strictly [[Proof of concept|proof-of-concept]].

===BAE device===
PRAM is also a promising technology in the military and aerospace industries where radiation effects make the use of standard [[Non-volatile memory|non-volatile memories]] such as flash impractical. PRAM devices have been introduced by BAE Systems, referred to as C-RAM, claiming excellent radiation tolerance (rad-hard) and latchup immunity. In addition, BAE claims a write cycle endurance of 10<sup>8</sup>, which will allow it to be a contender for replacing [[Programmable read-only memory|PROM]]s and [[EEPROM]]s in space systems.

===Multi-level cell===
In February 2008, Intel and STMicroelectronics revealed the first multilevel (MLC) PRAM array prototype. The prototype stored two logical bits in each physical cell, in effect 256&nbsp;Mb of memory stored in a 128&nbsp;Mb physical array. This means that instead of the normal two states—fully [[Physics:Amorphous solid|amorphous]] and fully [[Earth:Crystal|crystal]]line—an additional two distinct intermediate states represent different degrees of partial crystallization, allowing for twice as many bits to be stored in the same physical area.<ref name=review/> In June 2011,<ref name="engadget article">{{cite web|title=IBM develops 'instantaneous' memory, 100x faster than flash| publisher=engadget|date=2011-06-30|url=https://www.engadget.com/2011/06/30/embargo-ibm-develops-instantaneous-memory-100x-faster-than-fl/|access-date=2011-06-30}}</ref> IBM announced that they had created stable, reliable, multi-bit phase-change memory with high performance and stability. [[Company:SK Hynix|SK Hynix]] had a joint developmental agreement and a technology license agreement with IBM for the development of multi-level PRAM technology.<ref>{{Cite web|last=|title=SK hynix and IBM Sign Joint Development for PCRAM|url=https://news.skhynix.com/sk-hynix-and-ibm-sign-joint-development-for-pcram/|access-date=2022-02-05|website=SK hynix Newsroom|language=en-US}}</ref>

===Intel's 90 nm device===
Also in February 2008, Intel and STMicroelectronics shipped prototype samples of their first PRAM product to customers. The 90&nbsp;nm, 128&nbsp;Mb (16&nbsp;MB) product was called Alverstone.<ref name="numonyx_sample">{{cite web|title=Intel, STMicroelectronics Deliver Industry's First Phase Change Memory Prototypes|publisher=Numonyx|date=2008-02-06|url=http://www.numonyx.com/en-US/About/PressRoom/Releases/Pages/IntelSTDeliverFirstPCMPrototypes.aspx|access-date=2008-08-15 |archive-url = https://web.archive.org/web/20080609215913/http://www.numonyx.com/en-US/About/PressRoom/Releases/Pages/IntelSTDeliverFirstPCMPrototypes.aspx <!-- Bot retrieved archive --> |archive-date = 2008-06-09}}</ref>

In June 2009, Samsung and Numonyx B.V. announced a collaborative effort in the development of PRAM market-tailored hardware products.<ref name="Samsung Electronics and Numonyx Join Forces on Phase Change Memory">{{cite web|title=Samsung Electronics and Numonyx Join Forces on Phase Change Memory| publisher=Samsung|date=2009-06-23|url=http://www.samsung.com/us/business/semiconductor/newsView.do?news_id=1023;articleID=1023}}</ref>

In April 2010,<ref name="eetimes article">{{cite web|title=Samsung to ship MCP with phase-change| publisher=EE Times|date=2010-04-28|url=http://www.eetimes.com/showArticle.jhtml;jsessionid=AZ0IF3RVEBPQVQE1GHPSKHWATMY32JVN?articleID=224700051|access-date=2010-05-03}}</ref> Numonyx announced the Omneo line of 128-Mbit NOR-compatible phase-change memories. Samsung announced shipment of 512&nbsp;Mb phase-change RAM (PRAM) in a multi-chip package (MCP) for use in mobile handsets by Fall 2010.

===ST 28 nm, 16 MB array===
In December 2018 STMicroelectronics presented design and performance data for a 16&nbsp;MB ePCM array for a 28&nbsp;nm fully depleted [[Physics:Silicon on insulator|silicon on insulator]] automotive control unit.<ref>{{Cite web |title=Phase-Change Memory (PCM) - Technology, Advantages & Applications - STMicroelectronics |url=https://www.st.com/content/st_com/en/about/innovation---technology/PCM.html |access-date=2022-07-08 |website=www.st.com |language=en}}</ref>

===In-memory computing===
More recently, there is significant interest in the application of PCM for in-memory computing.<ref>{{Cite journal|last1=Burr|first1=Geoffrey W.|last2=Shelby|first2=Robert M.|last3=Sidler|first3=Severin|last4=di Nolfo|first4=Carmelo|last5=Jang|first5=Junwoo|last6=Boybat|first6=Irem|last7=Shenoy|first7=Rohit S.|last8=Narayanan|first8=Pritish|last9=Virwani|first9=Kumar|last10=Giacometti|first10=Emanuele U.|last11=Kurdi|first11=Bulent N.|date=November 2015|title=Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element|url=https://ieeexplore.ieee.org/document/7151827|journal=IEEE Transactions on Electron Devices|volume=62|issue=11|pages=3498–3507|doi=10.1109/TED.2015.2439635|bibcode=2015ITED...62.3498B |s2cid=5243635 |issn=0018-9383}}</ref> The essential idea is to perform computational tasks such as [[Matrix multiplication algorithm|matrix-vector-multiply operations]] in the memory array itself by exploiting PCM's analog storage capability and [[Kirchhoff's circuit laws]]. PCM-based in-memory computing could be interesting for applications such as [[Deep learning|deep learning]] [[Statistical inference|inference]] which do not require very high computing precision.<ref>{{Cite journal|last1=Sebastian|first1=Abu|last2=Le Gallo|first2=Manuel|last3=Khaddam-Aljameh|first3=Riduan|last4=Eleftheriou|first4=Evangelos|date=July 2020|title=Memory devices and applications for in-memory computing|url=https://www.nature.com/articles/s41565-020-0655-z|journal=Nature Nanotechnology|language=en|volume=15|issue=7|pages=529–544|doi=10.1038/s41565-020-0655-z|pmid=32231270 |bibcode=2020NatNa..15..529S |s2cid=214704544 |issn=1748-3395}}</ref> In 2021, IBM published a full-fledged in-memory computing core based on multi-level PCM integrated in 14&nbsp;nm [[Engineering:CMOS|CMOS]] technology node.<ref>{{Cite journal|last1=Khaddam-Aljameh|first1=Riduan|last2=Stanisavljevic|first2=Milos|last3=Mas|first3=Jordi Fornt|last4=Karunaratne|first4=Geethan|last5=Brändli|first5=Matthias|last6=Liu|first6=Feng|last7=Singh|first7=Abhairaj|last8=Müller|first8=Silvia M.|last9=Egger|first9=Urs|last10=Petropoulos|first10=Anastasios|last11=Antonakopoulos|first11=Theodore|date=2022|title=HERMES-Core–A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs|journal=IEEE Journal of Solid-State Circuits|volume=57 |issue=4 |pages=1027–1038|doi=10.1109/JSSC.2022.3140414|bibcode=2022IJSSC..57.1027K |s2cid=246417395 |issn=1558-173X|doi-access=free}}</ref>

==Challenges==
The greatest challenge for phase-change memory has been the requirement of high programming [[Physics:Current density|current density]] (>10<sup>7</sup>[[Ampere|&nbsp;A]]/cm², compared to 10<sup>5</sup>...10<sup>6</sup>&nbsp;A/cm² for a typical [[Engineering:Transistor|transistor]] or [[Engineering:Diode|diode]]). {{citation needed|date=June 2012}}
The contact between the hot phase-change region and the adjacent [[Physics:Dielectric|dielectric]] is another fundamental concern. The dielectric may begin to leak [[Physics:Electric current|current]] at higher temperature, or may lose [[Chemistry:Adhesion|adhesion]] when expanding at a different rate from the phase-change material.

Phase-change memory is susceptible to a fundamental tradeoff of unintended vs. intended phase-change. This stems primarily from the fact that phase-change is a thermally driven process rather than an electronic process. Thermal conditions that allow for fast [[Physics:Crystallization|crystallization]] should not be too similar to standby conditions, e.g. room temperature, otherwise data retention cannot be sustained. With the proper [[Chemistry:Activation energy|activation energy]] for crystallization it is possible to have fast crystallization at programming conditions while having very slow crystallization at normal conditions.

Probably the biggest challenge for phase-change memory is its long-term [[Physics:Electrical resistance and conductance|resistance]] and [[Physics:Threshold voltage|threshold voltage]] drift.<ref>{{cite journal |first1=I.V. |last1=Karpov |first2=M. |last2=Mitra |first3=D. |last3=Kau |first4=G. |last4=Spadini |first5=Y.A. |last5=Kryukov |first6=V.G. |last6=Karpov |title=Fundamental drift of parameters in chalcogenide phase change memory |journal=J. Appl. Phys. |volume=102 |issue= 12|pages=124503–124503–6 |year=2007 |doi=10.1063/1.2825650 |bibcode=2007JAP...102l4503K }}</ref> The resistance of the [[Physics:Amorphous solid|amorphous]] state slowly increases according to a [[Power law|power law]] (~t<sup>0.1</sup>). This severely limits the ability for multilevel operation, since a lower intermediate state would be confused with a higher intermediate state at a later time, and could also jeopardize standard two-state operation if the threshold voltage increases beyond the design value.

In April 2010, Numonyx released its Omneo line of parallel and serial interface 128&nbsp;Mb [[NOR flash replacement]] PRAM chips. Although the NOR flash chips they intended to replace operated in the −40-85&nbsp;°C range, the PRAM chips operated in the 0-70&nbsp;°C range, indicating a smaller operating window compared to NOR flash. This is likely due to the use of highly temperature-sensitive [[Physics:P–n junction|p–n junction]]s to provide the high currents needed for programming.

==Timeline==
*'''January 1955''': Kolomiets and Gorunova revealed semiconducting properties of [[Physics:Chalcogenide glass|chalcogenide glass]]es.<ref>{{cite journal|doi=10.1002/pssb.19640070202 | volume=7 | issue=2 | title=Vitreous Semiconductors (I) | year=1964 | journal=Physica Status Solidi B | pages=359–372 | last1 = Kolomiets | first1 = B. T.| bibcode=1964PSSBR...7..359K | s2cid=222432031 }}</ref><ref>{{cite journal|doi=10.1002/pssb.19640070302 | volume=7 | issue=3 | title=Vitreous Semiconductors (II) | year=1964 | journal=Physica Status Solidi B | pages=713–731 | last1 = Kolomiets | first1 = B. T.| bibcode=1964PSSBR...7..713K }}</ref>
*'''September 1966''': Stanford Ovshinsky files first patent on phase-change technology
*'''January 1969''': Charles H. Sie published a dissertation at Iowa State University on chalcogenide phase-change-memory device
*'''June 1969''': US Patent 3,448,302 (Shanefield) licensed to Ovshinsky claims first reliable operation of PRAM device
*'''September 1970''': Gordon Moore publishes research in Electronics Magazine
*'''June 1999''': Ovonyx joint venture is formed to commercialize PRAM technology
*'''November 1999''': Lockheed Martin works with Ovonyx on PRAM for space applications
*'''February 2000''': Intel invests in Ovonyx, licenses technology
*'''December 2000''': ST Microelectronics licenses PRAM technology from Ovonyx
*'''March 2002''': Macronix files a patent application for transistor-less PRAM
*'''July 2003''': Samsung begins work on PRAM technology
*'''2003 through 2005''': PRAM-related patent applications filed by Toshiba, Hitachi, Macronix, Renesas, Elpida, Sony, Matsushita, Mitsubishi, Infineon and more
*'''August 2004''': Nanochip licenses PRAM technology from Ovonyx for use in MEMS probe storage
*'''August 2004''': Samsung announces successful 64&nbsp;Mbit PRAM array
*'''February 2005''': Elpida licenses PRAM technology from Ovonyx
*'''September 2005''': Samsung announces successful 256&nbsp;Mbit PRAM array, touts 400&nbsp;μA programming current
*'''October 2005''': Intel increases investment in Ovonyx
*'''December 2005'''; Hitachi and Renesas announce 1.5&nbsp;V PRAM with 100&nbsp;μA programming current
*'''December 2005''': Samsung licenses PRAM technology from Ovonyx
*'''July 2006''': BAE Systems begins selling the first commercial PRAM chip
*'''September 2006''': Samsung announces 512&nbsp;Mbit PRAM device
*'''October 2006''': Intel and STMicroelectronics show a 128&nbsp;Mbit PRAM chip
*'''December 2006''': IBM Research Labs demonstrate a prototype 3 by 20 nanometers<ref>{{Cite web|url=http://www.techtree.com/India/News/Phase_Change_Memory_to_Replace_Flash/551-77782-581.html|archive-url=https://web.archive.org/web/20070927213502/http://www.techtree.com/India/News/Phase_Change_Memory_to_Replace_Flash/551-77782-581.html |url-status=dead |title=Phase Change to Replace Flash?|archive-date=September 27, 2007}}</ref>
*'''January 2007''': [[Company:Qimonda|Qimonda]] licenses PRAM technology from Ovonyx
*'''April 2007''': Intel's chief technology officer Justin Rattner is set to give the first public demonstration of the company's PRAM (phase-change RAM) technology <ref>{{Cite web|url=https://www.computerworld.com/|title=IT news, careers, business technology, reviews|website=Computerworld}}</ref>
*'''October 2007''': Hynix begins pursuing PRAM by licensing Ovonyx' technology
*'''February 2008''': Intel and STMicroelectronics announce four-state MLC PRAM<ref name=review/> and begin shipping samples to customers.<ref name="numonyx_sample" />
*'''December 2008''': Numonyx announces mass production 128&nbsp;Mbit PRAM device to selected customer.
*'''June 2009''': Samsung's phase-change RAM will go into mass production starting in June<ref>[https://www.engadget.com/2009/05/05/samsungs-pram-chips-go-into-mass-production-in-june/ Engadget Samsung PRAM chips go into mass production]</ref>
*'''September 2009''': Samsung announces mass production start of 512&nbsp;Mbit PRAM device<ref>{{Cite web|url=http://www.eetimessupplynetwork.com/220100470?cid=RSSfeed_eetsn_eetsnRSS|title=Samsung moves phase-change memory to production}}</ref>
*'''October 2009''': Intel and Numonyx announce they have found a way to stack phase-change memory arrays on one die<ref>{{Cite web|url=https://www.intel.com/pressroom/archive/releases/2009/20091028corp.htm|title=Intel and Numonyx Achieve Research Milestone with Stacked, Cross Point Phase Change Memory Technology|website=www.intel.com}}</ref>
*'''December 2009''': Numonyx announces 1&nbsp;Gb 45&nbsp;nm product<ref>[http://investors.micron.com/releasedetail.cfm?ReleaseID=467227 Numonyx to Present Phase-Change Memory Research Results at Leading Technology Industry Conference]</ref>
*'''April 2010''': Numonyx releases Omneo PRAM Series (P8P and P5Q), both in 90&nbsp;nm.<ref>{{Cite web |url=http://www.numonyx.com/en-US/About/PressRoom/Releases/Pages/NewPCMDevices.aspx |title=Numonyx Memory Solutions - Numonyx Introduces New Phase Change Memory Devices |date=April 25, 2010 |website= |archive-url=https://web.archive.org/web/20100425035721/http://www.numonyx.com/en-US/About/PressRoom/Releases/Pages/NewPCMDevices.aspx |archive-date=25 April 2010 |url-status=dead}}</ref>
*'''April 2010''': Samsung releases 512Mbit PRAM with 65&nbsp;nm process, in Multi-Chip-Package.<ref>{{Cite web|url=https://www.samsung.com/us/|archive-url=https://web.archive.org/web/20100821115849/http://www.samsung.com/us/aboutsamsung/news/newsIrRead.do?news_ctgry=irnewsrelease&page=1&news_seq=18828&rdoPeriod=ALL&from_dt=&to_dt=&search_keyword= |url-status=dead |title=Page Not Found - SAMSUNG|archive-date=August 21, 2010|website=Samsung Electronics America}}</ref>
*'''February 2011''': Samsung presented 58&nbsp;nm 1.8V 1Gb PRAM.<ref>{{cite book |first=H. |last=Chung |display-authors=0 |chapter=A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW |title=2011 IEEE International Solid-State Circuits Conference |year=2011 |isbn= 978-1-61284-303-2|pages=500–2 |doi=10.1109/ISSCC.2011.5746415|s2cid=206996875 }}</ref>
*'''February 2012''': Samsung presented 20&nbsp;nm 1.8V 8Gb PRAM<ref>[http://www.miracd.com/ISSCC2012/WebAP/PDF/AP_Full.pdf A 20nm 1.8V 8Gb PRAM with 40MB/s Program Bandwidth] {{webarchive|url=https://web.archive.org/web/20120131223524/http://www.miracd.com/ISSCC2012/WebAP/PDF/AP_Full.pdf |date=2012-01-31 }}</ref>
*'''July 2012''': Micron announces availability of Phase-Change Memory for mobile devices - the first PRAM solution in volume production<ref>[http://investors.micron.com/releasedetail.cfm?ReleaseID=692563 Micron Announces Availability of Phase Change Memory for Mobile Devices]</ref>
*'''January 2014''': Micron withdraws all PCM parts from the market.<ref>{{cite web |url=https://www.theregister.co.uk/2014/01/14/phase_change_micron_drops_phase_change_memory_products/ |title=Micron: Hot DRAM. We don't need no steenkin' PCM |last1=Mellor |first1=Chris |date=14 January 2014 |website=www.theregister.co.uk |publisher=The Register |access-date=14 January 2014}}</ref>
*'''May 2014''': IBM demonstrates combining PCM, conventional NAND, and DRAM on a single controller<ref>{{cite web |first=Joel |last=Hruska |title=IBM demonstrates next-gen phase-change memory that's up to 275 times faster than your SSD |date=8 May 2014 |publisher=ExtremeTech |url=http://www.extremetech.com/extreme/182096-ibm-demonstrates-next-gen-phase-change-memory-thats-up-to-275-times-faster-than-your-ssd}}</ref>
*'''August 2014''': Western Digital demonstrates prototype PCM storage with 3 million I/Os and 1.5 microsecond latency<ref>{{cite web |first=Joel |last=Hruska |title=Western Digital's HGST division creates new phase-change SSD that's orders of magnitude faster than any NAND flash drive on the market |date=6 August 2014 |publisher=ExtremeTech |url=http://www.extremetech.com/extreme/187577-hitachis-new-phase-change-ssd-is-orders-of-magnitude-faster-than-any-nand-flash-drive-on-the-market}}</ref>
*'''July 2015''': Intel and Micron announced 3D Xpoint memory where phase-change alloy is used as a storage part of a memory cell.

==See also==
* [[Ferroelectric RAM]] (FRAM)
* [[Physics:Magnetoresistive random-access memory|Magnetoresistive random-access memory]] (MRAM)
* [[Read-mostly memory]] (RMM)

==References==
{{reflist|colwidth=30em}}

==External links==
*[http://www.micron.com/ Micron]
*[https://web.archive.org/web/20100107193028/http://ovonyx.com/ Ovonyx, Inc.]
*[https://web.archive.org/web/20100619132610/http://www.ovonic.com/ Energy Conversion Devices, Inc.]
*[http://www.hitachi.com/New/cnews/051213.html Hitachi/Renesas Low-Power PRAM]
*[http://www.hp.com/hpinfo/abouthp/iplicensing/ars.html Hewlett-Packard Probe Storage]
*[https://web.archive.org/web/20110608044213/http://www.epcos.org/library/library2009.htm European\Phase Change and Ovonics Symposium]
*[https://web.archive.org/web/20080515194603/http://www.eis.na.baesystems.com/news_room/new_product_release/c_ram.htm BAE C-RAM Radiation-Hardened NVM press release]
*[https://web.archive.org/web/20070708125909/http://www.eis.na.baesystems.com/sse/memory_cram.htm BAE C-RAM Radiation-Hardened NVM data sheet]
*[https://web.archive.org/web/20090519205710/http://www.numonyx.com/en-US/Community/TechTalk/Pages/VideoDetail.aspx?ContentId=1 Introduction to PCM] by Numonyx (video)

{{emerging technologies|topics=yes|infocom=yes}}

{{DEFAULTSORT:Phase-Change Memory}}
[[Category:Computer memory]]

{{Sourceattribution|Phase-change memory}}