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{{Short description|Class of error correction codes}}

In [[Computer science|computer science]], '''repeat-accumulate codes''' ('''RA codes''') are a low complexity class of error-correcting codes. They were devised so that their ensemble weight distributions are easy to derive. RA codes were introduced by Divsalar ''et al.''

In an RA code, an information block of length <math>{N}</math> is repeated <math>{q}</math> times, scrambled by an interleaver of size <math>{qN}</math>, and then encoded by a rate 1 [[Accumulator (computing)|accumulator]]. The accumulator can be viewed as a truncated rate 1 recursive convolutional encoder with transfer function <math>{1/(1 + D)}</math>, but Divsalar ''et al.'' prefer to think of it as a block code whose input block <math>{(z_1, \ldots , z_n)}</math> and output block <math>{(x_1, \ldots , x_n)}</math> are related by the formula  <math>{x_1 = z_1}</math> and <math>x_i = x_{i-1}+z_i</math> for <math>i > 1</math>. The encoding time for RA codes is linear and their rate is <math>1/q</math>. They are nonsystematic.

==Irregular repeat accumulate codes==

Irregular repeat accumulate (IRA) codes build on top of the ideas of RA codes. IRA replaces the outer code in RA code with a low density generator matrix code.<ref>{{cite web |first=Hui |last=Jin |first2=Aamod |last2=Khandekar |first3=Robert |last3=McEliece |title=Irregular Repeat-Accumulate Codes |date=2000 |publisher=Department of Electrical Engineering, California Institute of Technology |url=http://www.mceliece.caltech.edu/publications/Brest00.pdf}}</ref>  IRA codes first repeats information bits different times, and then accumulates subsets of these repeated bits to generate parity bits. The irregular degree profile on the information nodes, together with the degree profile on the check nodes, can be designed using density evolution.

Systematic IRA codes are considered a form of LDPC code.  Litigation over whether the DVB-S2 LDPC code is a form of IRA code is ongoing.<ref>[http://www.law360.com/articles/622198/hughes-satellite-codes-spark-caltech-patent-suit Hughes Satellite Codes Spark Caltech Patent Suit]</ref> US patents 7,116,710; 7,421,032; 7,916,781; and 8,284,833 are at issue.{{cn|date=August 2021}}

==Notes==
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== References ==
* {{cite conference |first=D. |last=Divsalar |first2=H. |last2=Jin |first3=R.J. |last3=McEliece |title=Coding theorems for ‘turbo-like’ codes |book-title=Proceedings of the annual Allerton Conference on Communication control and Computing |date=September 1998 |pages=201–210 |volume=36 |publisher=University Of Illinois |url=https://www.researchgate.net/profile/Dariush-Divsalar/publication/243768674_Coding_Theorems_for_Turbo-Like_Codes/links/53e3cc5c0cf2fb74870dbbc1/Coding-Theorems-for-Turbo-Like-Codes.pdf}}

== External links ==
* [http://www.cambridge.org/gb/knowledge/isbn/item2711886/?site_locale=en_GB Iterative Error Correction: Turbo, Low-Density Parity-Check, and Repeat-Accumulate Codes]

[[Category:Error detection and correction]]

{{Sourceattribution|Repeat-accumulate code}}