Category:Electronic design automation

• Engineering:Electronic design automation

A

• Algorithmic state machine
• And-inverter graph
• Engineering:Antenna effect
• Asynchronous system

B

• Engineering:Black's equation
• Boolean satisfiability problem

C

• Engineering:Cell (EDA)
• Central processing unit
• Engineering:Circuit extraction
• Engineering:Clock gating

D

• Data processing unit
• Engineering:Design closure
• Engineering:Design flow (EDA)
• Engineering:Design for additive manufacturing
• Engineering:Design for manufacturability
• Engineering:Design for testing
• Engineering:Digital electronics
• Company:Dolphin Integration

E

• Engineering:EDA database
• Engineering:Electromagnetic field solver
• Chemistry:Electromigration
• Electronic circuit simulation
• Engineering:Electronic system-level design and verification
• Engineering:Elmore delay
• Engineering:Engineering change order

F

• Engineering:Fault coverage
• Engineering:Feedback-controlled electromigration
• Engineering:Fiduccia-Mattheyses algorithm
• Engineering:Fiduccia–Mattheyses algorithm
• Floorplan (microelectronics)
• FpgaC

G

• Gajski-Kuhn chart
• Gajski–Kuhn chart
• Generic array logic
• Generic Array Logic
• Engineering:Graphical system design
• Graphics processing unit

H

• Handel-C
• Engineering:Hardware obfuscation
• Hardware watermarking
• High-level synthesis
• Engineering:High-level verification

I

• Engineering:IC layout editor
• Engineering:IEC 61131-3
• Engineering:Integrated circuit layout

L

• Ladder logic
• Engineering:Lee algorithm
• Software:LibrePCB
• Logic optimization
• Engineering:Logic simulation
• Logic synthesis
• Engineering:Low-power FSM synthesis

M

• Engineering:Mask data preparation
• Engineering:Maze runner
• Engineering:Multi-channel length
• Engineering:Multi-project wafer service

N

• Engineering:Netlist
• Engineering:Network on a chip
• Engineering:Noise margin

O

• Engineering:Open Verification Methodology

P

• Engineering:PBIST
• Engineering:Physical design (electronics)
• Engineering:Place and route
• Engineering:Placement (electronic design automation)
• Planar SAT
• Engineering:Platform-based design
• Chemistry:Potential applications of carbon nanotubes
• Engineering:Power gating
• Engineering:Power network design (IC)
• Engineering:Power optimization (EDA)
• Programmable Array Logic
• Programmable logic array

R

• Engineering:Register-transfer level
• Rent's rule
• Engineering:Resolution enhancement technologies

S

• Satisfiability modulo theories
• Engineering:SCALD
• Schematic
• Engineering:Schematic capture
• Engineering:Schematic editor
• Engineering:Semiconductor device modeling
• Engineering:Semiconductor intellectual property core
• Engineering:Semiconductor process simulation
• Engineering:Signal integrity
• Engineering:Signoff (electronic design automation)
• Silicon compiler
• Engineering:Silvaco Data Systems v. Intel Corp.
• Simulation software
• Engineering:Standard cell
• State logic
• Engineering:Stuck-at fault
• Engineering:Substrate coupling
• Symbolic simulation
• Systems design

T

• Engineering:Technology CAD
• Engineering:Test compression
• Engineering:Touchstone file
• Engineering:Transaction-level modeling

U

• Ultra-large-scale systems
• Engineering:Universal Verification Methodology

V

• VISC architecture