Engineering:Noise margin
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In electrical engineering, noise margin is the maximum voltage amplitude of extraneous signal that can be algebraically added to the noise-free worst-case input level without causing the output voltage to deviate from the allowable logic voltage level.[1] It is commonly used in at least two contexts as follows:
- In communications system engineering, noise margin is the ratio by which the signal exceeds the minimum acceptable amount. It is normally measured in decibels.
- In a digital circuit, the noise margin is the amount by which the signal exceeds the threshold for a proper '0' (logic low) or '1' (logic high). For example, a digital circuit might be designed to swing between 0.0 and 1.2 volts, with anything below 0.2 volts considered a '0', and anything above 1.0 volts considered a '1'. Then the noise margin for a '0' would be the amount that a signal is below 0.2 volts, and the noise margin for a '1' would be the amount by which a signal exceeds 1.0 volt. In this case noise margins are measured as an absolute voltage, not a ratio. Noise margins for CMOS chips are usually much greater than those for TTL because the VOH min is closer to the power supply voltage and VOL max is closer to zero.
- Real digital inverters do not instantaneously switch from a logic high (1) to a logic low (0), there is some capacitance. While an inverter is transitioning from a logic high to low, there is an undefined region where the voltage cannot be considered high or low. This is considered a noise margin. There are two noise margins to consider: Noise margin high (NMH) and noise margin low (NML). NMH is the amount of voltage between an inverter transitioning from a logic high (1) to a logic low (0) and vice versa for NML. The equations are as follows: NMH ≡ VOH - VIH and NML ≡ VIL - VOL.[2] Typically, in a CMOS inverter VOH will equal VDD and VOL will equal the ground potential, as mentioned above.
- VIH is defined as the highest input voltage at which the slope of the voltage transfer characteristic (VTC) is equal to -1,[3] where the VTC is the plot of all valid output voltages vs. input voltages. Similarly, VIL is defined as the lowest input voltage where slope of the VTC is equal to -1.
- Real digital inverters do not instantaneously switch from a logic high (1) to a logic low (0), there is some capacitance. While an inverter is transitioning from a logic high to low, there is an undefined region where the voltage cannot be considered high or low. This is considered a noise margin. There are two noise margins to consider: Noise margin high (NMH) and noise margin low (NML). NMH is the amount of voltage between an inverter transitioning from a logic high (1) to a logic low (0) and vice versa for NML. The equations are as follows: NMH ≡ VOH - VIH and NML ≡ VIL - VOL.[2] Typically, in a CMOS inverter VOH will equal VDD and VOL will equal the ground potential, as mentioned above.
In practice, noise margins are the amount of noise, that a logic circuit can withstand. Noise margins are generally defined so that positive values ensure proper operation, and negative margins result in compromised operation, or outright failure.[3]
See also
- Digital circuit
- Signal integrity
- Substrate coupling
- ITU G.992.1
- signal-to-noise ratio
- signal
References
- ↑ "noise margin | JEDEC". https://www.jedec.org/standards-documents/dictionary/terms/noise-margin.
- ↑ "MIT PowerPoint". http://web.mit.edu/6.012/www/SP07-L11.pdf.
- ↑ 3.0 3.1 Gopal., Gopalan, K. (1996). Introduction to digital electronic circuits. Chicago: Irwin. ISBN 0256120897. OCLC 33664747. https://archive.org/details/introductiontodi00gopa.
External links
- DMT, a DSL monitoring and downstream noise margin tweaking program.
- MIT, PDF of a PowerPoint Presentation on for Digital Noise Margin.
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