Engineering:Gen-Z (consortium)
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| Year created | 2016 |
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| Created by | Gen-Z Consortium |
The Gen-Z Consortium is a trade group of technology vendors involved in designing CPUs, random access memory, servers, storage, and accelerators. The goal was to design an open and royalty-free "memory-semantic" bus protocol, which is not limited by the memory controller of a CPU, to be used in either a switched fabric or a point-to-point device link on a standard connector.[1]
In November 2021, the GenZ Consortium voted to transfer all its specifications and intellectual property to the CXL Consortium.[2]
History
The consortium was publicly announced on October 11, 2016.[3][4]
Members include server vendors Cisco Systems, Cray, Dell Technologies, Hewlett Packard Enterprise, Huawei, IBM, and Lenovo. CPU vendor members include Advanced Micro Devices, ARM Holdings, Broadcom Limited, IBM, and Marvell. Memory and storage vendor members include Micron Technology, Samsung, Seagate Technology, SK Hynix, and Western Digital. Other members include IDT Corporation, IntelliProp,[5] Mellanox Technologies, Microsemi, Red Hat, and Xilinx. Analysts noted the absence of Intel, which announced an inter-connect technology of its own called Omni-Path a year before, and Nvidia, with its own NVLink technology.[4][1] Gen-Z also maintains cooperation with industry alliances such as OpenFabrics,[6] SNIA, and DMTF.
The effort followed years of delays with product availability for version 4.0 of PCI Express.[7][8] Some of the vendors also joined a group to promote the cache coherent interconnect for accelerators (CCIX) protocol on the same day.[9] At about the same time, yet another consortium formed to work on an open specification for the Coherent Accelerator Processor Interface (CAPI).[10]
The first version of the GenZ Core specifications was published in 2018; it defines physical link that rom both PCI Express and 50 Gigabit Ethernet physical layer (PHY) standards. The Gen-Z protocol allows for asymmetric links with more bandwidth in one direction, and supports connection topologies like point to point links, daisy-chaining, and switched fabrics.[8] The basic operations consist of simple loads and stores with the addition of modular extensions.
Collaboration with CXL
On April 2, 2020, the Compute Express Link (CXL) and Gen-Z Consortiums announced a memorandum of understanding (MOU), describing collaboration between the two groups.[11][12] By October 2020, some technologies were demonstrated at the super computing conference, but no products were announced.[13]
In November 2021 the CXL Consortium and the GenZ Consortium signed a letter of intent for Gen-Z to transfer its specifications and assets to CXL, leaving CXL as the sole industry standard moving forward.[2] In January 2022, GenZ started the process of dissolving operations and transferring all assets to CXL.
References
- ↑ 1.0 1.1 "Gen-Z Consortium". Group's web site. http://genzconsortium.org.
- ↑ 2.0 2.1 CXL Consortium statement, 10 November 2021
- ↑ Agam Shah (October 11, 2016). "Hardware makers unite to challenge Intel with Gen-Z spec". CIO from IDG. http://www.cio.com/article/3130273/hardware-makers-unite-to-challenge-intel-with-gen-z-spec.html.
- ↑ 4.0 4.1 Chris Mellor (October 11, 2016). "HPE, IBM, ARM, Samsung and pals in plot to weave 'memory fabric': Everyone but Intel and Cisco working together to build storage-class memory". The Register. https://www.theregister.com/2016/10/11/memory_fabric_needed_for_storageclass_memory/.
- ↑ "Gen-Z Technology". http://intelliprop.com/hardware-storage-design/technology/technology-gen-z.htm.
- ↑ "OpenFabrics Alliance (OFA) and Gen-Z Consortium Announce MoU Agreement". 12 May 2020. https://genzconsortium.org/openfabrics-alliance-ofa-and-gen-z-consortium-announce-mou-agreement/.
- ↑ Evan Koblentz (February 3, 2017). "New PCI Express 4.0 delay may empower next-gen alternatives". Tech Republic. http://www.techrepublic.com/article/new-pci-express-4-0-delay-may-empower-next-gen-alternatives/.
- ↑ 8.0 8.1 Tallis, Billy (February 13, 2018). "Gen-Z Core Specification 1.0 Published". Anandtech. https://www.anandtech.com/show/12431/genz-interconnect-core-specification-10-published. Retrieved October 26, 2021.
- ↑ Jeff Defilippi (October 11, 2016). "How do AMBA, CCIX and GenZ address the needs of the data center?". ARM Community blog. https://community.arm.com/processors/b/blog/posts/how-do-amba-ccix-and-genz-address-the-needs-of-the-data-center.
- ↑ Chris Mellor (October 14, 2016). "Why OpenCAPI is a declaration of interconnect fabric war: Any standard but Intel in another CPU-memory interconnect consortium". The Register. https://www.theregister.co.uk/2016/10/14/opencapi_declaration_of_interconect_war/.
- ↑ Compute Express Link(CXL) Consortium and Gen-Z Consortium (April 2, 2020). "CXL Consortium and Gen-Z Consortium Announce MOU Agreement". https://b373eaf2-67af-4a29-b28c-3aae9e644f30.filesusr.com/ugd/0c1418_efb1cff3f41d486ea85d50ec638ea715.pdf.
- ↑ Gen-Z Consortium (April 2, 2020). "CXL Consortium and Gen-Z Consortium Announce MOU Agreement". https://genzconsortium.org/cxl-consortium-and-gen-z-consortium-announce-mou-agreement/.
- ↑ "Gen-Z Consortium's Activity Lineup at Upcoming Flash Memory Summit, SC20". Inside HPC. October 23, 2020. https://insidehpc.com/2020/10/gen-z-consortiums-activity-lineup-at-upcoming-flash-memory-summit-sc20/. Retrieved October 26, 2021.
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