UCIe

Short description: Universal Chiplet Interconnect express

Universal Chiplet Interconnect Express (UCIe) is an open specification for a die-to-die interconnect and serial bus between chiplets. It is co-developed by AMD, Arm, ASE Group, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC.

In August 2022, Alibaba Group and Nvidia joined as board members.

Overview

A common chiplet interconnect specification enables construction of large System-on-Chip (SoC) packages that exceed maximum reticle size. It allows intermixing components from different silicon vendors within the same package and improves manufacturing yields by using smaller dies. Each chiplet can use a different silicon manufacturing process, suitable for a specific device type, or computing performance and power draw requirements.

Specifications

The UCIe 1.0 specification was released on March 2, 2022. It defines physical layer, protocol stack and software model, as well as procedures for compliance testing. The physical layer supports up to 32 GT/s with 16 to 64 lanes and uses a 256 byte Flow Control Unit (FLIT) for data, similar to PCIe 6.0; the protocol layer is based on Compute Express Link with CXL.io (PCIe), CXL.mem and CXL.cache protocols.

Various on-die interconnect technologies are defined, like organic substrate for a 'standard' 2D package, or embedded silicon bridge (EMIB), silicon interposer, and fanout embedded bridge for 'advanced' 2.5D/3D packages. Physical specifications are based on Intel's Advanced Interface Bus (AIB).

Shorter signal paths allow the links to have 20× better I/O performance and power consumption (~0.5 pJ per bit) comparing to typical PCIe SerDes, with bandwidth density up to 1.35 TByte/s per mm² for a common bump pitch of 45 μm, and 3.24× higher density with a bump pitch of 25 μm.

Future versions may include additional protocols, wider data links, and higher density connections.

The UCIe 1.1 specification was released on August 8, 2023.