Engineering:Chiplet
A chiplet[1][2][3][4] is a tiny integrated circuit (IC) that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single package. A set of chiplets can be implemented in a mix-and-match "Lego-like" assembly. This provides several advantages over a traditional system on chip (SoC):
- Reusable IP (intellectual property):[5] the same chiplet can be used in many different devices
- Heterogeneous integration:[6] chiplets can be fabricated with different processes, materials, and nodes, each optimized for its particular function
- Known good die:[7] chiplets can be tested before assembly, improving the yield of the final device
Multiple chiplets working together in a single integrated circuit may be called a multi-chip module, hybrid IC, 2.5D IC, or an advanced package.
Chiplets may be connected with standards such as UCIe, bunch of wires (BoW), OpenHBI, and OIF XSR.
The term was coined by University of California, Berkeley professor John Wawrzynek as a component of the RAMP Project (research accelerator for multiple processors) in 2006 [8][9] extension for the Department of Energy, as was RISC-V architecture.
Common examples include:
- Intel Meteor Lake
- AMD Ryzen based on Zen 4 and later architecture
- NVidia H100
See also
References
- ↑ Brookes (25 July 2021). "What Is a Chiplet?". https://www.howtogeek.com/740584/what-is-a-chiplet/.
- ↑ "Chiplet". https://en.wikichip.org/wiki/chiplet.
- ↑ Semi Engineering "Chiplets" Retrieved 5 December 2022
- ↑ Don Scansen, EE Times "Chiplets: A Short History Retrieved 5 December 2022
- ↑ Keeler. "Common Heterogeneous Integration and IP Reuse Strategies (CHIPS)". https://www.darpa.mil/program/common-heterogeneous-integration-and-ip-reuse-strategies.
- ↑ Kenyon (6 April 2021). "Heterogeneous Integration and the Evolution of IC Packaging". https://www.eetimes.eu/heterogeneous-integration-and-the-evolution-of-ic-packaging/.
- ↑ Bertin, Claude L.; Su, Lo-Soun; Van Horn, Jody (2001). "Known Good die (KGD)". Area Array Interconnection Handbook. SpringerLink. pp. 149–200. doi:10.1007/978-1-4615-1389-6_4. ISBN 978-1-4613-5529-8. https://link.springer.com/chapter/10.1007/978-1-4615-1389-6_4. Retrieved 7 October 2022.
- ↑ Patterson, D.A. (March 2006). "RAMP: Research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform". 2006 IEEE International Symposium on Performance Analysis of Systems and Software. pp. 1–. doi:10.1109/ISPASS.2006.1620784. ISBN 1-4244-0186-0. https://ieeexplore.ieee.org/document/1620784.
- ↑ Wawrzynek, John (2015-05-01). "Accelerating Science Driven System Design With RAMP" (in English). UCB. https://www.osti.gov/biblio/1186854.
Further reading
- Clark, Don (11 May 2023). "U.S. Focuses on Invigorating 'Chiplets' to Stay Cutting-Edge in Tech". The New York Times. https://www.nytimes.com/2023/05/11/technology/us-chiplets-tech.html.
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