Wide-issue
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Revision as of 18:57, 3 November 2020 by imported>Rtexter1 (correction)
A wide-issue architecture is a computer processor that issues more than one instruction per clock cycle.[1] They can be considered in three broad types:
- Statically-scheduled superscalar architectures execute instructions in the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle.
- VLIW architectures rely on the programming software (compiler) to determine which instructions to dispatch on a given clock cycle.[2]
- Dynamically-scheduled superscalar architectures execute instructions in an order that gives the same result as the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle.[3]
See also
References
- ↑ "Scheduling for Superscalar & Multiple Issue Machines". http://pages.cs.wisc.edu/~fischer/cs701.f08/lectures/Lecture12.4up.pdf.
- ↑ "Wide Issue and Speculation". http://taco.cse.tamu.edu/utsa-www/cs5513-fall07/lecture6.html.
- ↑ Martin, Milo. "Superscalar". https://www.cis.upenn.edu/~milom/cis501-Fall11/lectures/07_superscalar.pdf.
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