Engineering:10 nm process

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Short description: MOSFET technology node

In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nm process as the MOSFET technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nm.

All production "10 nm" processes are based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology. Samsung first started their production of 10 nm-class chips in 2013 for their multi-level cell (MLC) flash memory chips, followed by their SoCs using their 10 nm process in 2016. TSMC began commercial production of 10 nm chips in 2016, and Intel later began production of 10 nm chips in 2018.

Since 2009, however, "node" has become a commercial name for marketing purposes[1] that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch.[2][3][4] For example, GlobalFoundries' 7 nm processes are similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred.[5] TSMC and Samsung's 10 nm processes are somewhere between Intel's 14 nm and 10 nm processes in transistor density. The transistor density (number of transistors per square millimetre) is more important than transistor size, since smaller transistors no longer necessarily mean improved performance, or an increase in the number of transistors.

Background

Egyptian-American engineer Mohamed Atalla and Korean-American engineer Dawon Kahng (the original inventors of the MOSFET in 1959)[6] in 1962 demonstrated a device that has a metallic layer with nanometric thickness sandwiched between two semiconducting layers, with the metal forming the base and the semiconductors forming the emitter and collector. They deposited metal layers (the base) on top of single crystal semiconductor substrates (the collector), with the emitter being a crystalline semiconductor piece with a top or a blunt corner pressed against the metallic layer (the point contact). With the low resistance and short transit times in the thin metallic nanolayer base, the devices were capable of high operation frequency compared to bipolar transistors. The device demonstrated by Atalla and Kahng deposited gold (Au) thin films with a thickness of 10 nm on n-type germanium (n-Ge) and the point contact was n-type silicon (n-Si).[7]

In 1987, Iranian-American engineer Bijan Davari led an IBM research team that demonstrated the first MOSFET with a 10 nm gate oxide thickness, using tungsten-gate technology.[8]

In 2002, an international team of researchers at UC Berkeley, including Shibly Ahmed (Bangladeshi), Scott Bell, Cyrus Tabery (Iranian), Jeffrey Bokor, David Kyser, Chenming Hu (Taiwan Semiconductor Manufacturing Company), and Tsu-Jae King Liu, demonstrated the first FinFET with 10 nm gate length.[9][10]

The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm.

In 2008, Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, said that Intel saw a 'clear way' towards the 10 nm node.[11][12]

In 2011, Samsung announced plans to introduce the 10 nm process the following year.[13] In 2012, Samsung announced eMMC flash memory chips that are produced using the 10 nm process.[14]

In actuality, "10 nm" as it is generally understood in 2018 is only in high-volume production at Samsung. GlobalFoundries has skipped 10 nm, Intel has not yet started high-volume 10 nm production, due to yield issues, and TSMC has considered 10 nm to be a short-lived node,[15] mainly dedicated to processors for Apple during 2017–2018, moving on to 7 nm in 2018.

There is also a distinction to be made between 10 nm as marketed by foundries and 10 nm as marketed by DRAM companies.

Technology production history

In April 2013, Samsung announced that it had begun mass production of multi-level cell (MLC) flash memory chips using a 10 nm-class process, which, according to Tom's Hardware, Samsung defined as "a process technology node somewhere between 10-nm and 20-nm".[16] On 17 October 2016, Samsung Electronics announced mass production of SoC chips at 10 nm.[17] The technology's main announced challenge has been triple patterning for its metal layer.[18][19]

TSMC began commercial production of 10 nm chips in early 2016, before moving onto mass production in early 2017.[20]

On 21 April 2017, Samsung started shipping their Galaxy S8 smartphone which uses the company's version of the 10 nm processor.[21] On 12 June 2017, Apple delivered second-generation iPad Pro tablets powered with TSMC-produced Apple A10X chips using the 10 nm FinFET process.[22]

On 12 September 2017, Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC using a 10 nm FinFET process and containing 4.3 billion transistors on a die of 87.66 mm2.

In April 2018, Intel announced a delay in volume production of 10 nm mainstream CPUs until sometime in 2019.[23] In July the exact time was further pinned down to the holiday season.[24] In the meantime, however, they did release a low-power 10 nm mobile chip, albeit exclusive to Chinese markets and with much of the chip disabled.[25]

In June 2018 at VLSI 2018, Samsung announced their 11LPP and 8LPP processes. 11LPP is a hybrid based on Samsung 14 nm and 10 nm technology. 11LPP is based on their 10 nm BEOL, not their 20 nm BEOL like their 14LPP. 8LPP is based on their 10LPP process.[26][27]

Nvidia released their GeForce 30 series GPUs in September 2020. They are made on a custom version of Samsung's 8 nm process, called Samsung 8N, with a transistor density of 44.56 million transistors per mm2.[28][29]

10 nm process nodes

Foundry

ITRS Logic Device
Ground Rules (2015) 		Samsung TSMC Intel
Process name 16/14 nm 11/10 nm 10LPE/10LPP
(10 nm) 		11LPP
(11 nm) 		8LPP
(8 nm) 		10FF
(10 nm) 		10nm SF
(10 nm)[lower-alpha 1][lower-alpha 2]
Transistor density (MTr / mm2) Unknown Unknown 51.82[27] 54.38[27] 61.18[27] 52.51[31] 100.76[32][lower-alpha 3]
Transistor gate pitch (nm) 70 48 68 78 64 66 54
Interconnect pitch (nm) 56 36 51 ? ? 44 36
Transistor fin pitch (nm) 42 36 42 ? 42 36 34
Transistor fin height (nm) 42 42 49 ? ? 42 53
Production year 2015 2017 2017[27] 2018 2018 2016[lower-alpha 4]
2017[lower-alpha 5] 		2018(Cannon Lake)[34]
  1. ↑ for 10nm ESF renamed intel 7, see 7 nm)
  2. ↑ Measurements of the process used for Cannon Lake in 2018. It is unclear whether these will be the same for Intel's next 10nm process in 2019.[30]
  3. ↑ Intel uses this formula:[33] [math]\displaystyle{ \rm No.\ Transistors / mm^2 = 0.6 \cdot \frac{\rm NAND2\ Tr\ Count}{\rm NAND2\ Cell\ Area} + 0.4 \cdot \frac{\rm Scan\ Flip\ Flop\ Tr\ Count}{\rm Scan\ Flip\ Flop\ Cell\ Area} }[/math]
  4. ↑ accepting tape-outs[20]
  5. ↑ high volume shipment[20]

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their 10 nm process as having a 64 nm transistor gate pitch and 48 nm interconnect pitch. TSMC reported their 10 nm process as having a 64 nm transistor gate pitch and 42 nm interconnect pitch. Further investigation by Tech Insights revealed these values to be false and they have been updated accordingly. In addition, the transistor fin height of Samsung's 10 nm process was updated by MSSCORPS CO at SEMICON Taiwan 2017.[35][36][37][38][39] GlobalFoundries decided not to develop a 10 nm node, because it believed it would be short lived.[40] Samsung's 8 nm process is the company's last to exclusively use DUV lithography.[41]

DRAM "10 nm class"

Main page: Dynamic random-access memory

For the DRAM industry, the term "10 nm-class" is often used and this dimension generally refers to the half-pitch of the active area.[citation needed] The "10 nm" foundry structures are generally much larger.[citation needed]

Generally 10 nm class refers to DRAM with a 10-19 nm feature size, and was first introduced c. 2016. As of 2020 there are three generations of 10 nm class DRAM : 1x nm (19-17 nm, Gen1); 1y nm (16-14 nm, Gen2); and 1z nm (13-11 nm, Gen3).[42] 3rd Generation "1z" DRAM was first introduced c.2019 by Samsung, and was initially stated to be produced using ArF lithography without the use of EUV lithography;[43][44] subsequent production did utilise EUV lithography.[45]

Beyond 1z Samsung names its next node (fourth generation 10 nm class) DRAM : "D1a" (for 2021), and beyond that D1b (expected 2022); whilst Micron refers to succeeding "nodes" as "D1α" and "D1β".[46] Micron announced volume shipment of 1α class DRAM in early 2021.[47]

References

  1. ↑ "No More Nanometers – EEJournal". https://www.eejournal.com/article/no-more-nanometers/. 
  2. ↑ Shukla, Priyank. "A Brief History of Process Node Evolution". https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html. 
  3. ↑ Hruska, Joel. "14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists...". https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists. 
  4. ↑ "Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022". 2016-09-10. https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/. 
  5. ↑ "Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms". 2018-03-12. https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/. 
  6. ↑ "1960: Metal Oxide Semiconductor (MOS) Transistor Demonstrated". The Silicon Engine (Computer History Museum). https://www.computerhistory.org/siliconengine/metal-oxide-semiconductor-mos-transistor-demonstrated/. Retrieved August 31, 2019. 
  7. ↑ Pasa, André Avelino (2010). "Chapter 13: Metal Nanolayer-Base Transistor". Handbook of Nanophysics: Nanoelectronics and Nanophotonics. CRC Press. pp. 13-1, 13-4. ISBN 9781420075519. https://books.google.com/books?id=a3kJAMALo0MC&pg=SA13-PA1. 
  8. ↑ Davari, Bijan; Ting, Chung-Yu; Ahn, Kie Y.; Basavaiah, S.; Hu, Chao-Kun; Taur, Yuan; Wordeman, Matthew R.; Aboelfotoh, O. et al. (1987). "Submicron Tungsten Gate MOSFET with 10 nm Gate Oxide". 1987 Symposium on VLSI Technology. Digest of Technical Papers: 61–62. https://ieeexplore.ieee.org/document/4480422. 
  9. ↑ Tsu-Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". Symposium on VLSI Technology Short Course. https://people.eecs.berkeley.edu/~tking/presentations/KingLiu_2012VLSI-Tshortcourse. 
  10. ↑ Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin et al. (December 2002). "FinFET scaling to 10 nm gate length". Digest. International Electron Devices Meeting: 251–254. doi:10.1109/IEDM.2002.1175825. ISBN 0-7803-7462-2. https://www.eecs.wsu.edu/~osman/EE597/FINFET/finfet4.pdf. Retrieved 2019-10-12. 
  11. ↑ Damon Poeter (July 2008). "Intel's Gelsinger Sees Clear Path To 10nm Chips". http://www.crn.com/hardware/208801780. 
  12. ↑ "MIT: Optical lithography good to 12 nanometers". http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=209400807. 
  13. ↑ "World's Largest Fabrication Facility, Line-16". Samsung. September 26, 2011. https://news.samsung.com/global/world%E2%80%99s-largest-memory-fabrication-facility-line-16memory. 
  14. ↑ "Samsung's new 10nm-process 64GB mobile flash memory chips are smaller, faster, better". Engadget. November 15, 2012. https://www.engadget.com/2012/11/15/samsung-10nm-64gb-emmc-mobile-flash-memory/. 
  15. ↑ "10nm rollout". http://techinsights.com/about-techinsights/overview/blog/10nm-rollout-marching-right-along/. 
  16. ↑ "Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". Tom's Hardware. 11 April 2013. https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html. 
  17. ↑ Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology, Oct 2016, https://news.samsung.com/global/samsung-starts-industrys-first-mass-production-of-system-on-chip-with-10-nanometer-finfet-technology 
  18. ↑ "Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology". https://news.samsung.com/global/samsung-starts-industrys-first-mass-production-of-system-on-chip-with-10-nanometer-finfet-technology. 
  19. ↑ "triple patterning for 10nm metal". http://www.cse.cuhk.edu.hk/~byu/papers/N01-SPIE-TPL.pdf. 
  20. ↑ 20.0 20.1 20.2 "10nm Technology". TSMC. https://www.tsmc.com/english/dedicatedFoundry/technology/10nm.htm. 
  21. ↑ "Buy". http://www.samsung.com/us/explore/galaxy-s8/buy/. 
  22. ↑ techinsights.com. "10nm Rollout Marching Right Along". http://www.techinsights.com/about-techinsights/overview/blog/10nm-rollout-marching-right-along/. 
  23. ↑ "Intel Corp. Delays 10nm Chip Production - Mass production is now scheduled for 2019.". 2018-04-29. https://www.fool.com/investing/2018/04/29/intel-corp-delays-10nm-chip-production.aspx. 
  24. ↑ "Intel says not to expect mainstream 10nm chips until 2H19". 2018-07-28. https://arstechnica.com/gadgets/2018/07/intel-says-not-to-expect-mainstream-10nm-chips-until-2h19/. 
  25. ↑ "Intel's First 10nm Processor Lands In China". 2018-05-15. https://www.tomshardware.com/news/intel-10nm-processor-core-i3-8121u,37054.html. 
  26. ↑ "VLSI 2018: Samsung's 11nm nodelet, 11LPP" (in en-US). 2018-06-30. https://fuse.wikichip.org/news/1425/vlsi-2018-samsungs-11nm-11lpp/. 
  27. ↑ 27.0 27.1 27.2 27.3 27.4 "VLSI 2018: Samsung's 8nm 8LPP, a 10nm extension" (in en-US). 2018-07-01. https://fuse.wikichip.org/news/1443/vlsi-2018-samsungs-8nm-8lpp-a-10nm-extension/. 
  28. ↑ "Nvidia confirms Samsung 8nm process for RTX 3090, RTX 3080, and RTX 3070 | PC Gamer". https://www.pcgamer.com/amp/nvidia-ampere-samsung-8nm-process/. 
  29. ↑ "NVIDIA GeForce RTX 30 Ampere GPU Deep-Dive, Full Specs, Thermals, Power & Performance Detailed". September 4, 2020. https://wccftech.com/nvidia-geforce-rtx-30-series-ampere-graphics-cards-deep-dive/. 
  30. ↑ Demerjian, Charlie (2018-08-02). "Intel guts 10nm to get it out the door". SemiAccurate. https://semiaccurate.com/2018/08/02/intel-guts-10nm-to-get-it-out-the-door/. 
  31. ↑ Schor, David (2019-04-16). "TSMC Announces 6-Nanometer Process" (in en-US). https://fuse.wikichip.org/news/2261/tsmc-announces-6-nanometer-process/. 
  32. ↑ "Intel 10nm density is 2.7X improved over its 14nm node" (in en-GB). HEXUS. https://hexus.net/tech/news/cpu/119699-intel-10nm-density-27x-improved-14nm-node/. 
  33. ↑ Bohr, Mark (2017-03-28). "Let's Clear Up the Node Naming Mess". https://newsroom.intel.com/editorials/lets-clear-up-node-naming-mess/. 
  34. ↑ Cutress, Dr Ian. "Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!". https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros. 
  35. ↑ "Intel Details Cannonlake's Advanced 10nm FinFET Node, Claims Full Generation Lead Over Rivals". 2017-03-28. http://hothardware.com/news/intel-details-advanced-10nm-node. 
  36. ↑ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report". https://www.semiconductors.org/wp-content/uploads/2018/06/0_2015-ITRS-2.0-Executive-Report-1.pdf. 
  37. ↑ Jones, Scotten. "14nm 16nm 10nm and 7nm - What we know now". https://semiwiki.com/semiconductor-manufacturers/intel/6713-14nm-16nm-10nm-and-7nm-what-we-know-now/. 
  38. ↑ "Qualcomm Snapdragon 835 First to 10 nm". http://www.techinsights.com/about-techinsights/overview/blog/qualcomm-snapdragon-835-first-to-10-nm/. "Samsung 10LPE process" 
  39. ↑ "10 nm lithography process". https://en.wikichip.org/wiki/10_nm_lithography_process. 
  40. ↑ Jones, Scotten. "Exclusive - GLOBALFOUNDRIES discloses 7nm process detail". https://semiwiki.com/semiconductor-manufacturers/globalfoundries/6879-exclusive-globalfoundries-discloses-7nm-process-detail/. 
  41. ↑ Shilov, Anton. "Samsung's 8LPP Process Technology Qualified, Ready for Production". https://www.anandtech.com/show/11946/samsungs-8lpp-process-technology-qualified-ready-for-production. 
  42. ↑ Mellor, Chris (13 April 2020), "Why DRAM is stuck in a 10nm trap", blocksandfiles.com, https://blocksandfiles.com/2020/04/13/dram-is-stuck-in-a-10nm-process-trap/ 
  43. ↑ Shilov, Anton (21 March 2019), "Samsung Develops Smaller DDR4 Dies Using 3rd Gen 10nm-Class Process Tech", www.anandtech.com, https://www.anandtech.com/show/14118/samsung-develops-8-gb-drams-using-3rd-gen-10nmclass-process-technology 
  44. ↑ Samsung Develops Industry's First 3rd-generation 10nm-Class DRAM for Premium Memory Applications, Samsung, 25 Mar 2019, https://news.samsung.com/my/samsung-develops-industrys-first-3rd-generation-10nm-class-dram-for-premium-memory-applications 
  45. ↑ Samsung Announces Industry's First EUV DRAM with Shipment of First Million Modules, Samsung, 25 Mar 2020, https://news.samsung.com/my/samsung-announces-industrys-first-euv-dram-with-shipment-of-first-million-modules 
  46. ↑ Choe, Jeongdong (18 Feb 2021), "Teardown: Samsung's D1z DRAM with EUV Lithography", www.eetimes.com, https://www.eetimes.com/teardown-samsungs-d1z-dram-with-euv-lithography/ 
  47. ↑ Micron Delivers Industry's First 1α DRAM Technology, Micron, 26 Jan 2021, https://investors.micron.com/news-releases/news-release-details/micron-delivers-industrys-first-1a-dram-technology 


Preceded by
14 nm 		MOSFET manufacturing processes Succeeded by
7 nm




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