Engineering:Clock feedthrough

In analog electronics, Clock feedthrough is the result of the coupling between control signals on the analog switch and analog signal passing through the switch. In digital electronics, clock feedthrough is the coupling of the clock signal to the nodes where coupling is not intended. Such coupling happens because of the gate-to-source capacitance, interconnects parasitic capacitance or because of the substrate coupling. Clock feedthrough is generally considered harmful. Methods to reduce clock feedthrough include:

• Slew rate reduction of the clock signal, usually by the resistor in series with the controlled gate.
• Reduction of the voltage swing of the clock signal
• Reduction of the interconnects parasitic capacitance by rerouting interconnects
• Increase of the substrate resistance by the buried N-well insulation, shallow trench isolation, or back-grinding
• Use of the differential clocks to spread clock feedthrough signal across large bandwidth
• Use of the differential signal lines where clock feedthrough appears as common-mode signal

References

Clock feedthrough in CMOS analog transmission gate switches by Eby G. Friedman

Clock feedthrough example in digital circuits

Clock feedthrough compensation with phase slope control in SC circuits

Clock feedthrough cancellation with compensation for the current-switched systems